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AIDA-2020 TLU - Hardware
Commit a648eb8d authored by David Cussans's avatar David Cussans
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Comitting updated schematics for fmc vc . Adding a diagram illustrating… 

Comitting updated schematics for fmc vc . Adding a diagram illustrating coincidence logic. Adding simulation scripts
parent 5ab3f84e
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Showing with 66517 additions and 54262 deletions
Cadence/adw/shoppingCart.xml
View file @ a648eb8d
...@@ -56,4 +56,38 @@ ...@@ -56,4 +56,38 @@
<property name="PACK_TYPE" value="SC88"/> <property name="PACK_TYPE" value="SC88"/>
<property name="TYPE" value="PRTR5V0U4Y"/> <property name="TYPE" value="PRTR5V0U4Y"/>
</component> </component>
<component cell="con19p" library="cnconnector" partname="CON19P" partno="HDMI-19-01-X-SM" quantity="1" >
<property name="TYPE" value="HDMI-19-01-X-SM"/>
</component>
<component cell="common_mode_line_filter" library="cndiscrete" partname="COMMON_MODE_LINE_FILTER" partno="744231091" quantity="1" >
<property name="PACK_TYPE" value="4312"/>
<property name="TYPE" value="744231091"/>
<property name="VALUE" value="90ohm"/>
</component>
<component cell="res_array_x4" library="cnpassive" partname="RES_ARRAY_X4" partno="TC164-FR-##47RL" quantity="1" >
<property name="PACK_TYPE" value="1206_TC164"/>
<property name="TOL" value="1%"/>
<property name="VALUE" value="47"/>
</component>
<component cell="capn4i" library="cnpassive" partname="CAPN4I" partno="GNM214B11C105MA01D" quantity="1" >
<property name="DIELECTRIC" value="X5R"/>
<property name="TYPE" value="GNM21"/>
<property name="VALUE" value="1uF"/>
<property name="VOLTAGE" value="16V"/>
</component>
<component cell="tps786xx" library="cnlinear" partname="TPS786XX" partno="TPS78633DCQ" quantity="1" >
<property name="PACK_TYPE" value="SOT223"/>
<property name="TYPE" value="TPS78633DCQ"/>
</component>
<component cell="plemo2ci" library="cnconnector" partname="PLEMO2CI" partno="EPG.00.302.NLN" quantity="1" >
<property name="TYPE" value="EPG.00.302.NLN"/>
</component>
<component cell="24aa025e48" library="cnmemory" partname="24AA025E48" partno="24AA025E48T-I/SN" quantity="1" >
<property name="PACK_TYPE" value="SOIC"/>
<property name="TYPE" value="24AA025E48T-I/SN"/>
</component>
<component cell="zener" library="cndiscrete" partname="ZENER" partno="BZT52-C3V6" quantity="1" >
<property name="PACK_TYPE" value="SOD123-CA"/>
<property name="TYPE" value="BZT52-C3V6"/>
</component>
</sc:shoppingCart> </sc:shoppingCart>
Cadence/fmc_tlu_diode_clamp_b.cpm 0 → 100644
View file @ a648eb8d
{ Machine generated file created by SPI }
{ Last modified was 15:25:40 Wednesday, May 18, 2016 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/fmc_tlu_diode_clamp_b/physical'
design_name 'fmc_tlu_diode_clamp_b'
design_library 'fmc_tlu_v1_lib'
library 'fmc_tlu_v1_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cnconnector' 'cninterface' 'cnpower' 'cnlinear' 'cnpassive' 'cndiscrete' 'standard' 'cds_analogue' 'cn100e' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnfast' 'cnmemory' 'uob_hep_pc036a_lib' 'cds_connectors' 'cds_special' 'cnmech' 'cnspecial'
temp_dir 'temp'
cpm_version '16.3'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
cdsprop_file ''
physical_path './worklib/fmc_tlu_diode_clamp_b/physical'
trapezoidal_angle_in_degree '90.000000'
session_name 'ProjectMgr8446'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_TOGGLE 'ON'
LOGIC_GRID_SIZE '0.0500'
SYMBOL_GRID_TOGGLE 'ON'
DOC_GRID_TOGGLE 'ON'
DOC_GRID_SIZE '0.0500'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME 'Generic PostScript Printer'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL
START_PKGRXL
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
GEN_SUBDESIGN
force_subdesign 'fmc_tlu_cfd' 'fmc_tlu_vsupply5v'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '0'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_v1a_66_gloss4a.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file './worklib/fmc_tlu_toplevel_b/bom/fmc_tlu_v1a.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Colon :'
use_filters '0'
last_callout_file ''
last_variant ''
END_BOMHDL
START_PDF
CURRENTPDFVIEWER '0'
CURRENTPDFVIEWERPATH 'Default'
END_PDF
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
Cadence/fmc_tlu_v1c.cpm
View file @ a648eb8d
{ Machine generated file created by SPI } { Machine generated file created by SPI }
{ Last modified was 14:45:25 Thursday, April 21, 2016 } { Last modified was 15:16:35 Friday, May 20, 2016 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by } { NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. } { SPI, your modifications will be overwritten. }
...@@ -40,6 +40,7 @@ electrical_constraints 'ON' ...@@ -40,6 +40,7 @@ electrical_constraints 'ON'
overwrite_constraints 'OFF' overwrite_constraints 'OFF'
GEN_SUBDESIGN GEN_SUBDESIGN
force_subdesign 'fmc_tlu_cfd' 'fmc_tlu_vsupply5v' force_subdesign 'fmc_tlu_cfd' 'fmc_tlu_vsupply5v'
f2b_overwrite_constraints 'ON'
END_PKGRXL END_PKGRXL
START_DESIGNSYNC START_DESIGNSYNC
...@@ -50,10 +51,11 @@ create_user_prop 'NO' ...@@ -50,10 +51,11 @@ create_user_prop 'NO'
run_packager 'YES' run_packager 'YES'
run_netrev 'YES' run_netrev 'YES'
backannotate_forward 'NO' backannotate_forward 'NO'
last_board_file 'fmc_tlu_v1a_66_gloss4a.brd' last_board_file 'fmc_tlu_v1c_67.brd'
run_feedback 'YES' run_feedback 'YES'
run_genfeedformat 'YES' run_genfeedformat 'YES'
backannotate_feedback 'NO' backannotate_feedback 'NO'
show_report 'NO'
END_DESIGNSYNC END_DESIGNSYNC
START_BOMHDL START_BOMHDL
......
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/fmc_tlu_diode_clamp_b.dcf
View file @ a648eb8d
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
( 16.6 ) ( 16.6 )
) )
( revisionNumber ( revisionNumber
( logicalViewRevNum 2 ) ( logicalViewRevNum 4 )
( physicalViewRevNum 0 ) ( physicalViewRevNum 0 )
( otherViewRevNum 0 ) ( otherViewRevNum 0 )
) )
...@@ -544,32 +544,38 @@ ...@@ -544,32 +544,38 @@
( objectFlag fObjectAlias ) ( objectFlag fObjectAlias )
( objectStatus "page1_gnd_signal" ) ( objectStatus "page1_gnd_signal" )
) )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig0" ( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig4_p"
( objectStatus "sig0" ) ( objectStatus "sig4_p" )
) )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig1" ( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig4_n"
( objectStatus "sig1" ) ( objectStatus "sig4_n" )
) )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig2" ( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):vclamp"
( objectStatus "sig2" ) ( objectStatus "vclamp" )
) )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig3" ( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig0_n"
( objectStatus "sig3" ) ( objectStatus "sig0_n" )
) )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig4" ( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig0_p"
( objectStatus "sig4" ) ( objectStatus "sig0_p" )
) )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig5" ( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig1_n"
( objectStatus "sig5" ) ( objectStatus "sig1_n" )
) )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig6" ( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig1_p"
( objectStatus "sig6" ) ( objectStatus "sig1_p" )
) )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig7" ( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig2_n"
( objectStatus "sig7" ) ( objectStatus "sig2_n" )
) )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):vclamp" ( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig2_p"
( objectStatus "vclamp" ) ( objectStatus "sig2_p" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig3_n"
( objectStatus "sig3_n" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig3_p"
( objectStatus "sig3_p" )
) )
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i9" ( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i9"
( attribute "CDS_LIB" "cnpassive" ( attribute "CDS_LIB" "cnpassive"
...@@ -702,6 +708,145 @@ ...@@ -702,6 +708,145 @@
( pin "vcc" ( pin "vcc"
) )
) )
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i58"
( attribute "CDS_LIB" "cnpassive"
( Origin gPackager )
)
( attribute "PACK_TYPE" "0603"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "1"
( Origin gFrontEnd )
)
( attribute "SIZE" "1"
( Origin gFrontEnd )
)
( attribute "VALUE" "100NF"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "VOLTAGE" "16V"
( Units "uVoltage" "V" 1.000000)
( Origin gFrontEnd )
)
( attribute "XY" "(2575,-1875)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "CAPCERSMDCL2"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "CAPCERSMDCL2_0603-100NF,16V"
( Origin gPackager )
)
( objectStatus "PAGE1_I58" )
( pin "a(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
( pin "b(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i70"
( attribute "CDS_LIB" "cndiscrete"
( Origin gPackager )
)
( attribute "LOCATION" "D3"
( Origin gPackager )
)
( attribute "PACK_TYPE" "SOT23"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "0"
( Origin gFrontEnd )
)
( attribute "TYPE" "USBLC6-2SC6"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "XY" "(5025,175)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "USBLC6-2"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "USBLC6-2SC6"
( Origin gPackager )
)
( objectStatus "PAGE1_I70" )
( pin "gnd"
)
( pin "\i/o1\(0)"
)
( pin "\i/o1\(1)"
)
( pin "\i/o2\(0)"
)
( pin "\i/o2\(1)"
)
( pin "vbus"
)
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i67"
( attribute "CDS_LIB" "cnpassive"
( Origin gPackager )
)
( attribute "PACK_TYPE" "0603"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "1"
( Origin gFrontEnd )
)
( attribute "SIZE" "1"
( Origin gFrontEnd )
)
( attribute "VALUE" "100NF"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "VOLTAGE" "16V"
( Units "uVoltage" "V" 1.000000)
( Origin gFrontEnd )
)
( attribute "XY" "(5975,0)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "CAPCERSMDCL2"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "CAPCERSMDCL2_0603-100NF,16V"
( Origin gPackager )
)
( objectStatus "PAGE1_I67" )
( pin "a(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
( pin "b(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
)
) )
) )
) )
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/fmc_tlu_diode_clamp_b.dcf,1
View file @ a648eb8d
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
( 16.6 ) ( 16.6 )
) )
( revisionNumber ( revisionNumber
( logicalViewRevNum 0 ) ( logicalViewRevNum 1 )
( physicalViewRevNum 0 ) ( physicalViewRevNum 0 )
( otherViewRevNum 0 ) ( otherViewRevNum 0 )
) )
......
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/fmc_tlu_diode_clamp_b.dcf,2
View file @ a648eb8d
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
( 16.6 ) ( 16.6 )
) )
( revisionNumber ( revisionNumber
( logicalViewRevNum 1 ) ( logicalViewRevNum 2 )
( physicalViewRevNum 0 ) ( physicalViewRevNum 0 )
( otherViewRevNum 0 ) ( otherViewRevNum 0 )
) )
...@@ -536,6 +536,172 @@ ...@@ -536,6 +536,172 @@
( allRules ) ( allRules )
( design "fmc_tlu_diode_clamp_b" ( design "fmc_tlu_diode_clamp_b"
) )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):gnd_signal"
( alias ( signalRef "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_gnd_signal") )
( objectStatus "gnd_signal" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_gnd_signal"
( objectFlag fObjectAlias )
( objectStatus "page1_gnd_signal" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig0"
( objectStatus "sig0" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig1"
( objectStatus "sig1" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig2"
( objectStatus "sig2" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig3"
( objectStatus "sig3" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig4"
( objectStatus "sig4" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig5"
( objectStatus "sig5" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig6"
( objectStatus "sig6" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig7"
( objectStatus "sig7" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):vclamp"
( objectStatus "vclamp" )
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i9"
( attribute "CDS_LIB" "cnpassive"
( Origin gPackager )
)
( attribute "PACK_TYPE" "0603"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "1"
( Origin gFrontEnd )
)
( attribute "SIZE" "1"
( Origin gFrontEnd )
)
( attribute "VALUE" "100NF"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "VOLTAGE" "16V"
( Units "uVoltage" "V" 1.000000)
( Origin gFrontEnd )
)
( attribute "XY" "(2175,-1875)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "CAPCERSMDCL2"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "CAPCERSMDCL2_0603-100NF,16V"
( Origin gPackager )
)
( objectStatus "PAGE1_I9" )
( pin "a(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
( pin "b(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i55"
( attribute "CDS_LIB" "cndiscrete"
( Origin gPackager )
)
( attribute "PACK_TYPE" "SC88"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "0"
( Origin gFrontEnd )
)
( attribute "TYPE" "PRTR5V0U4Y"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "XY" "(1025,-250)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "PRTR5V0U4Y"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "PRTR5V0U4Y"
( Origin gPackager )
)
( objectStatus "PAGE1_I55" )
( pin "esd1"
)
( pin "esd2"
)
( pin "esd3"
)
( pin "esd4"
)
( pin "gnd"
)
( pin "vcc"
)
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i56"
( attribute "CDS_LIB" "cndiscrete"
( Origin gPackager )
)
( attribute "PACK_TYPE" "SC88"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "0"
( Origin gFrontEnd )
)
( attribute "TYPE" "PRTR5V0U4Y"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "XY" "(1050,-2450)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "PRTR5V0U4Y"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "PRTR5V0U4Y"
( Origin gPackager )
)
( objectStatus "PAGE1_I56" )
( pin "esd1"
)
( pin "esd2"
)
( pin "esd3"
)
( pin "esd4"
)
( pin "gnd"
)
( pin "vcc"
)
)
) )
) )
) )
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/page1.cpc
View file @ a648eb8d
...@@ -43,6 +43,30 @@ ...@@ -43,6 +43,30 @@
#ISCELL #ISCELL
standard gnd_signal * standard gnd_signal *
page1_i57 page1_i57
#CELL
cnpassive capcersmdcl2 *
page1_i58
#ISCELL
standard gnd_signal *
page1_i59
#ISCELL
standard inport *
page1_i64
#ISCELL
standard inport *
page1_i65
#CELL
cnpassive capcersmdcl2 *
page1_i67
#ISCELL
standard gnd_signal *
page1_i68
#CELL
cndiscrete usblc6-2 *
page1_i70
#ISCELL
standard gnd_signal *
page1_i71
#CELL #CELL
cnpassive capcersmdcl2 * cnpassive capcersmdcl2 *
page1_i9 page1_i9
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/page1.csv
View file @ a648eb8d
...@@ -2,139 +2,181 @@ FILE_TYPE = CONNECTIVITY; ...@@ -2,139 +2,181 @@ FILE_TYPE = CONNECTIVITY;
{Allegro Design Entry HDL 16.6-S055 (v16-6-112EP) 8/13/2015} {Allegro Design Entry HDL 16.6-S055 (v16-6-112EP) 8/13/2015}
"PAGE_NUMBER" = 1; "PAGE_NUMBER" = 1;
0"NC"; 0"NC";
1"GND_SIGNAL\g"; 1"SIG4_N";
2"GND_SIGNAL\g"; 2"SIG4_P";
3"GND_SIGNAL\g"; 3"VCLAMP";
4"SIG4"; 4"GND_SIGNAL\g";
5"VCLAMP"; 5"GND_SIGNAL\g";
6"SIG7"; 6"SIG3_N";
7"SIG6"; 7"SIG1_N";
8"SIG5"; 8"VCLAMP";
9"SIG3"; 9"SIG3_P";
10"SIG2"; 10"SIG2_N";
11"SIG1"; 11"SIG2_P";
12"SIG0"; 12"SIG1_P";
13"SIG0_N";
14"SIG0_P";
15"GND_SIGNAL\g";
16"GND_SIGNAL\g";
17"GND_SIGNAL\g";
18"GND_SIGNAL\g";
%"INPORT" %"INPORT"
"1","(-850,550)","0","standard","I24"; "1","(-850,550)","0","standard","I24";
; ;
CDS_LIB"standard" OFFPAGE"TRUE"
OFFPAGE"TRUE"; CDS_LIB"standard";
"A" "A"
VHDL_PORT"IN" HDL_PORT"IN"
HDL_PORT"IN"12; VHDL_PORT"IN"14;
%"INPORT" %"INPORT"
"1","(-850,0)","0","standard","I25"; "1","(-850,0)","0","standard","I25";
; ;
CDS_LIB"standard" OFFPAGE"TRUE"
OFFPAGE"TRUE"; CDS_LIB"standard";
"A" "A"
VHDL_PORT"IN" HDL_PORT"IN"
HDL_PORT"IN"11; VHDL_PORT"IN"13;
%"INPORT" %"INPORT"
"1","(-850,-550)","0","standard","I26"; "1","(-850,-550)","0","standard","I26";
; ;
CDS_LIB"standard" OFFPAGE"TRUE"
OFFPAGE"TRUE"; CDS_LIB"standard";
"A" "A"
VHDL_PORT"IN" HDL_PORT"IN"
HDL_PORT"IN"10; VHDL_PORT"IN"12;
%"INPORT" %"INPORT"
"1","(-850,-1100)","0","standard","I27"; "1","(-850,-1100)","0","standard","I27";
; ;
CDS_LIB"standard" OFFPAGE"TRUE"
OFFPAGE"TRUE"; CDS_LIB"standard";
"A" "A"
VHDL_PORT"IN" HDL_PORT"IN"
HDL_PORT"IN"9; VHDL_PORT"IN"7;
%"INPORT" %"INPORT"
"1","(-850,-1650)","0","standard","I28"; "1","(-850,-1650)","0","standard","I28";
; ;
CDS_LIB"standard" OFFPAGE"TRUE"
OFFPAGE"TRUE"; CDS_LIB"standard";
"A" "A"
VHDL_PORT"IN" HDL_PORT"IN"
HDL_PORT"IN"4; VHDL_PORT"IN"11;
%"INPORT" %"INPORT"
"1","(-850,-2200)","0","standard","I29"; "1","(-850,-2200)","0","standard","I29";
; ;
CDS_LIB"standard" OFFPAGE"TRUE"
OFFPAGE"TRUE"; CDS_LIB"standard";
"A" "A"
VHDL_PORT"IN" HDL_PORT"IN"
HDL_PORT"IN"8; VHDL_PORT"IN"10;
%"INPORT" %"INPORT"
"1","(-850,-2750)","0","standard","I30"; "1","(-850,-2750)","0","standard","I30";
; ;
CDS_LIB"standard" OFFPAGE"TRUE"
OFFPAGE"TRUE"; CDS_LIB"standard";
"A" "A"
VHDL_PORT"IN" HDL_PORT"IN"
HDL_PORT"IN"7; VHDL_PORT"IN"9;
%"INPORT" %"INPORT"
"1","(-850,-3300)","0","standard","I31"; "1","(-850,-3300)","0","standard","I31";
; ;
CDS_LIB"standard" OFFPAGE"TRUE"
OFFPAGE"TRUE"; CDS_LIB"standard";
"A" "A"
VHDL_PORT"IN" HDL_PORT"IN"
HDL_PORT"IN"6; VHDL_PORT"IN"6;
%"GND_SIGNAL" %"GND_SIGNAL"
"1","(2125,-2175)","0","standard","I42"; "1","(2125,-2175)","0","standard","I42";
; ;
HDL_POWER"GND_SIGNAL" CDS_LIB"standard"
BODY_TYPE"PLUMBING" BODY_TYPE"PLUMBING"
CDS_LIB"standard"; HDL_POWER"GND_SIGNAL";
"GND"3; "GND"16;
%"GND_SIGNAL" %"GND_SIGNAL"
"1","(575,-525)","0","standard","I53"; "1","(575,-525)","0","standard","I53";
; ;
HDL_POWER"GND_SIGNAL" HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING" BODY_TYPE"PLUMBING"
CDS_LIB"standard"; CDS_LIB"standard";
"GND"2; "GND"17;
%"IOPORT" %"IOPORT"
"1","(2850,-1450)","0","standard","I54"; "1","(2850,-1450)","0","standard","I54";
; ;
CDS_LIB"standard" OFFPAGE"TRUE"
OFFPAGE"TRUE"; CDS_LIB"standard";
"A" "A"
HDL_PORT"INOUT" VHDL_PORT"INOUT"
VHDL_PORT"INOUT"5; HDL_PORT"INOUT"8;
%"PRTR5V0U4Y" %"PRTR5V0U4Y"
"1","(1025,-250)","0","cndiscrete","I55"; "1","(1025,-250)","0","cndiscrete","I55";
; ;
$LOCATION"D?"
CDS_LIB"cndiscrete"
TYPE"PRTR5V0U4Y" TYPE"PRTR5V0U4Y"
PACK_TYPE"SC88"; $LOCATION"D?"
"ESD4"12; PACK_TYPE"SC88"
"ESD1"11; CDS_LIB"cndiscrete";
"ESD2"10; "ESD4"14;
"GND"2; "ESD1"13;
"ESD3"9; "ESD2"12;
"VCC"5; "GND"17;
"ESD3"7;
"VCC"8;
%"PRTR5V0U4Y" %"PRTR5V0U4Y"
"1","(1050,-2450)","0","cndiscrete","I56"; "1","(1050,-2450)","0","cndiscrete","I56";
; ;
$LOCATION"D?" $LOCATION"D?"
TYPE"PRTR5V0U4Y"
PACK_TYPE"SC88" PACK_TYPE"SC88"
TYPE"PRTR5V0U4Y"
CDS_LIB"cndiscrete"; CDS_LIB"cndiscrete";
"ESD4"4; "ESD4"11;
"ESD1"8; "ESD1"10;
"ESD2"7; "ESD2"9;
"GND"1; "GND"15;
"ESD3"6; "ESD3"6;
"VCC"5; "VCC"8;
%"GND_SIGNAL" %"GND_SIGNAL"
"1","(600,-2725)","0","standard","I57"; "1","(600,-2725)","0","standard","I57";
; ;
HDL_POWER"GND_SIGNAL" CDS_LIB"standard"
BODY_TYPE"PLUMBING" BODY_TYPE"PLUMBING"
CDS_LIB"standard"; HDL_POWER"GND_SIGNAL";
"GND"1; "GND"15;
%"CAPCERSMDCL2" %"CAPCERSMDCL2"
"1","(2175,-1875)","1","cnpassive","I9"; "1","(2575,-1875)","1","cnpassive","I58";
;
VALUE"100NF"
VOLTAGE"16V"
$LOCATION"C?"
SIZE"1"
CDS_LIB"cnpassive"
PACK_TYPE"0603";
"A <SIZE-1..0>\NAC"
$PN"#"18;
"B <SIZE-1..0>\NAC"
$PN"#"8;
%"GND_SIGNAL"
"1","(2525,-2175)","0","standard","I59";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_POWER"GND_SIGNAL";
"GND"18;
%"INPORT"
"1","(3200,275)","0","standard","I64";
;
CDS_LIB"standard"
OFFPAGE"TRUE";
"A"
VHDL_PORT"IN"
HDL_PORT"IN"2;
%"INPORT"
"1","(3200,75)","0","standard","I65";
;
CDS_LIB"standard"
OFFPAGE"TRUE";
"A"
VHDL_PORT"IN"
HDL_PORT"IN"1;
%"CAPCERSMDCL2"
"1","(5975,0)","1","cnpassive","I67";
; ;
PACK_TYPE"0603" PACK_TYPE"0603"
CDS_LIB"cnpassive" CDS_LIB"cnpassive"
...@@ -142,8 +184,48 @@ SIZE"1" ...@@ -142,8 +184,48 @@ SIZE"1"
$LOCATION"C?" $LOCATION"C?"
VOLTAGE"16V" VOLTAGE"16V"
VALUE"100NF"; VALUE"100NF";
"B <SIZE-1..0>\NAC"
$PN"#"5;
"A <SIZE-1..0>\NAC" "A <SIZE-1..0>\NAC"
$PN"#"4;
"B <SIZE-1..0>\NAC"
$PN"#"3; $PN"#"3;
%"GND_SIGNAL"
"1","(5925,-300)","0","standard","I68";
;
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"GND"4;
%"USBLC6-2"
"1","(5025,175)","0","cndiscrete","I70";
;
CDS_LIB"cndiscrete"
$LOCATION"D3"
TYPE"USBLC6-2SC6"
PACK_TYPE"SOT23";
"I/O1<1>"2;
"I/O1<0>"2;
"GND"5;
"I/O2<0>"1;
"I/O2<1>"1;
"VBUS"3;
%"GND_SIGNAL"
"1","(4675,-75)","0","standard","I71";
;
CDS_LIB"standard"
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING";
"GND"5;
%"CAPCERSMDCL2"
"1","(2175,-1875)","1","cnpassive","I9";
;
VALUE"100NF"
VOLTAGE"16V"
$LOCATION"C?"
SIZE"1"
CDS_LIB"cnpassive"
PACK_TYPE"0603";
"A <SIZE-1..0>\NAC"
$PN"#"16;
"B <SIZE-1..0>\NAC"
$PN"#"8;
END. END.
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/pc.db
View file @ a648eb8d
-- pcdb file, Rev:1.0 written by Allegro Design Entry HDL 16.6-S055 (v16-6-112EP) 8/13/2015 on Fri Apr 22 09:05:35 2016 -- pcdb file, Rev:1.0 written by Allegro Design Entry HDL 16.6-S055 (v16-6-112EP) 8/13/2015 on Wed May 18 10:06:29 2016
#ISCELL #ISCELL
bris_cds_standard a3-2000 * bris_cds_standard a3-2000 *
* *
...@@ -44,6 +44,30 @@ ...@@ -44,6 +44,30 @@
#ISCELL #ISCELL
standard gnd_signal * standard gnd_signal *
page1_i57 page1_i57
#CELL
cnpassive capcersmdcl2 *
page1_i58
#ISCELL
standard gnd_signal *
page1_i59
#ISCELL
standard inport *
page1_i64
#ISCELL
standard inport *
page1_i65
#CELL
cnpassive capcersmdcl2 *
page1_i67
#ISCELL
standard gnd_signal *
page1_i68
#CELL
cndiscrete usblc6-2 *
page1_i70
#ISCELL
standard gnd_signal *
page1_i71
#CELL #CELL
cnpassive capcersmdcl2 * cnpassive capcersmdcl2 *
page1_i9 page1_i9
Cadence/worklib/fmc_tlu_toplevel_c/packaged/pxl.state
View file @ a648eb8d
This source diff could not be displayed because it is too large. You can view the blob instead.
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/module_order.dat
View file @ a648eb8d
...@@ -2,17 +2,16 @@ Version 15.0 ...@@ -2,17 +2,16 @@ Version 15.0
START_MODULEORDER START_MODULEORDER
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1) 0 1 1 3 0 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1) 0 1 1 3 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page1_i2@fmc_tlu_v1_lib.pc036a_fmc_lpc_connector(sch_1) 0 0 4 1 0 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page1_i2@fmc_tlu_v1_lib.pc036a_fmc_lpc_connector(sch_1) 0 0 4 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page4_i62@fmc_tlu_v1_lib.fmc_tlu_diode_clamp(sch_1) 0 1 5 1 0 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i35@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 5 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page4_i63@fmc_tlu_v1_lib.fmc_tlu_diode_clamp(sch_1) 0 0 6 1 1 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i36@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 6 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page4_i64@fmc_tlu_v1_lib.fmc_tlu_diode_clamp(sch_1) 0 0 7 1 1 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i37@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 7 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i35@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 8 1 0 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i38@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 8 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i36@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 9 1 1 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1) 0 0 9 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i37@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 10 1 1 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i29@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 10 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i38@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 11 1 1 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i30@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 11 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1) 0 0 12 1 0 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i31@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 12 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i29@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 13 1 0 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i32@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 13 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i30@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 14 1 1 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i55@fmc_tlu_v1_lib.fmc_tlu_vsupply5v(sch_1) 0 0 14 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i31@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 15 1 1 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page4_i1@fmc_tlu_v1_lib.fmc_tlu_hdmi_dut_connector(sch_1) 0 1 15 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i32@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 16 1 1 @fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page4_i1@fmc_tlu_v1_lib.fmc_tlu_hdmi_dut_connector(sch_1):page1_i78@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1) 0 0 16 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i55@fmc_tlu_v1_lib.fmc_tlu_vsupply5v(sch_1) 0 0 17 1 0
END_MODULEORDER END_MODULEORDER
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