replaced timestamp counter with high/low parts with single 48-bit counter. seems…

replaced timestamp counter with high/low parts with single 48-bit counter. seems to eliminate bug with bit flipping high prematurely. also gives shorter and easier to read code

replaced timestamp counter with high/low parts with single 48-bit counter. seems…
replaced timestamp counter with high/low parts with single 48-bit counter. seems to eliminate bug with bit flipping high prematurely. also gives shorter and easier to read code
02df9202 · David Cussans · 82d99e73 · 02df9202
Commit 02df9202 authored Oct 30, 2015 by David Cussans
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triggerLogic_rtl.vhd firmware/hdl/common/triggerLogic_rtl.vhd +2 -2

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--- a/firmware/hdl/common/triggerLogic_rtl.vhd
+++ b/firmware/hdl/common/triggerLogic_rtl.vhd
@@ -175,9 +175,9 @@ BEGIN
  s_status_to_ipbus(5) <= s_external_veto_word;
  s_external_veto_word(0) <= veto_i;
  s_external_veto_word(g_IPBUS_WIDTH-1 downto 1) <= (others=>'0');
--  s_status_to_ipbus(6) <= s_PulseStretchWord;
+  s_status_to_ipbus(6) <= s_PulseStretchWord;
  s_status_to_ipbus(7) <= s_PulseDelayWord;
-  s_status_to_ipbus(6) <= std_logic_vector(s_aux_trigger_counter);-- Bodge
+  -- s_status_to_ipbus(6) <= std_logic_vector(s_aux_trigger_counter);-- Bodge

  -- purpose: Delay pulse that loads trigger pattern by one cycle of IPBus clk.
  -- type   : combinational