Commit 404f85fd authored by Paolo Baesso's avatar Paolo Baesso

Added script folder

parent 0a069cdf
......@@ -6,3 +6,4 @@
/Enclustra_tests/
*.py~
*.pyc
.svn/*
{
"protocol": "sftp",
"host": "fortis.phy.bris.ac.uk",
"port": 22,
"user": "phpgb",
"pass": "",
"promptForPass": true,
"remote": "/users/phpgb/",
"local": "",
"agent": "",
"privatekey": "",
"passphrase": "",
"hosthash": "",
"ignorehost": true,
"connTimeout": 10000,
"keepalive": 10000,
"keyboardInteractive": false,
"watch": [],
"watchTimeout": 500
}
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# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
class AD5665R:
#Class to configure the DAC modules
def __init__(self, i2c, slaveaddr=0x1F):
self.i2c = i2c
self.slaveaddr = slaveaddr
def setIntRef(self, intRef=False, verbose=False):
mystop=True
if intRef:
cmdDAC= [0x38,0x00,0x01]
else:
cmdDAC= [0x38,0x00,0x00]
self.i2c.write( self.slaveaddr, cmdDAC, mystop)
if verbose:
print "DAC int ref:", intRef
def writeDAC(self, dacCode, channel, verbose=False):
#Vtarget is the required voltage, channel is the DAC channel to target
#intRef indicates whether to use the external voltage reference (True)
#or the internal one (False).
print "\tDAC value:" , hex(dacCode)
if channel<0 or channel>7:
print "writeDAC ERROR: channel",channel,"not in range 0-7 (bit mask)"
return -1
if dacCode<0:
print "writeDAC ERROR: value",dacCode,"<0. Default to 0"
dacCode=0
elif dacCode>0xFFFF :
print "writeDAC ERROR: value",dacCode,">0xFFFF. Default to 0xFFFF"
dacCode=0xFFFF
sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
print "\tWriting DAC string:", sequence
mystop= False
self.i2c.write( self.slaveaddr, sequence, mystop)
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import time
#import miniTLU
from si5345 import si5345
from AD5665R import AD5665R
from PCA9539PW import PCA9539PW
from E24AA025E48T import E24AA025E48T
manager = uhal.ConnectionManager("file://./TLUconnection.xml")
hw = manager.getDevice("tlu")
# hw.getNode("A").write(255)
reg = hw.getNode("version").read()
hw.dispatch()
print "CHECK REG= ", hex(reg)
# #First I2C core
print ("Instantiating master I2C core:")
master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
master_I2C.state()
#
# #######################################
enableCore= True #Only need to run this once, after power-up
if (enableCore):
mystop=True
print " Write RegDir to set I/O[7] to output:"
myslave= 0x21
mycmd= [0x01, 0x7F]
nwords= 1
master_I2C.write(myslave, mycmd, mystop)
mystop=False
mycmd= [0x01]
master_I2C.write(myslave, mycmd, mystop)
res= master_I2C.read( myslave, nwords)
print "\tPost RegDir: ", res
# #######################################
#
# time.sleep(0.1)
# #Read the EPROM
# mystop=False
# nwords=6
# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
# myaddr= [0xfa]#0xfa
# master_I2C.write( myslave, myaddr, mystop)
# #res= master_I2C.read( 0x50, 6)
# res= master_I2C.read( myslave, nwords)
# print " PCB EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
# #######################################
#Second I2C core
#print ("Instantiating SFP I2C core:")
#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
#clock_I2C.state()
# #Third I2C core
# print ("Instantiating clock I2C core:")
# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
# clock_I2C.state()
# #time.sleep(0.01)
# #Read the EPROM
# mystop=False
# nwords=2
# myslave= 0x68 #DUNE CLOCK CHIP 0x68
# myaddr= [0x02 ]#0xfa
# clock_I2C.write( myslave, myaddr, mystop)
# #time.sleep(0.1)
# res= clock_I2C.read( myslave, nwords)
# print " CLOCK EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
#
#CLOCK CONFIGURATION BEGIN
zeClock=si5345(master_I2C, 0x68)
res= zeClock.getDeviceVersion()
zeClock.checkDesignID()
#zeClock.setPage(0, True)
#zeClock.getPage(True)
clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config.txt")
zeClock.writeConfiguration(clkRegList)######
zeClock.writeRegister(0x0536, [0x0B]) #Configures manual switch of inputs
zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
iopower= zeClock.readRegister(0x0949, 1)
print " Clock IO power: 0x%X" % iopower[0]
lol= zeClock.readRegister(0x000E, 1)
print " Clock LOL: 0x%X" % lol[0]
los= zeClock.readRegister(0x000D, 1)
print " Clock LOS: 0x%X" % los[0]
#CLOCK CONFIGURATION END
#DAC CONFIGURATION BEGIN
zeDAC1=AD5665R(master_I2C, 0x13)
zeDAC1.setIntRef(intRef= False, verbose= True)
zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
zeDAC2=AD5665R(master_I2C, 0x1F)
zeDAC2.setIntRef(intRef= False, verbose= True)
zeDAC2.writeDAC(0x2fff, 3, verbose= True)
#DAC CONFIGURATION END
#EEPROM BEGIN
zeEEPROM= E24AA025E48T(master_I2C, 0x50)
res=zeEEPROM.readEEPROM(0xfa, 6)
result=" EEPROM ID:\n\t"
for iaddr in res:
result+="%02x "%(iaddr)
print result
#EEPROM END
# #I2C EXPANDER CONFIGURATION BEGIN
IC6=PCA9539PW(master_I2C, 0x74)
#BANK 0
IC6.setInvertReg(0, 0x00)# 0= normal
IC6.setIOReg(0, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
IC6.setOutputs(0, 0xFF)
res= IC6.getInputs(0)
print "IC6 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC6.setInvertReg(1, 0x00)# 0= normal
IC6.setIOReg(1, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
IC6.setOutputs(1, 0xFF)
res= IC6.getInputs(1)
print "IC6 read back bank 1: 0x%X" % res[0]
# # #
IC7=PCA9539PW(master_I2C, 0x75)
#BANK 0
IC7.setInvertReg(0, 0xFF)# 0= normal
IC7.setIOReg(0, 0xFA)# 0= output <<<<<<<<<<<<<<<<<<<
IC7.setOutputs(0, 0xFF)
res= IC7.getInputs(0)
print "IC7 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC7.setInvertReg(1, 0x00)# 0= normal
IC7.setIOReg(1, 0x0F)# 0= output <<<<<<<<<<<<<<<<<<<
IC7.setOutputs(1, 0xFF)
res= IC7.getInputs(1)
print "IC7 read back bank 1: 0x%X" % res[0]
# #I2C EXPANDER CONFIGURATION END
# #Reset counters
#cmd = int("0x0", 16) #write 0x2 to reset
#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
#hw.dispatch()
#print "Trigger Reset: 0x%X" % restatus
## #Read trigger inputs
#myreg= [-1, -1, -1, -1, -1, -1]
#for inputN in range(0, 6):
# regString= "triggerInputs.ThrCount%dR" % inputN
# myreg[inputN]= hw.getNode(regString).read()
# hw.dispatch()
# print regString, myreg[inputN]
## Read ev formatter
#cmd = int("0x0", 16) #
##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
#hw.dispatch()
#print "Event Formatter Record: 0x%X" % efstatus
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
class E24AA025E48T:
#Class to configure the EEPROM
def __init__(self, i2c, slaveaddr=0x50):
self.i2c = i2c
self.slaveaddr = slaveaddr
def readEEPROM(self, startadd, nBytes):
#Read EEPROM memory locations
mystop= False
myaddr= [startadd]#0xfa
self.i2c.write( self.slaveaddr, [startadd], mystop)
res= self.i2c.read( self.slaveaddr, nBytes)
return res
import time
#from PyChipsUser import *
from I2cBusProperties import *
from RawI2cAccess import *
class FmcTluI2c:
############################
### configure i2c connection
############################
def __init__(self,board):
self.board = board
i2cClockPrescale = 0x30
self.i2cBusProps = I2cBusProperties(self.board, i2cClockPrescale)
return
##########################
### scan all i2c addresses
##########################
def i2c_scan(self):
list=[]
for islave in range(128):
i2cscan = RawI2cAccess(self.i2cBusProps, islave)
try:
i2cscan.write([0x00])
device="slave address "+hex(islave)+" "
if islave==0x1f:
device+="(DAC)"
elif islave==0x50:
device+="(serial number PROM)"
elif islave>=0x54 and islave<=0x57:
device+="(sp601 onboard EEPROM)"
else:
device+="(???)"
pass
list.append(device)
pass
except:
pass
pass
return list
###################
### write to EEPROM
###################
def eeprom_write(self,address,value):
if address<0 or address>127:
print "eeprom_write ERROR: address",address,"not in range 0-127"
return
if value<0 or value>255:
print "eeprom_write ERROR: value",value,"not in range 0-255"
return
i2cSlaveAddr = 0x50 # seven bit address, binary 1010000
prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
prom.write([address,value])
time.sleep(0.01) # write cycle time is 5ms. let's wait 10 to make sure.
return
####################
### read from EEPROM
####################
def eeprom_read(self,address):
if address<0 or address>255:
print "eeprom_write ERROR: address",address,"not in range 0-127"
return
i2cSlaveAddr = 0x50 # seven bit address, binary 1010000
prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
prom.write([address])
return prom.read(1)[0]
######################
### read serial number
######################
def get_serial_number(self):
result=""
for iaddr in [0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff]:
result+="%02x "%(self.eeprom_read(iaddr))
pass
return result
#################
### set DAC value
#################
def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
if channel<0 or channel>7:
print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
return -1
if value<0 or value>0xFFFF:
print "set_dac ERROR: value",value,"not in range 0-0xFFFF"
return -1
# AD5665R chip with A0,A1 tied to ground
#i2cSlaveAddrDac = 0x1F # seven bit address, binary 00011111
print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
# if we want to enable internal voltage reference:
if vrefOn:
# enter vref-on mode:
print "Turning internal reference ON"
dac.write([0x38,0x00,0x01])
else:
print "Turning internal reference OFF"
dac.write([0x38,0x00,0x00])
# now set the actual value
sequence=[( 0x18 + ( channel &0x7 ) ) , (value/256)&0xff , value&0xff]
print sequence
dac.write(sequence)
##################################################
### convert required threshold voltage to DAC code
##################################################
def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
Vdaq = ( desiredVoltage + Vref ) / 2
dacCode = 0xFFFF * Vdaq / Vref
return int(dacCode)
##################################################
### calculate the DAC code required and set DAC
##################################################
def set_threshold_voltage(self, channel , voltage ):
dacCode = self.convert_voltage_to_dac(voltage)
print " requested voltage, calculated DAC code = " , voltage , dacCode
self.set_dac(channel , dacCode)
# -*- coding: utf-8 -*-
"""
"""
import time
import uhal
verbose = True
################################################################################
# /*
# I2C CORE
# */
################################################################################
class I2CCore:
"""I2C communication block."""
# Define bits in cmd_stat register
startcmd = 0x1 << 7
stopcmd = 0x1 << 6
readcmd = 0x1 << 5
writecmd = 0x1 << 4
ack = 0x1 << 3
intack = 0x1
recvdack = 0x1 << 7
busy = 0x1 << 6
arblost = 0x1 << 5
inprogress = 0x1 << 1
interrupt = 0x1
def __init__(self, target, wclk, i2cclk, name="i2c", delay=None):
self.target = target
self.name = name
self.delay = delay
self.prescale_low = self.target.getNode("%s.i2c_pre_lo" % name)
self.prescale_high = self.target.getNode("%s.i2c_pre_hi" % name)
self.ctrl = self.target.getNode("%s.i2c_ctrl" % name)
self.data = self.target.getNode("%s.i2c_rxtx" % name)
self.cmd_stat = self.target.getNode("%s.i2c_cmdstatus" % name)
self.wishboneclock = wclk
self.i2cclock = i2cclk
self.config()
def state(self):
status = {}
status["ps_low"] = self.prescale_low.read()
status["ps_hi"] = self.prescale_high.read()
status["ctrl"] = self.ctrl.read()
status["data"] = self.data.read()
status["cmd_stat"] = self.cmd_stat.read()
self.target.dispatch()
status["prescale"] = status["ps_hi"] << 8
status["prescale"] |= status["ps_low"]
for reg in status:
val = status[reg]
bval = bin(int(val))
if verbose:
print "\treg %s = %d, 0x%x, %s" % (reg, val, val, bval)
def clearint(self):
self.ctrl.write(0x1)
self.target.dispatch()
def config(self):
#INITIALIZATION OF THE I2S MASTER CORE
#Disable core
self.ctrl.write(0x0 << 7)
self.target.dispatch()
#Write pre-scale register
#prescale = int(self.wishboneclock / (5.0 * self.i2cclock)) - 1
prescale = 0x0100 #FOR NOW HARDWIRED, TO BE MODIFIED
#prescale = 0x2710 #FOR NOW HARDWIRED, TO BE MODIFIED
self.prescale_low.write(prescale & 0xff)
self.prescale_high.write((prescale & 0xff00) >> 8)
#Enable core
self.ctrl.write(0x1 << 7)
self.target.dispatch()
def checkack(self):
inprogress = True
ack = False
while inprogress:
cmd_stat = self.cmd_stat.read()
self.target.dispatch()
inprogress = (cmd_stat & I2CCore.inprogress) > 0
ack = (cmd_stat & I2CCore.recvdack) == 0
return ack
def delayorcheckack(self):
ack = True
if self.delay is None:
ack = self.checkack()
else:
time.sleep(self.delay)
ack = self.checkack()#Remove this?
return ack
################################################################################
# /*
# I2C WRITE
# */
################################################################################
def write(self, addr, data, stop=True):
"""Write data to the device with the given address."""
# Start transfer with 7 bit address and write bit (0)
nwritten = -1
addr &= 0x7f
addr = addr << 1
startcmd = 0x1 << 7
stopcmd = 0x1 << 6
writecmd = 0x1 << 4
#Set transmit register (write operation, LSB=0)
self.data.write(addr)
#Set Command Register to 0x90 (write, start)
self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
self.target.dispatch()
ack = self.delayorcheckack()
if not ack:
self.cmd_stat.write(I2CCore.stopcmd)
self.target.dispatch()
return nwritten
nwritten += 1
for val in data:
val &= 0xff
#Write slave memory address
self.data.write(val)
#Set Command Register to 0x10 (write)
self.cmd_stat.write(I2CCore.writecmd)
self.target.dispatch()
ack = self.delayorcheckack()
if not ack:
self.cmd_stat.write(I2CCore.stopcmd)
self.target.dispatch()
return nwritten
nwritten += 1
if stop:
self.cmd_stat.write(I2CCore.stopcmd)
self.target.dispatch()
return nwritten
################################################################################
# /*
# I2C READ
# */
################################################################################
def read(self, addr, n):
"""Read n bytes of data from the device with the given address."""
# Start transfer with 7 bit address and read bit (1)
data = []
addr &= 0x7f
addr = addr << 1
addr |= 0x1 # read bit
self.data.write(addr)
self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
self.target.dispatch()
ack = self.delayorcheckack()
if not ack:
self.cmd_stat.write(I2CCore.stopcmd)
self.target.dispatch()
return data
for i in range(n):
if i < (n-1):
self.cmd_stat.write(I2CCore.readcmd) # <---
else:
self.cmd_stat.write(I2CCore.readcmd | I2CCore.ack | I2CCore.stopcmd) # <--- This tells the slave that it is the last word
self.target.dispatch()
ack = self.delayorcheckack()
val = self.data.read()
self.target.dispatch()
data.append(val & 0xff)
#self.cmd_stat.write(I2CCore.stopcmd)
#self.target.dispatch()
return data
################################################################################
# /*
# I2C WRITE-READ
# */
################################################################################
# def writeread(self, addr, data, n):
# """Write data to device, then read n bytes back from it."""
# nwritten = self.write(addr, data, stop=False)
# readdata = []
# if nwritten == len(data):
# readdata = self.read(addr, n)
# return nwritten, readdata
"""
SPI core XML:
<node description="SPI master controller" fwinfo="endpoint;width=3">
<node id="d0" address="0x0" description="Data reg 0"/>
<node id="d1" address="0x1" description="Data reg 1"/>
<node id="d2" address="0x2" description="Data reg 2"/>
<node id="d3" address="0x3" description="Data reg 3"/>
<node id="ctrl" address="0x4" description="Control reg"/>
<node id="divider" address="0x5" description="Clock divider reg"/>
<node id="ss" address="0x6" description="Slave select reg"/>
</node>
"""
class SPICore:
go_busy = 0x1 << 8
rising = 1
falling = 0
def __init__(self, target, wclk, spiclk, basename="io.spi"):
self.target = target
# Only a single data register is required since all transfers are
# 16 bit long
self.data = target.getNode("%s.d0" % basename)
self.control = target.getNode("%s.ctrl" % basename)
self.control_val = 0b0
self.divider = target.getNode("%s.divider" % basename)
self.slaveselect = target.getNode("%s.ss" % basename)
self.divider_val = int(wclk / spiclk / 2.0 - 1.0)
self.divider_val = 0x7f
self.configured = False
def config(self):
"Configure SPI interace for communicating with ADCs."
self.divider_val = int(self.divider_val) % 0xffff
if verbose:
print "Configuring SPI core, divider = 0x%x" % self.divider_val
self.divider.write(self.divider_val)
self.target.dispatch()
self.control_val = 0x0
self.control_val |= 0x0 << 13 # Automatic slave select
self.control_val |= 0x0 << 12 # No interrupt
self.control_val |= 0x0 << 11 # MSB first
# ADC samples data on rising edge of SCK
self.control_val |= 0x1 << 10 # change ouput on falling edge of SCK
# ADC changes output shortly after falling edge of SCK
self.control_val |= 0x0 << 9 # read input on rising edge
self.control_val |= 0x10 # 16 bit transfers
if verbose:
print "SPI control val = 0x%x = %s" % (self.control_val, bin(self.control_val))
self.configured = True
def transmit(self, chip, value):
if not self.configured:
self.config()
assert chip >= 0 and chip < 8
value &= 0xffff
self.data.write(value)
checkdata = self.data.read()
self.target.dispatch()
assert checkdata == value
self.control.write(self.control_val)
self.slaveselect.write(0xff ^ (0x1 << chip))
self.target.dispatch()
self.control.write(self.control_val | SPICore.go_busy)
self.target.dispatch()
busy = True
while busy:
status = self.control.read()
self.target.dispatch()
busy = status & SPICore.go_busy > 0
self.slaveselect.write(0xff)
data = self.data.read()
ss = self.slaveselect.read()
status = self.control.read()
self.target.dispatch()
#print "Received data: 0x%x, status = 0x%x, ss = 0x%x" % (data, status, ss)
return data
##########################################################