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AIDA-2020 TLU
Commit 4b25ad91 authored by David Cussans's avatar David Cussans
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Manual merge of scripted firmware build files from dgc_scripted_build_ipbus2 back into trunk. 

Also, a few PCB files updated when I tested cleaned up trunk 
by exporting schematic to pcb.
parent 6a2a87c7
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circuit_board/Cadence/fmc_tlu_v1a.cpm
View file @ 4b25ad91
{ Machine generated file created by SPI }
{ Last modified was 13:02:03 Thursday, October 10, 2013 }
{ Last modified was 18:42:38 Tuesday, February 11, 2014 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -50,7 +50,7 @@ create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_v1a_63.brd'
last_board_file 'fmc_tlu_v1a_66_gloss4a.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
......
circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstback.dat
View file @ 4b25ad91
{ Packager-XL run on 02-Oct-2013 AT 09:57:38 }
{ Packager-XL run on 11-Feb-2014 AT 18:41:05 }
FILE_TYPE = BACK_ANNOTATION;
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_toplevel_b(sch_1):page1";
BODY = "PLEMO2CI","I7": LOCATION = "PX1" #&CDS_LOCATION = "PX1" &SEC = "1" #&CDS_SEC = "1";
......
circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstpin.dat
View file @ 4b25ad91
FILE_TYPE=PINLIST;
{ Packager-XL run on 02-Oct-2013 AT 09:57:38 }
TIME=' COMPILATION ON 02-Oct-2013 AT 09:57:38';
{ Packager-XL run on 11-Feb-2014 AT 18:41:05 }
TIME=' COMPILATION ON 11-Feb-2014 AT 18:41:05';
primitive '24AA025E48'; body '24AA025E48';
'VCC':'(8)';
'VSS':'(4)';
......
circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxnet.dat
View file @ 4b25ad91
This source diff could not be displayed because it is too large. You can view the blob instead.
circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxref.dat
View file @ 4b25ad91
This source diff could not be displayed because it is too large. You can view the blob instead.
circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pxl.chg
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This source diff could not be displayed because it is too large. You can view the blob instead.
circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pxl.log
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circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/physical/netrev.lst
View file @ 4b25ad91
......@@ -2,9 +2,9 @@
( )
( Allegro Netrev Import Logic )
( )
( Drawing : fmc_tlu_v1_44.brd )
( Software Version : 16.5P002 )
( Date/Time : Thu Dec 06 10:13:00 2012 )
( Drawing : fmc_tlu_v1a_66_gloss4.brd )
( Software Version : 16.6S014 )
( Date/Time : Tue Feb 11 18:41:14 2014 )
( )
(---------------------------------------------------------------------)
......@@ -16,21 +16,21 @@ RIPUP_DELETE_FIRST_SEGMENT FALSE;
RIPUP_RETAIN_BONDWIRE FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'X:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel\packaged';
SCHEMATIC_DIRECTORY '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/physical/fmc_tlu_v1_44.brd';
NEW_BOARD_NAME 'fmc_tlu_v1_45.brd';
OLD_BOARD_NAME '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd';
NEW_BOARD_NAME 'fmc_tlu_v1a_66_gloss4a.brd';
CmdLine: netrev -proj X:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\fmc_tlu_v1.cpm -5 -y 1 -O X:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel\physical\fmc_tlu_v1_44.brd X:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel\physical\fmc_tlu_v1_45.brd -$
CmdLine: netrev -proj /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/fmc_tlu_v1a.cpm -y 1 -O /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4a.brd -$
------ Preparing to read pst files ------
Starting to read X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstchip.dat
Finished reading X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstchip.dat (00:00:00.56)
Starting to read X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstxprt.dat
Finished reading X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstxprt.dat (00:00:00.09)
Starting to read X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstxnet.dat
Finished reading X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstxnet.dat (00:00:00.06)
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstchip.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstchip.dat (00:00:00.21)
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxprt.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxprt.dat (00:00:00.01)
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxnet.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxnet.dat (00:00:00.00)
------ Oversights/Warnings/Errors ------
......@@ -39,54 +39,59 @@ Starting to read X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc
===========================================================
Start Constraint Diff3 Import
Constraint File: X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstcmdb.dat
Allegro Baseline: C:/Temp/#Taaaaae02620.tmp
Start time: Thu Dec 06 10:13:00 2012
Constraint File: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstcmdb.dat
Allegro Baseline: /tmp/#Taaaaad01896.tmp
Schematic Baseline: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstcmbc.dat
Start time: Tue Feb 11 18:41:15 2014
===========================================================
===========================================================
Finished Constraint Update Time: Thu Dec 06 10:13:01 2012
Finished Constraint Update Time: Tue Feb 11 18:41:16 2014
===========================================================
------ Library Paths ------
MODULEPATH = .
C:/Cadence/SPB_16.5/share/local/pcb/modules
/cadence/psd15.1/share/local/pcb/modules
../../../modules
../../fmc_tlu_cfd/physical
../../../pc042a_lib/pc042b_vsupply5v/physical
../../fmc_tlu_vsupply5v/physical
PSMPATH = .
/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/symbols
/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/formats
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/connector
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/soic
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/discrete
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/dip
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/so
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/bga
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/qfp
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/passif
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/cap
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/led
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/rel
/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/symbols
PADPATH = .
symbols
..
../symbols
C:/Cadence/SPB_16.5/share/local/pcb/symbols
C:/Cadence/SPB_16.5/share/pcb/pcb_lib/symbols
C:/Cadence/SPB_16.5/share/pcb/allegrolib/symbols
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/discrete
g:\cad\bris_cdslib\lib_psd14.x/symbols
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/bga
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/led
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/so
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/soic
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/cap
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/rel
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/dip
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/connector
PADPATH = x:\cad\ral_cdslib\lib_psd15.x/pads
.
symbols
..
../symbols
x:\cad\cern_cdslib/lib_psd16.x/allegro_libs/pe16/padstacks/padstack_smd
g:\cad\bris_cdslib\lib_psd14.x/pads
x:\cad\cern_cdslib/lib_psd16.x/allegro_libs/pe16/padstacks/padstack3
x:\cad\cern_cdslib/lib_psd16.x/allegro_libs/pe16/padstacks/padstackm
x:\cad\cern_cdslib/lib_psd16.x/allegro_libs/pe16/padstacks/padstack_smd
/software/CAD/Cadence/SPB16.60.000/share/local/pcb/padstacks
/software/CAD/Cadence/SPB16.60.000/share/pcb/pcb_lib/symbols
/software/CAD/Cadence/SPB16.60.000/share/pcb/allegrolib/symbols
/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/pads
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstack_smd
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstack3
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstackm
/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/pads
------ Summary Statistics ------
netrev run on Dec 6 10:12:59 2012
DESIGN NAME : 'FMC_TLU_TOPLEVEL'
PACKAGING ON 06-Dec-2012 AT 10:12:42
netrev run on Feb 11 18:41:14 2014
DESIGN NAME : 'FMC_TLU_TOPLEVEL_B'
PACKAGING ON 11-Feb-2014 AT 18:41:05
COMPILE 'logic'
CHECK_PIN_NAMES OFF
......@@ -118,6 +123,6 @@ netrev run on Dec 6 10:12:59 2012
No oversight detected
No warning detected
cpu time 0:05:45
elapsed time 0:00:03
cpu time 0:00:01
elapsed time 0:00:02
firmware/config/ise14/sp601/build_bitstream.tcl 0 → 100644
View file @ 4b25ad91
project open fmc-mtlu
puts "Regenerating cores"
cd $::env(FW_WORKSPACE)/workspace/ipcore_dir
catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
process run "Synthesize"
process run "Translate"
process run "Map"
process run "Place & Route"
process run "Generate Programming File"
project close
firmware/config/ise14/sp601/setup_project.tcl
View file @ 4b25ad91
project new single_cbc2_fmc
project new fmc-mtlu
project set family spartan6
project set device xc6slx16
project set package csg324
......@@ -17,17 +17,21 @@ project set "Enable BitStream Compression" TRUE -process "Generate Programming F
# IPBus Ethernet for gig_eth_pcs_pma_v11_5
xfile add ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
xfile add ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
puts "Adding and Regenerating Ethernet cores"
# Add cores for Ethernet
exec cp ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco ipcore_dir
exec cp ipbus/firmware/ethernet/coregen/mac_fifo_axi4.xco ipcore_dir
xfile add ipcore_dir/tri_mode_eth_mac_v5_4.xco
xfile add ipcore_dir/mac_fifo_axi4.xco
cd ipcore_dir
catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
cd ..
# Don't regenerate cores for now...
#cd ipcore_dir
#catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
#catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
#cd ..
puts "Adding IPBus files"
# Xilinx ISE setup fragment for ipbus core
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
......@@ -69,16 +73,63 @@ xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_registers.vhd
xfile add external/opencores_i2c/i2c_master_top.vhd
# Add CBC2 files
xfile add cbc2/firmware/hdl/i2c_master_rtl.vhd
xfile add cbc2/firmware/hdl/slaves.vhd
xfile add cbc2/firmware/hdl/clocks_s6_extphy.vhd
xfile add cbc2/firmware/hdl/ipbus_addr_decode.vhd
xfile add cbc2/firmware/hdl/top_sp605_extphy.vhd
xfile add cbc2/firmware/hdl/cbc2_interface.vhd
xfile add cbc2/firmware/hdl/i2c_trig.vhd
# Add TLU cores....
# Add cores for Ethernet
puts "Adding and Regenerating TLU cores"
exec cp fmc-mtlu/firmware/ise/ipcore_dir/tlu_event_fifo.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/FIFO.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/CounterUp.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_dir
xfile add ipcore_dir/tlu_event_fifo.xco
xfile add ipcore_dir/FIFO.xco
xfile add ipcore_dir/CounterUp.xco
xfile add ipcore_dir/internalTriggerGenerator.xco
# Don't regenerate cores for now...
#cd ipcore_dir
#catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
#catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
#catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
#catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
#cd ..
puts "Adding TLU Files "
# Add FMC-MTLU files. First the hand-written VHDL
xfile add fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
xfile add fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
xfile add fmc-mtlu/firmware/hdl/common/sync_reg.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
# Then add the HDL-Designer generated files..
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
# Add user constraints file
xfile add cbc2/firmware/ucf/sp601_extphy_pc045b_1hybrid.ucf
# UCF for TLU with FMC connector wrong way round.
#xfile add fmc-mtlu/firmware/ucf/sp601_FMC_mTLU.ucf
# bug-fixed TLU:
xfile add fmc-mtlu/firmware/ucf/sp601_FMC_mTLU_v1a.ucf
project close
puts "Successfully finished building project file"
firmware/config/ise14/sp605/build_bitstream.tcl 0 → 100644
View file @ 4b25ad91
project open fmc-mtlu
puts "Regenerating cores"
cd $::env(FW_WORKSPACE)/workspace/ipcore_dir
catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
process run "Synthesize"
process run "Translate"
process run "Map"
process run "Place & Route"
process run "Generate Programming File"
project close
firmware/config/ise14/sp605/coregen.cgp 0 → 100644
View file @ 4b25ad91
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET package = fgg484
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
firmware/config/ise14/sp605/file_list 0 → 100644
View file @ 4b25ad91
hdl ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
include ipbus/firmware/ethernet/cfg/file_list_s6_extphy
include ipbus/firmware/ipbus_core/cfg/file_list
firmware/config/ise14/sp605/setup_project.tcl 0 → 100644
View file @ 4b25ad91
project new fmc-mtlu
project set family spartan6
project set device xc6slx45t
project set package fgg484
project set speed -3
project set "Enable Multi-Threading" "2" -process "Map"
project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" -process "Map"
project set "Enable Multi-Threading" "2" -process "Place & Route"
project set "Enable BitStream Compression" TRUE -process "Generate Programming File"
# source $::env(REPOS_FW_DIR)/firmware/example_designs/scripts/addfiles.tcl
# Just list files by hand for now. Can't get addfiles.tcl to work.
#xfile add ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
# IPBus Ethernet for gig_eth_pcs_pma_v11_5
xfile add ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
xfile add ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
puts "Adding and Regenerating Ethernet cores"
# Add cores for Ethernet
exec cp ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco ipcore_dir
exec cp ipbus/firmware/ethernet/coregen/mac_fifo_axi4.xco ipcore_dir
xfile add ipcore_dir/tri_mode_eth_mac_v5_4.xco
xfile add ipcore_dir/mac_fifo_axi4.xco
# Don't regenerate cores for now...
#cd ipcore_dir
#catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
#catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
#cd ..
puts "Adding IPBus files"
# Xilinx ISE setup fragment for ipbus core
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd
# Add Opencores files for i2c interface
xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_registers.vhd
xfile add external/opencores_i2c/i2c_master_top.vhd
# Add TLU cores....
# Add cores for Ethernet
puts "Adding and Regenerating TLU cores"
exec cp fmc-mtlu/firmware/ise/ipcore_dir/tlu_event_fifo.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/FIFO.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/CounterUp.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_dir
xfile add ipcore_dir/tlu_event_fifo.xco
xfile add ipcore_dir/FIFO.xco
xfile add ipcore_dir/CounterUp.xco
xfile add ipcore_dir/internalTriggerGenerator.xco
# Don't regenerate cores for now...
#cd ipcore_dir
#catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
#catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
#catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
#catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
#cd ..
puts "Adding TLU Files "
# Add FMC-MTLU files. First the hand-written VHDL
xfile add fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
xfile add fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
xfile add fmc-mtlu/firmware/hdl/common/sync_reg.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
# Then add the HDL-Designer generated files..
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
# Add user constraints file
xfile add fmc-mtlu/firmware/ucf/sp605_FMC_mTLU.ucf
project close
puts "Successfully finished building project file"
firmware/ise/fmc_tlu_top_sp601/fmcTLU_v1.xise deleted 100644 → 0
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firmware/ise/fmc_tlu_top_sp601/setup_ipcore_dir.sh deleted 100755 → 0
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mkdir ipcore_dir
cp ipbus-firmware/ethernet/coregen/soft_emac_gmii_4_5.xco ipcore_dir
cp ipbus-firmware/ipbus/coregen/sdpram_8x11.xco ipcore_dir
cp ipbus-firmware/ipbus/coregen/dpram_8x12_32x10.xco ipcore_dir
firmware/ise/projects/fmcTLU_v1.xise deleted 100644 → 0
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firmware/scripts/build_bitstream.sh 0 → 100644
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#!/bin/sh
#
# Script to build firmware for FMC-based AIDA mini-TLU
#
# This script builds the bitstream using ISE and the ISE project generated
# by setup_workspace.sh
#
# cd to the working directory and execute this script....
#
# David Cussans, December 2013
#
export BOARD_TYPE=sp601
export ISE_VER=ise14
export FW_WORKSPACE=`pwd`
echo "Workspace directory = " ${FW_WORKSPACE}/workspace
TLUDir=`pwd`/fmc-mtlu
echo "Directory with TLU source files = ${TLUDir}"
pushd $FW_WORKSPACE/workspace
xtclsh $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/build_bitstream.tcl
echo "Bitstream built in ${FW_WORKSPACE}/workspace"
popd
firmware/scripts/setup_workspace.sh 0 → 100644
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#!/bin/sh
#
# Script to build firmware for FMC-based AIDA mini-TLU
#
# This script creates an ISE project.
#
# Create a working directory and execute this script....
#
# Once project has been created either open in ISE or
# execute the build_bitstream.sh script.
#
# David Cussans, December 2013
#
export FW_WORKSPACE=`pwd`
echo "Current directory = " $FW_WORKSPACE
export BOARD_TYPE=sp601
export ISE_VER=ise14
export VERSION=branches/dgc_scripted_build_ipbus2
echo "Setting up AIDA mini-TLU code version $VERSION"
# Check out FMC-MTLU code
TLUDir=`pwd`/fmc-mtlu
if [ ! -d "$TLUDir" ]; then
echo "Checking out AIDA mini-TLU code"
mkdir fmc-mtlu
pushd fmc-mtlu
svn co http://svn.ohwr.org/fmc-mtlu/${VERSION}/firmware
popd
echo "Checked out FMC-MTLU code"
fi
# Check out IPBus code
IPBusDir=`pwd`/IPBus2
if [ ! -d "$IPBusDir" ]; then
mkdir $IPBusDir
pushd $IPBusDir
svn co http://svn.cern.ch/guest/cactus/tags/ipbus_2_0_v1/firmware
echo "Checked out IPBus2 code"
popd
fi
# Check out directory for external cores ( e.g. I2C)
if [ ! -d "external" ]; then
echo "Checking out I2C code"
svn co http://cactus.hepforge.org/svn/tags/firmware_pre_131_RAL/firmware/external
fi
# Create a directory contain the build products.
WorkDir=workspace
if [ ! -d "$WorkDir" ]; then
mkdir workspace
mkdir workspace/ipcore_dir
echo "Made workspace"
fi
export REPOS_BUILD_DIR=`pwd`/workspace
pushd workspace
# Create soft links to ipbus, fmc-mtlu code , i2c code
if [ ! -e "ipbus" ]; then
ln -s $IPBusDir ipbus
fi
if [ ! -e "fmc-mtlu" ]; then
ln -s ../fmc-mtlu .
fi
if [ ! -e "external" ]; then
ln -s ../external .
fi
if [ ! -e "file_list" ]; then
ln -s $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/file_list .
fi
if [ ! -e "ipbus" ]; then
ln -s ../$IPBusDir/firmware/config/$ISE_VER/$BOARD_TYPE/file_list .
fi
pushd ipcore_dir
if [ ! -e "coregen.cgp" ]; then
ln -s $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/coregen.cgp .
fi
popd
#export REPOS_FW_DIR=$IPBusDir
export REPOS_FW_DIR=ipbus
echo "IPBus directory = " $IPBusDir
echo "FMC-MTLU directry = " $TLUDir
xtclsh $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/setup_project.tcl
echo "Finished setting up ISE project."
echo "Open in $ISE_VER and build bit-stream ,or execute build_bitstream.sh"
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