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AIDA-2020 TLU
Commits
4df4608a
Commit
4df4608a
authored
May 28, 2015
by
David Cussans
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* Renamed TPx3_iface to TPx3_iface_rtl
* Edited top_extphy to include IPBus interface to TPx3 interface.
parent
a6c17ac3
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TPx3_iface.vhd
firmware/hdl/common/TPx3_iface.vhd
+0
-95
top_extphy_struct.vhd
firmware/hdl/miniTLU/top_extphy_struct.vhd
+10
-4
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firmware/hdl/common/TPx3_iface.vhd
deleted
100644 → 0
View file @
a6c17ac3
--! Simple module to interface AIDA TLU to LHCb TimePix3 telescope.
--! Accepts T0 sync signal and shutter signal from telescope and re-transmits.
LIBRARY
ieee
;
USE
ieee
.
std_logic_1164
.
all
;
library
unisim
;
use
unisim
.
VComponents
.
all
;
entity
TPx3_iface
is
port
(
clk_4x_i
:
in
std_logic
;
--! system clock
clk_4x_strobe
:
in
std_logic
;
--! strobes high for one cycle every 4 of clk_4x
T0_p_i
:
in
std_logic
;
--! T0 signal from timepix telescope clk/sync system
T0_n_i
:
in
std_logic
;
--! T0 signal from timepix telescope clk/sync system
T0_o
:
out
std_logic
;
--! T0 signal retimed onto system clock
shutter_p_i
:
in
std_logic
;
--! shutter signal from timepix telescope clk/sync system
shutter_n_i
:
in
std_logic
;
--! shutter signal from timepix telescope clk/sync system
shutter_o
:
out
std_logic
--! shutter signal retimed onto system clock
);
end
entity
TPx3_iface
;
architecture
rtl
of
TPx3_iface
is
signal
s_T0
,
s_T0_d1
,
s_T0_d2
,
s_stretch_T0_in
:
std_logic
:
=
'0'
;
-- signal after IBufDS and sampled onto clk_4x
signal
s_stretch_T0_in_sr
:
std_logic_vector
(
2
downto
0
)
:
=
"111"
;
--! Gets shifted out by clk_4x logic. Loaded by T0ger_i
signal
s_T0_out_sr
:
std_logic_vector
(
2
downto
0
)
:
=
"111"
;
--! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
signal
s_shutter
,
s_shutter_d1
,
s_shutter_d2
:
std_logic
:
=
'0'
;
-- signal after IBufDS and sampled onto clk_4x
begin
-- architecture rtl
cmp_IBUFDS_T0
:
IBUFDS
generic
map
(
DIFF_TERM
=>
TRUE
,
-- Differential Termination
IBUF_LOW_PWR
=>
TRUE
,
-- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD
=>
"LVDS_25"
)
port
map
(
O
=>
s_T0
,
-- Buffer output
I
=>
T0_p_i
,
-- Diff_p buffer input (connect directly to top-level port)
IB
=>
T0_n_i
-- Diff_n buffer input (connect directly to top-level port)
);
p_T0_retime
:
process
(
clk_4x_i
,
clk_4x_strobe
,
s_T0
)
is
begin
-- process p_T0_retime
if
rising_edge
(
clk_4x_i
)
then
s_T0_d1
<=
s_T0
;
s_T0_d2
<=
s_T0_d1
;
-- Stretch T0_i pulse to 4 clock cycles on clk4x
if
s_T0_d1
=
'1'
then
s_stretch_T0_in
<=
'1'
;
s_stretch_T0_in_sr
<=
"111"
;
else
s_stretch_T0_in
<=
s_stretch_T0_in_sr
(
0
);
s_stretch_T0_in_sr
<=
'0'
&
s_stretch_T0_in_sr
(
s_stretch_T0_in_sr
'left
downto
1
);
end
if
;
--
if
(
clk_4x_strobe
=
'1'
)
and
(
s_stretch_T0_in
=
'1'
)
then
T0_o
<=
'1'
;
s_T0_out_sr
<=
"111"
;
else
T0_o
<=
s_T0_out_sr
(
0
);
s_T0_out_sr
<=
'0'
&
s_T0_out_sr
(
s_T0_out_sr
'left
downto
1
);
end
if
;
end
if
;
end
process
p_T0_retime
;
cmp_IBUFDS_shutter
:
IBUFDS
generic
map
(
DIFF_TERM
=>
TRUE
,
-- Differential Termination
IBUF_LOW_PWR
=>
TRUE
,
-- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD
=>
"LVDS_25"
)
port
map
(
O
=>
s_shutter
,
-- Buffer output
I
=>
shutter_p_i
,
-- Diff_p buffer input (connect directly to top-level port)
IB
=>
shutter_n_i
-- Diff_n buffer input (connect directly to top-level port)
);
-- Just retime onto the 4x clock. Probably should retime onto 1x clock.
p_shutter_retime
:
process
(
s_shutter
,
clk_4x_i
)
is
begin
-- process p_shutter_retime
if
rising_edge
(
clk_4x_i
)
then
s_shutter_d1
<=
s_shutter
;
s_shutter_d2
<=
s_shutter_d1
;
shutter_o
<=
s_shutter_d2
;
end
if
;
end
process
p_shutter_retime
;
end
architecture
rtl
;
firmware/hdl/miniTLU/top_extphy_struct.vhd
View file @
4df4608a
...
...
@@ -2,7 +2,7 @@
--
-- Created:
-- by - phdgc.users (voltar.phy.bris.ac.uk)
-- at - 1
8:33:07 05/08
/15
-- at - 1
3:09:17 05/13
/15
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1b (Build 2)
--
...
...
@@ -14,7 +14,7 @@ ENTITY top_extphy IS
GENERIC
(
g_NUM_DUTS
:
positive
:
=
2
;
g_NUM_TRIG_INPUTS
:
positive
:
=
4
;
g_NUM_EXT_SLAVES
:
positive
:
=
7
;
--! Number of slaves outside IPBus interface
g_NUM_EXT_SLAVES
:
positive
:
=
8
;
--! Number of slaves outside IPBus interface
g_EVENT_DATA_WIDTH
:
positive
:
=
64
;
g_IPBUS_WIDTH
:
positive
:
=
32
;
g_NUM_EDGE_INPUTS
:
positive
:
=
4
;
...
...
@@ -69,7 +69,7 @@ END ENTITY top_extphy ;
--
-- Created:
-- by - phdgc.users (voltar.phy.bris.ac.uk)
-- at - 1
7:12:07 05/11
/15
-- at - 1
3:18:44 05/13
/15
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1b (Build 2)
--
...
...
@@ -199,9 +199,12 @@ ARCHITECTURE struct OF top_extphy IS
T0_p_i
:
IN
std_logic
;
clk_4x_i
:
IN
std_logic
;
clk_4x_strobe
:
IN
std_logic
;
ipbus_clk_i
:
IN
std_logic
;
ipbus_i
:
IN
ipb_wbus
;
shutter_n_i
:
IN
std_logic
;
shutter_p_i
:
IN
std_logic
;
T0_o
:
OUT
std_logic
;
ipbus_o
:
OUT
ipb_rbus
;
shutter_o
:
OUT
std_logic
);
END
COMPONENT
TPx3_iface
;
...
...
@@ -468,7 +471,10 @@ BEGIN
T0_o
=>
T0_o
,
shutter_p_i
=>
TPix_Shutter_p_i
,
shutter_n_i
=>
TPix_Shutter_n_i
,
shutter_o
=>
s_shutter
shutter_o
=>
s_shutter
,
ipbus_clk_i
=>
ipbus_clk
,
ipbus_i
=>
ipbw
(
7
),
ipbus_o
=>
ipbr
(
7
)
);
I5
:
eventBuffer
GENERIC
MAP
(
...
...
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