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AIDA-2020 TLU
Commit 6e6ff933 authored by Alvaro Dosil's avatar Alvaro Dosil
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Increase FIFO size to 16M

parent f4280fa5
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Showing with 22 additions and 17 deletions
firmware/hdl/common/eventBuffer_rtl.vhd
View file @ 6e6ff933
......@@ -54,8 +54,8 @@ ENTITY eventBuffer IS
GENERIC(
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_WRITE_COUNTER_WIDTH : positive := 13;
g_READ_COUNTER_WIDTH : positive := 14
g_WRITE_COUNTER_WIDTH : positive := 15;
g_READ_COUNTER_WIDTH : positive := 16
);
PORT(
clk_4x_logic_i : IN std_logic;
......@@ -84,7 +84,8 @@ ARCHITECTURE rtl OF eventBuffer IS
signal s_wr_data_count , s_wr_data_count_reg : std_logic_vector(g_WRITE_COUNTER_WIDTH-1 downto 0) := (others =>'0');
signal s_rd_data_count : std_logic_vector(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0');
signal s_fifo_fill_level : unsigned(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0'); -- read-counter - 2*write_count
--signal s_fifo_fill_level : unsigned(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0'); -- read-counter - 2*write_count
signal s_fifo_fill_level : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others =>'0'); -- read-counter - 2*write_count
signal s_write_strobe : std_logic := '0';
signal s_rst_fifo : std_logic := '0'; -- ! Take high to reset FIFO pointers.
......@@ -112,7 +113,8 @@ BEGIN
--! Multiplex output data.
with ipbus_i.ipb_addr(1 downto 0) select ipbus_o.ipb_rdata <=
s_fifo_dout when "00",
s_fifo_fill_level_d1 when "01",
--s_fifo_fill_level_d1 when "01",
s_fifo_fill_level when "01",
s_fifo_status_ipb when "10",
(others => '1') when others;
......@@ -126,7 +128,8 @@ BEGIN
-- Register data onto IPBus clock domain to ease timing closure.
s_fifo_status_ipb <= X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty;
s_fifo_fill_level_d1 <= X"0000" & "00" & std_logic_vector(s_fifo_fill_level);
--s_fifo_fill_level_d1 <= X"0000" & "00" & std_logic_vector(s_fifo_fill_level);
s_fifo_fill_level <= X"0000" & s_rd_data_count;
end if;
end process ipbus_write;
......@@ -173,7 +176,7 @@ BEGIN
--! wr_data_count and rd_data_count provide exactly the same information but in different clock domains
--s_fifo_fill_level <= (unsigned(std_logic_vector(s_wr_data_count_reg) & "0") - unsigned(s_rd_data_count));
s_fifo_fill_level <= unsigned(s_rd_data_count);
--s_fifo_fill_level <= unsigned(s_rd_data_count);
END ARCHITECTURE rtl;
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
View file @ 6e6ff933
......@@ -215,8 +215,8 @@ ARCHITECTURE struct OF top_extphy IS
GENERIC (
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_WRITE_COUNTER_WIDTH : positive := 13;
g_READ_COUNTER_WIDTH : positive := 14
g_WRITE_COUNTER_WIDTH : positive := 15;
g_READ_COUNTER_WIDTH : positive := 16
);
PORT (
clk_4x_logic_i : IN std_logic ;
......@@ -472,8 +472,8 @@ BEGIN
GENERIC MAP (
g_EVENT_DATA_WIDTH => g_EVENT_DATA_WIDTH,
g_IPBUS_WIDTH => g_IPBUS_WIDTH,
g_WRITE_COUNTER_WIDTH => 13,
g_READ_COUNTER_WIDTH => 14
g_WRITE_COUNTER_WIDTH => 15,
g_READ_COUNTER_WIDTH => 16
)
PORT MAP (
clk_4x_logic_i => clk_4x_logic,
......
firmware/scripts/test_aida_tlu.py
View file @ 6e6ff933
......@@ -104,7 +104,7 @@ board.write("InternalTriggerIntervalW",0)
print "Enabling DUT 1"
board.write("DUTMaskW",0)
board.write("TriggerMaskW",0x8)
board.write("TriggerMaskW",0x0)
board.write("TriggerVetoW",0)
print "Trigger inputs enabled: ", board.read("TriggerMaskR")
......@@ -117,12 +117,12 @@ board.write("Enable_Record_Data",1)
print "Enabling handshake: No-handshake"
board.write("HandshakeTypeW",1)
TriggerInterval = 0
board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*25ns
TriggerInterval = 1000
board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
#sys.exit(0)
n=1000 #number of measurements
n=60000 #number of measurements
data={"EvtType":[],"InputTrig":[],"CoarseTS":[],"FineTS0":[],"FineTS1":[],"FineTS2":[],"FineTS3":[],"EvtNumber":[], "TS":[]}
read=range(4)
trigger_old=0
......@@ -144,12 +144,14 @@ while i<n:
data["EvtNumber"].append(read[3])
if data["InputTrig"][i]==0x800:
data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS0"][i]>>3)*6.25+(data["FineTS0"][i]&0x7)*0.781)
if data["InputTrig"][i]==0x400:
elif data["InputTrig"][i]==0x400:
data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS1"][i]>>3)*6.25+(data["FineTS1"][i]&0x7)*0.781)
if data["InputTrig"][i]==0x200:
elif data["InputTrig"][i]==0x200:
data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS2"][i]>>3)*6.25+(data["FineTS2"][i]&0x7)*0.781)
if data["InputTrig"][i]==0x100:
elif data["InputTrig"][i]==0x100:
data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS3"][i]>>3)*6.25+(data["FineTS3"][i]&0x7)*0.781)
else:
data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS0"][i]>>3)*6.25+(data["FineTS0"][i]&0x7)*0.781)
#print data["CoarseTS"][i], (data["FineTS0"][i]&0x18)>>3
#hFineTS.Fill(data["FineTS0"][i]&0x7)
#if i!=0:
......
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