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AIDA-2020 TLU
Commit 75e77d84 authored by David Cussans's avatar David Cussans
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Partially bug fixes for shutter mode 

Partially catching up ( manually ) with Paolo's code .
parent f71ea4c3
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components/tlu/firmware/hdl/dut/DUTInterface_AIDA_rtl.vhd
View file @ 75e77d84
......@@ -36,8 +36,8 @@ ENTITY DUTInterface_AIDA IS
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
trigger_i : IN std_logic; --! goes high when trigger logic issues a trigger
reset_or_clk_to_dut_i : IN std_logic; --! Synchronization signal. Passed to DUT pins
shutter_to_dut_i : IN std_logic; --! Goes high to indicate data-taking active. DUTs report busy unless ignore_shutter_veto flag is set high
ignore_shutter_veto_i : in std_logic;
shutter_to_dut_i : IN std_logic; --! Goes high to indicate data-taking active. Gets passed to DUT pins
-- ignore_shutter_veto_i : in std_logic;
ignore_dut_busy_i : in std_logic;
--dut_mask_i : in std_logic; --! Set high if DUT is active. Moved one level up
busy_o : OUT std_logic; --! goes high when DUT is busy or vetoed by shutter
......@@ -139,8 +139,9 @@ BEGIN
-- ((dut_busy_i and DUT_mask_i ) and (not ignore_dut_busy_i) );
--busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or ( (dut_busy_i and DUT_mask_i ) );
busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or ( dut_busy_i );
--busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or ( dut_busy_i );
busy_o <= dut_busy_i;
dut_clk_o <= s_dut_clk ;
--dut_trigger_o <= DUT_mask_i and s_trigger_out;
dut_trigger_o <= s_trigger_out;
......
components/tlu/firmware/hdl/dut/DUTInterface_EUDET_rtl.vhd
View file @ 75e77d84
......@@ -25,7 +25,7 @@ entity DUTInterface_EUDET is
system_clk_i : in std_logic; --! rising edge active clock from TLU
reset_or_clk_to_dut_i : IN std_logic; --! Synchronization signal. Passed to DUT pins
shutter_to_dut_i : IN std_logic; --! Goes high to indicate data-taking active. DUTs report busy unless ignoreShutterVeto flag set high
ignore_shutter_veto_i : in std_logic;
-- ignore_shutter_veto_i : in std_logic;
enable_dut_veto_i : in std_logic; --! If high: if DUT raises dut_busy_i, then busy_o is raised
-- Connections to DUT:
dut_clk_i : in std_logic; --! rising edge active clock from DUT
......@@ -244,9 +244,9 @@ end process;
begin -- process set_muxsel
if rising_edge(system_clk_i) then
if (state = IDLE) then
busy_o <= '0';
busy_o <= '0'; -- If idle, then busy is low.
else
busy_o <= '1';
busy_o <= '1'; -- For all other states, busy is high
end if;
end if;
end process set_busy;
......
components/tlu/firmware/hdl/dut/DUTInterfaces_rtl.vhd
View file @ 75e77d84
......@@ -61,7 +61,8 @@ ENTITY DUTInterfaces IS
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
trigger_i : IN std_logic; --! goes high when trigger logic issues a trigger
reset_or_clk_to_dut_i : IN std_logic; --! Synchronization signal. Passed to DUT pins
shutter_to_dut_i : IN std_logic; --! Goes high to indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high
shutter_to_dut_i : IN std_logic; --! Goes high to indicate data-taking active.
shutter_veto_i : IN std_logic; --! WHen high DUTs report busy unless ignoreShutterVeto IPBus flag is set high
-- IPBus signals.
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus; --! Signals from IPBus core to slave
......@@ -103,7 +104,8 @@ ARCHITECTURE rtl OF DUTInterfaces IS
signal s_clk_to_DUT_AIDA , s_busy_from_dut_aida , s_dut_veto_aida , s_reset_or_clk_to_dut_aida , s_trigger_to_dut_aida , s_shutter_to_dut_aida : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs used. 1 = active
signal s_dut_clk_is_output : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1'); --! Set low to enable transmission of clock from TLU to DUT
signal s_veto_from_duts : std_logic; --! Goes high if any of the DUTs are busy
constant c_NUM_EUDET_FSM_BITS : positive := 4;
signal s_dut_fsm_status_eudet : std_logic_vector((c_NUM_EUDET_FSM_BITS*g_NUM_DUTS)-1 downto 0) ; --! Stores status from EUDET interface FSM. Can only support up to 32/4 = 8 DUT interfaces, not 12...
......@@ -121,51 +123,62 @@ ARCHITECTURE rtl OF DUTInterfaces IS
-- Signal for IPBus
constant c_N_CTRL : positive := 9;
constant c_N_STAT : positive := 9;
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
constant c_N_CTRL : positive := 8;
constant c_N_STAT : positive := 8;
-- signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
-- signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
signal s_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
constant c_qmask : ipb_reg_v(c_N_CTRL-1 downto 0) := (others => (others => '1'));
attribute mark_debug : string;
attribute mark_debug of s_IgnoreShutterVeto: signal is "true";
attribute mark_debug of s_DUT_ignore_busy: signal is "true";
BEGIN
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
ipbus_registers: entity work.ipbus_ctrlreg_v
ipbus_registers: entity work.ipbus_syncreg_v
generic map(
N_CTRL => c_N_CTRL,
N_STAT => c_N_STAT
)
port map(
clk => ipbus_clk_i,
reset=> '0',--ipbus_reset_i ,
ipbus_in=> ipbus_i,
ipbus_out=> ipbus_o,
d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb=> open
rst=> '0',--ipbus_reset_i ,
ipb_in=> ipbus_i,
ipb_out=> ipbus_o,
slv_clk => clk_4x_logic_i,
d=> s_status_to_ipbus,
q=> s_sync_control_from_ipbus,
qmask => c_qmask,
stb=> open,
rstb => open
);
-- Synchronize registers from logic clock to ipbus.
sync_status: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_4x_logic_i,
data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
-- -- Synchronize registers from logic clock to ipbus.
-- sync_status: entity work.synchronizeRegisters
-- generic map (
-- g_NUM_REGISTERS => c_N_STAT )
-- port map (
-- clk_input_i => clk_4x_logic_i,
-- data_i => s_status_to_ipbus,
-- data_o => s_sync_status_to_ipbus,
-- clk_output_i => ipbus_clk_i);
-- Synchronize registers from logic clock to ipbus.
sync_ctrl: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_CTRL )
port map (
clk_input_i => ipbus_clk_i,
data_i => s_control_from_ipbus,
data_o => s_sync_control_from_ipbus,
clk_output_i => clk_4x_logic_i);
-- -- Synchronize registers from logic clock to ipbus.
-- sync_ctrl: entity work.synchronizeRegisters
-- generic map (
-- g_NUM_REGISTERS => c_N_CTRL )
-- port map (
-- clk_input_i => ipbus_clk_i,
-- data_i => s_control_from_ipbus,
-- data_o => s_sync_control_from_ipbus,
-- clk_output_i => clk_4x_logic_i);
-- Map the control registers
s_DUT_mask <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
......@@ -289,7 +302,7 @@ BEGIN
trigger_i => trigger_i ,
reset_or_clk_to_dut_i => reset_or_clk_to_dut_i,
shutter_to_dut_i => shutter_to_dut_i ,
ignore_shutter_veto_i => s_IgnoreShutterVeto ,
-- ignore_shutter_veto_i => s_IgnoreShutterVeto ,
ignore_dut_busy_i => s_DUT_ignore_busy(dut),
--dut_mask_i => s_DUT_mask(dut),
busy_o => s_dut_veto_aida(dut),
......@@ -317,7 +330,7 @@ BEGIN
system_clk_i => clk_4x_logic_i ,
reset_or_clk_to_dut_i => reset_or_clk_to_dut_i,
shutter_to_dut_i => shutter_to_dut_i ,
ignore_shutter_veto_i => s_IgnoreShutterVeto ,
-- ignore_shutter_veto_i => s_IgnoreShutterVeto ,
enable_dut_veto_i => s_dut_enable_veto_eudet(dut),
-- Connections to DUT:
dut_clk_i => s_clk_from_dut_eudet(dut),
......@@ -337,8 +350,9 @@ BEGIN
s_dut_clk_is_output <= not s_DUT_aida_eudet_mode; -- at the moment can hardwire clk_is_output to mode_is_aida
s_intermediate_busy_or(0) <= '0';
veto_o <= s_intermediate_busy_or(g_NUM_DUTS);
s_veto_from_duts <= s_intermediate_busy_or(g_NUM_DUTS);
veto_o <= '0' when s_veto_from_duts ='0' and ((s_IgnoreShutterVeto = '1') or (shutter_veto_i = '0')) else '1';
-- purpose: Multiplexes signals between EUDET and AIDA interfaces
-- type : combinational
-- inputs : clk_4x_logic_i
......
projects/TLU_v1e/addr_table/TLUaddrmap.xml
View file @ 75e77d84
......@@ -9,11 +9,11 @@
<node id="IgnoreShutterVetoW" address="0x2" permission="w" description="" />
<node id="DUTInterfaceModeW" address="0x3" permission="w" description="" />
<node id="DUTInterfaceModeModifierW" address="0x4" permission="w" description="" />
<node id="DUTInterfaceModeR" address="0xB" permission="r" description="" />
<node id="DUTInterfaceModeModifierR" address="0xC" permission="r" description="" />
<node id="DutMaskR" address="0x8" permission="r" description="" />
<node id="IgnoreDUTBusyR" address="0x9" permission="r" description="" />
<node id="IgnoreShutterVetoR" address="0xA" permission="r" description="" />
<node id="DUTInterfaceModeR" address="0xB" permission="r" description="" />
<node id="DUTInterfaceModeModifierR" address="0xC" permission="r" description="" />
</node>
<node id="Shutter" address="0x2000" description="Shutter/T0 control" fwinfo="endpoint;width=4">
......
projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
View file @ 75e77d84
......@@ -25,7 +25,7 @@ use work.ipbus.ALL;
entity top is
generic(
constant FW_VERSION : unsigned(31 downto 0):= X"1e00000f"; -- Firmware revision. Remember to change this as needed.
constant FW_VERSION : unsigned(31 downto 0):= X"1e000010"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......@@ -162,6 +162,7 @@ architecture rtl of top is
trigger_i : IN std_logic ; --! goes high when trigger logic issues a trigger
reset_or_clk_to_dut_i : IN std_logic ; --! Synchronization signal. Passed TO DUT pins
shutter_to_dut_i : IN std_logic ; --! Goes high TO indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high
shutter_veto_i : IN std_logic; --! WHen high DUTs report busy unless ignoreShutterVeto IPBus flag is set high
-- IPBus signals.
ipbus_clk_i : IN std_logic ;
ipbus_i : IN ipb_wbus ; --! Signals from IPBus core TO slave
......@@ -409,7 +410,7 @@ begin
-- ModuleWare code(v1.12) for instance 'I19' of 'merge'
--gpio_hdr <= dout1 & dout & s_shutter & T0_o;
-- ModuleWare code(v1.12) for instance 'I8' of 'sor'
overall_veto <= buffer_full_o OR veto_o or shutter_veto_o;
overall_veto <= buffer_full_o OR veto_o ; -- or shutter_veto_o;
-- ModuleWare code(v1.12) for instance 'I16' of 'sor'
s_triggerLogic_reset <= logic_reset OR T0_o;
......@@ -634,6 +635,7 @@ begin
trigger_i => overall_trigger,
reset_or_clk_to_dut_i => T0_o,
shutter_to_dut_i => s_shutter,
shutter_veto_i => shutter_veto_o,
ipbus_clk_i => clk_ipb,
ipbus_i => ipbww(N_SLV_DUTINTERFACES),
ipbus_reset_i => rst_ipb,
......
projects/TLU_v1e/firmware/ucf/I2C_constr.xdc
View file @ 75e77d84
......@@ -22,73 +22,5 @@ set_property PACKAGE_PIN P18 [get_ports i2c_sda_b]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 4 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list I4/clk_4x_logic_o]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 6 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {I5/trigger_o[0]} {I5/trigger_o[1]} {I5/trigger_o[2]} {I5/trigger_o[3]} {I5/trigger_o[4]} {I5/trigger_o[5]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 6 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {I10/trigger_o[0]} {I10/trigger_o[1]} {I10/trigger_o[2]} {I10/trigger_o[3]} {I10/trigger_o[4]} {I10/trigger_o[5]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 6 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {triggers[0]} {triggers[1]} {triggers[2]} {triggers[3]} {triggers[4]} {triggers[5]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list buffer_full_i]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list s_shutter]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list I8/cmp_SyncGen/s_shutter]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list shutter_veto_o]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list I6/trigger_i]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list I10/cmp_coincidence_logic/trigger_o]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list veto_i]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list I9/veto_o]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list I10/s_post_veto_trigger0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list I10/s_post_veto_trigger1]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list I10/s_pre_veto_trigger_reg_n_0]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_4x_logic]
projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
View file @ 75e77d84
......@@ -100,7 +100,6 @@ set_property PACKAGE_PIN G3 [get_ports {dut_clk_i[3]}]
# -------------------------------------------------------------------------------------------------
create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_ports sysclk_40_i_p]
#Define clock groups and make them asynchronous with each other
#set_clock_groups -asynchronous -group {sysclk I I_1 mmcm_n_10 mmcm_n_6 mmcm_n_8 clk_ipb_i} -group {sysclk_40_i_p pll_base_inst_n_2 s_clk160}
......@@ -110,14 +109,109 @@ create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_po
#set_clock_groups -asynchronous -group {sysclk clk_ipb_i} -group {sysclk_40_i_p s_clk160}
#set_clock_groups -asynchronous -group { [get_nets sysclk] } -group { [get_nets *sysclk_40_i*]}
set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -min 0.300 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -max 0.400 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
# -false_path
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {sysclk clk_ipb_i}] -group [get_clocks -include_generated_clocks {s_clk160 sysclk_40_i_p}]
#set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {sysclk clk_ipb_i}] -group [get_clocks -include_generated_clocks {s_clk160 sysclk_40_i_p}]
#set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks [get_ports sysclk]] -group [get_clocks -include_generated_clocks [get_ports sysclk_40_i_p]]
# set_false_path -from [get_clocks sysclk] -to [get_clocks sysclk_40_i_p]
#set_clock_groups -asynchronous -group {[get_clocks sysclk]} -group {[get_clocks sysclk_40_i_p]}
#set_clock_groups -asynchronous -group [get_clocks sysclk] -group [get_clocks sysclk_40_i_p]
create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_ports sysclk_40_i_p]
set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -min 0.300 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -max 1.400 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
set_clock_groups -asynchronous -group [list [get_clocks clk_ipb_i] [get_clocks sysclk]] -group [list [get_clocks s_clk160] [get_clocks sysclk_40_i_p]]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 1 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list I4/clk_4x_logic_o]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 6 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {I5/trigger_o[0]} {I5/trigger_o[1]} {I5/trigger_o[2]} {I5/trigger_o[3]} {I5/trigger_o[4]} {I5/trigger_o[5]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 4 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {I9/s_DUT_ignore_busy[0]} {I9/s_DUT_ignore_busy[1]} {I9/s_DUT_ignore_busy[2]} {I9/s_DUT_ignore_busy[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 6 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {I10/trigger_o[0]} {I10/trigger_o[1]} {I10/trigger_o[2]} {I10/trigger_o[3]} {I10/trigger_o[4]} {I10/trigger_o[5]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 6 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {triggers[0]} {triggers[1]} {triggers[2]} {triggers[3]} {triggers[4]} {triggers[5]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list buffer_full_i]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list I9/s_IgnoreShutterVeto]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list I10/s_post_veto_trigger0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list I10/s_post_veto_trigger1]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list I10/s_pre_veto_trigger_reg_n_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list I8/cmp_SyncGen/s_shutter]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list s_shutter]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list I8/cmp_SyncGen/s_trigger]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list I6/s_trigger]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list shutter_veto_o]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list I6/trigger_i]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list I10/cmp_coincidence_logic/trigger_o]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list veto_i]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list I9/veto_o]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_4x_logic]
projects/TLU_v1e/scripts/AIDA_testPower.py 0 → 100644
View file @ 75e77d84
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import time
#import miniTLU
from si5345 import si5345
from AD5665R import AD5665R
from PCA9539PW import PCA9539PW
from E24AA025E48T import E24AA025E48T
manager = uhal.ConnectionManager("file://./TLUconnection.xml")
hw = manager.getDevice("tlu")
# hw.getNode("A").write(255)
reg = hw.getNode("version").read()
hw.dispatch()
print "CHECK REG= ", hex(reg)
# #First I2C core
print ("Instantiating master I2C core:")
master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
master_I2C.state()
#
# #######################################
enableCore= False #Only need to run this once, after power-up
if (enableCore):
mystop=True
print " Write RegDir to set I/O[7] to output:"
myslave= 0x21
mycmd= [0x01, 0x7F]
nwords= 1
master_I2C.write(myslave, mycmd, mystop)
mystop=False
mycmd= [0x01]
master_I2C.write(myslave, mycmd, mystop)
res= master_I2C.read( myslave, nwords)
print "\tPost RegDir: ", res
#DAC CONFIGURATION BEGIN
if (False):
zeDAC1=AD5665R(master_I2C, 0x1C)
zeDAC1.setIntRef(intRef= False, verbose= True)
zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
if (True):
# #I2C EXPANDER CONFIGURATION BEGIN
IC6=PCA9539PW(master_I2C, 0x76)
#BANK 0
IC6.setInvertReg(0, 0x00)# 0= normal
IC6.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
IC6.setOutputs(0, 0x00)
res= IC6.getInputs(0)
print "IC6 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC6.setInvertReg(1, 0x00)# 0= normal
IC6.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
IC6.setOutputs(1, 0x00)
res= IC6.getInputs(1)
print "IC6 read back bank 1: 0x%X" % res[0]
# # #
IC7=PCA9539PW(master_I2C, 0x77)
#BANK 0
IC7.setInvertReg(0, 0x00)# 0= normal
IC7.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
IC7.setOutputs(0, 0x00)
res= IC7.getInputs(0)
print "IC7 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC7.setInvertReg(1, 0x00)# 0= normal
IC7.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
IC7.setOutputs(1, 0x00)
res= IC7.getInputs(1)
print "IC7 read back bank 1: 0x%X" % res[0]
# #I2C EXPANDER CONFIGURATION END
projects/TLU_v1e/scripts/AIDA_testScript_tx0_rx1_tx2.py 0 → 100644
View file @ 75e77d84
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import time
#import miniTLU
from si5345 import si5345
from AD5665R import AD5665R
from PCA9539PW import PCA9539PW
from E24AA025E48T import E24AA025E48T
manager = uhal.ConnectionManager("file://./TLUconnection.xml")
hw = manager.getDevice("tluLoop")
# hw.getNode("A").write(255)
reg = hw.getNode("version").read()
hw.dispatch()
print "CHECK REG= ", hex(reg)
# #First I2C core
print ("Instantiating master I2C core:")
master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
master_I2C.state()
# Plug cable into 1-->2 ( HDMI0-->1 ) look at 3 ( HDMI3 )
#
# #######################################
enableCore= True #Only need to run this once, after power-up
if (enableCore):
mystop=True
print " Write RegDir to set I/O[7] to output:"
myslave= 0x21
mycmd= [0x01, 0x7F]
nwords= 1
master_I2C.write(myslave, mycmd, mystop)
mystop=False
mycmd= [0x01]
master_I2C.write(myslave, mycmd, mystop)
res= master_I2C.read( myslave, nwords)
print "\tPost RegDir: ", res
# #######################################
#
# time.sleep(0.1)
# #Read the EPROM
# mystop=False
# nwords=6
# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
# myaddr= [0xfa]#0xfa
# master_I2C.write( myslave, myaddr, mystop)
# #res= master_I2C.read( 0x50, 6)
# res= master_I2C.read( myslave, nwords)
# print " PCB EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
# #######################################
#Second I2C core
#print ("Instantiating SFP I2C core:")
#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
#clock_I2C.state()
# #Third I2C core
# print ("Instantiating clock I2C core:")
# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
# clock_I2C.state()
# #time.sleep(0.01)
# #Read the EPROM
# mystop=False
# nwords=2
# myslave= 0x68 #DUNE CLOCK CHIP 0x68
# myaddr= [0x02 ]#0xfa
# clock_I2C.write( myslave, myaddr, mystop)
# #time.sleep(0.1)
# res= clock_I2C.read( myslave, nwords)
# print " CLOCK EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
#
#CLOCK CONFIGURATION BEGIN
zeClock=si5345(master_I2C, 0x68)
res= zeClock.getDeviceVersion()
zeClock.checkDesignID()
#zeClock.setPage(0, True)
#zeClock.getPage(True)
clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
zeClock.writeConfiguration(clkRegList)######
zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
iopower= zeClock.readRegister(0x0949, 1)
print " Clock IO power: 0x%X" % iopower[0]
lol= zeClock.readRegister(0x000E, 1)
print " Clock LOL (0x000E): 0x%X" % lol[0]
los= zeClock.readRegister(0x000D, 1)
print " Clock LOS (0x000D): 0x%X" % los[0]
#CLOCK CONFIGURATION END
#DAC CONFIGURATION BEGIN
zeDAC1=AD5665R(master_I2C, 0x13)
zeDAC1.setIntRef(intRef= False, verbose= True)
zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
zeDAC2=AD5665R(master_I2C, 0x1F)
zeDAC2.setIntRef(intRef= False, verbose= True)
zeDAC2.writeDAC(0x2fff, 3, verbose= True)
#DAC CONFIGURATION END
#EEPROM BEGIN
zeEEPROM= E24AA025E48T(master_I2C, 0x50)
res=zeEEPROM.readEEPROM(0xfa, 6)
result=" EEPROM ID:\n\t"
for iaddr in res:
result+="%02x "%(iaddr)
print result
#EEPROM END
# #I2C EXPANDER CONFIGURATION BEGIN
IC6=PCA9539PW(master_I2C, 0x74)
#BANK 0
IC6.setInvertReg(0, 0x00)# 0= normal
IC6.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC6.setOutputs(0, 0x77)
IC6.setOutputs(0, 0x0F)
res= IC6.getInputs(0)
print "IC6 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC6.setInvertReg(1, 0x00)# 0= normal
IC6.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC6.setOutputs(1, 0x77)
IC6.setOutputs(1, 0xFF)
res= IC6.getInputs(1)
print "IC6 read back bank 1: 0x%X" % res[0]
# # #
IC7=PCA9539PW(master_I2C, 0x75)
#BANK 0
IC7.setInvertReg(0, 0x00)# 0= normal
IC7.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC7.setOutputs(0, 0x00)
IC7.setOutputs(0, 0x0D)
res= IC7.getInputs(0)
print "IC7 read back bank 0: 0x%X" % res[0]
#
#BANK 1
# LEDs and HDMI power
IC7.setInvertReg(1, 0x00)# 0= normal
IC7.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC7.setOutputs(1, 0xB0)
IC7.setOutputs(1, 0xFF)
res= IC7.getInputs(1)
print "IC7 read back bank 1: 0x%X" % res[0]
# #I2C EXPANDER CONFIGURATION END
# #Reset counters
#cmd = int("0x0", 16) #write 0x2 to reset
#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
#hw.dispatch()
#print "Trigger Reset: 0x%X" % restatus
## #Read trigger inputs
#myreg= [-1, -1, -1, -1, -1, -1]
#for inputN in range(0, 6):
# regString= "triggerInputs.ThrCount%dR" % inputN
# myreg[inputN]= hw.getNode(regString).read()
# hw.dispatch()
# print regString, myreg[inputN]
## Read ev formatter
#cmd = int("0x0", 16) #
##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
#hw.dispatch()
#print "Event Formatter Record: 0x%X" % efstatus
projects/TLU_v1e/scripts/AIDA_testScript_tx0_rx2_tx1.py 0 → 100644
View file @ 75e77d84
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import time
#import miniTLU
from si5345 import si5345
from AD5665R import AD5665R
from PCA9539PW import PCA9539PW
from E24AA025E48T import E24AA025E48T
manager = uhal.ConnectionManager("file://./TLUconnection.xml")
hw = manager.getDevice("tlu")
# hw.getNode("A").write(255)
reg = hw.getNode("version").read()
hw.dispatch()
print "CHECK REG= ", hex(reg)
# #First I2C core
print ("Instantiating master I2C core:")
master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
master_I2C.state()
# Plug cable into 1-->2 ( HDMI0-->1 ) look at 3 ( HDMI3 )
#
# #######################################
enableCore= True #Only need to run this once, after power-up
if (enableCore):
mystop=True
print " Write RegDir to set I/O[7] to output:"
myslave= 0x21
mycmd= [0x01, 0x7F]
nwords= 1
master_I2C.write(myslave, mycmd, mystop)
mystop=False
mycmd= [0x01]
master_I2C.write(myslave, mycmd, mystop)
res= master_I2C.read( myslave, nwords)
print "\tPost RegDir: ", res
# #######################################
#
# time.sleep(0.1)
# #Read the EPROM
# mystop=False
# nwords=6
# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
# myaddr= [0xfa]#0xfa
# master_I2C.write( myslave, myaddr, mystop)
# #res= master_I2C.read( 0x50, 6)
# res= master_I2C.read( myslave, nwords)
# print " PCB EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
# #######################################
#Second I2C core
#print ("Instantiating SFP I2C core:")
#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
#clock_I2C.state()
# #Third I2C core
# print ("Instantiating clock I2C core:")
# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
# clock_I2C.state()
# #time.sleep(0.01)
# #Read the EPROM
# mystop=False
# nwords=2
# myslave= 0x68 #DUNE CLOCK CHIP 0x68
# myaddr= [0x02 ]#0xfa
# clock_I2C.write( myslave, myaddr, mystop)
# #time.sleep(0.1)
# res= clock_I2C.read( myslave, nwords)
# print " CLOCK EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
#
#CLOCK CONFIGURATION BEGIN
zeClock=si5345(master_I2C, 0x68)
res= zeClock.getDeviceVersion()
zeClock.checkDesignID()
#zeClock.setPage(0, True)
#zeClock.getPage(True)
clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
zeClock.writeConfiguration(clkRegList)######
zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
iopower= zeClock.readRegister(0x0949, 1)
print " Clock IO power: 0x%X" % iopower[0]
lol= zeClock.readRegister(0x000E, 1)
print " Clock LOL (0x000E): 0x%X" % lol[0]
los= zeClock.readRegister(0x000D, 1)
print " Clock LOS (0x000D): 0x%X" % los[0]
#CLOCK CONFIGURATION END
#DAC CONFIGURATION BEGIN
zeDAC1=AD5665R(master_I2C, 0x13)
zeDAC1.setIntRef(intRef= False, verbose= True)
zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
zeDAC2=AD5665R(master_I2C, 0x1F)
zeDAC2.setIntRef(intRef= False, verbose= True)
zeDAC2.writeDAC(0x2fff, 3, verbose= True)
#DAC CONFIGURATION END
#EEPROM BEGIN
zeEEPROM= E24AA025E48T(master_I2C, 0x50)
res=zeEEPROM.readEEPROM(0xfa, 6)
result=" EEPROM ID:\n\t"
for iaddr in res:
result+="%02x "%(iaddr)
print result
#EEPROM END
# #I2C EXPANDER CONFIGURATION BEGIN
IC6=PCA9539PW(master_I2C, 0x74)
#BANK 0
IC6.setInvertReg(0, 0x00)# 0= normal
IC6.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC6.setOutputs(0, 0x77)
IC6.setOutputs(0, 0xFF)
res= IC6.getInputs(0)
print "IC6 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC6.setInvertReg(1, 0x00)# 0= normal
IC6.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC6.setOutputs(1, 0x77)
IC6.setOutputs(1, 0xF0)
res= IC6.getInputs(1)
print "IC6 read back bank 1: 0x%X" % res[0]
# # #
IC7=PCA9539PW(master_I2C, 0x75)
#BANK 0
IC7.setInvertReg(0, 0x00)# 0= normal
IC7.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC7.setOutputs(0, 0x00)
IC7.setOutputs(0, 0x0B)
res= IC7.getInputs(0)
print "IC7 read back bank 0: 0x%X" % res[0]
#
#BANK 1
# LEDs and HDMI power
IC7.setInvertReg(1, 0x00)# 0= normal
IC7.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC7.setOutputs(1, 0xB0)
IC7.setOutputs(1, 0xFF)
res= IC7.getInputs(1)
print "IC7 read back bank 1: 0x%X" % res[0]
# #I2C EXPANDER CONFIGURATION END
# #Reset counters
#cmd = int("0x0", 16) #write 0x2 to reset
#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
#hw.dispatch()
#print "Trigger Reset: 0x%X" % restatus
## #Read trigger inputs
#myreg= [-1, -1, -1, -1, -1, -1]
#for inputN in range(0, 6):
# regString= "triggerInputs.ThrCount%dR" % inputN
# myreg[inputN]= hw.getNode(regString).read()
# hw.dispatch()
# print regString, myreg[inputN]
## Read ev formatter
#cmd = int("0x0", 16) #
##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
#hw.dispatch()
#print "Event Formatter Record: 0x%X" % efstatus
projects/TLU_v1e/scripts/AIDA_testScript_tx0_rx3_tx1.py 0 → 100644
View file @ 75e77d84
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import time
#import miniTLU
from si5345 import si5345
from AD5665R import AD5665R
from PCA9539PW import PCA9539PW
from E24AA025E48T import E24AA025E48T
manager = uhal.ConnectionManager("file://./TLUconnection.xml")
hw = manager.getDevice("tlu")
# hw.getNode("A").write(255)
reg = hw.getNode("version").read()
hw.dispatch()
print "CHECK REG= ", hex(reg)
# #First I2C core
print ("Instantiating master I2C core:")
master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
master_I2C.state()
# Plug cable into 1-->2 ( HDMI0-->1 ) look at 3 ( HDMI3 )
#
# #######################################
enableCore= True #Only need to run this once, after power-up
if (enableCore):
mystop=True
print " Write RegDir to set I/O[7] to output:"
myslave= 0x21
mycmd= [0x01, 0x7F]
nwords= 1
master_I2C.write(myslave, mycmd, mystop)
mystop=False
mycmd= [0x01]
master_I2C.write(myslave, mycmd, mystop)
res= master_I2C.read( myslave, nwords)
print "\tPost RegDir: ", res
# #######################################
#
# time.sleep(0.1)
# #Read the EPROM
# mystop=False
# nwords=6
# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
# myaddr= [0xfa]#0xfa
# master_I2C.write( myslave, myaddr, mystop)
# #res= master_I2C.read( 0x50, 6)
# res= master_I2C.read( myslave, nwords)
# print " PCB EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
# #######################################
#Second I2C core
#print ("Instantiating SFP I2C core:")
#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
#clock_I2C.state()
# #Third I2C core
# print ("Instantiating clock I2C core:")
# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
# clock_I2C.state()
# #time.sleep(0.01)
# #Read the EPROM
# mystop=False
# nwords=2
# myslave= 0x68 #DUNE CLOCK CHIP 0x68
# myaddr= [0x02 ]#0xfa
# clock_I2C.write( myslave, myaddr, mystop)
# #time.sleep(0.1)
# res= clock_I2C.read( myslave, nwords)
# print " CLOCK EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
#
#CLOCK CONFIGURATION BEGIN
zeClock=si5345(master_I2C, 0x68)
res= zeClock.getDeviceVersion()
zeClock.checkDesignID()
#zeClock.setPage(0, True)
#zeClock.getPage(True)
clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
zeClock.writeConfiguration(clkRegList)######
zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
iopower= zeClock.readRegister(0x0949, 1)
print " Clock IO power: 0x%X" % iopower[0]
lol= zeClock.readRegister(0x000E, 1)
print " Clock LOL (0x000E): 0x%X" % lol[0]
los= zeClock.readRegister(0x000D, 1)
print " Clock LOS (0x000D): 0x%X" % los[0]
#CLOCK CONFIGURATION END
#DAC CONFIGURATION BEGIN
zeDAC1=AD5665R(master_I2C, 0x13)
zeDAC1.setIntRef(intRef= False, verbose= True)
zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
zeDAC2=AD5665R(master_I2C, 0x1F)
zeDAC2.setIntRef(intRef= False, verbose= True)
zeDAC2.writeDAC(0x2fff, 3, verbose= True)
#DAC CONFIGURATION END
#EEPROM BEGIN
zeEEPROM= E24AA025E48T(master_I2C, 0x50)
res=zeEEPROM.readEEPROM(0xfa, 6)
result=" EEPROM ID:\n\t"
for iaddr in res:
result+="%02x "%(iaddr)
print result
#EEPROM END
# #I2C EXPANDER CONFIGURATION BEGIN
IC6=PCA9539PW(master_I2C, 0x74)
#BANK 0
IC6.setInvertReg(0, 0x00)# 0= normal
IC6.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC6.setOutputs(0, 0x77)
IC6.setOutputs(0, 0xFF)
res= IC6.getInputs(0)
print "IC6 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC6.setInvertReg(1, 0x00)# 0= normal
IC6.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC6.setOutputs(1, 0x77)
IC6.setOutputs(1, 0x0F)
res= IC6.getInputs(1)
print "IC6 read back bank 1: 0x%X" % res[0]
# # #
IC7=PCA9539PW(master_I2C, 0x75)
#BANK 0
IC7.setInvertReg(0, 0x00)# 0= normal
IC7.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC7.setOutputs(0, 0x00)
IC7.setOutputs(0, 0x07)
res= IC7.getInputs(0)
print "IC7 read back bank 0: 0x%X" % res[0]
#
#BANK 1
# LEDs and HDMI power
IC7.setInvertReg(1, 0x00)# 0= normal
IC7.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC7.setOutputs(1, 0xB0)
IC7.setOutputs(1, 0xFF)
res= IC7.getInputs(1)
print "IC7 read back bank 1: 0x%X" % res[0]
# #I2C EXPANDER CONFIGURATION END
# #Reset counters
#cmd = int("0x0", 16) #write 0x2 to reset
#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
#hw.dispatch()
#print "Trigger Reset: 0x%X" % restatus
## #Read trigger inputs
#myreg= [-1, -1, -1, -1, -1, -1]
#for inputN in range(0, 6):
# regString= "triggerInputs.ThrCount%dR" % inputN
# myreg[inputN]= hw.getNode(regString).read()
# hw.dispatch()
# print regString, myreg[inputN]
## Read ev formatter
#cmd = int("0x0", 16) #
##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
#hw.dispatch()
#print "Event Formatter Record: 0x%X" % efstatus
projects/TLU_v1e/scripts/AIDA_testScript_tx1_rx0_tx2.py 0 → 100644
View file @ 75e77d84
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import time
#import miniTLU
from si5345 import si5345
from AD5665R import AD5665R
from PCA9539PW import PCA9539PW
from E24AA025E48T import E24AA025E48T
manager = uhal.ConnectionManager("file://./TLUconnection.xml")
hw = manager.getDevice("tlu")
# hw.getNode("A").write(255)
reg = hw.getNode("version").read()
hw.dispatch()
print "CHECK REG= ", hex(reg)
# #First I2C core
print ("Instantiating master I2C core:")
master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
master_I2C.state()
# Plug cable into 1-->2 ( HDMI0-->1 ) look at 3 ( HDMI3 )
#
# #######################################
enableCore= True #Only need to run this once, after power-up
if (enableCore):
mystop=True
print " Write RegDir to set I/O[7] to output:"
myslave= 0x21
mycmd= [0x01, 0x7F]
nwords= 1
master_I2C.write(myslave, mycmd, mystop)
mystop=False
mycmd= [0x01]
master_I2C.write(myslave, mycmd, mystop)
res= master_I2C.read( myslave, nwords)
print "\tPost RegDir: ", res
# #######################################
#
# time.sleep(0.1)
# #Read the EPROM
# mystop=False
# nwords=6
# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
# myaddr= [0xfa]#0xfa
# master_I2C.write( myslave, myaddr, mystop)
# #res= master_I2C.read( 0x50, 6)
# res= master_I2C.read( myslave, nwords)
# print " PCB EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
# #######################################
#Second I2C core
#print ("Instantiating SFP I2C core:")
#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
#clock_I2C.state()
# #Third I2C core
# print ("Instantiating clock I2C core:")
# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
# clock_I2C.state()
# #time.sleep(0.01)
# #Read the EPROM
# mystop=False
# nwords=2
# myslave= 0x68 #DUNE CLOCK CHIP 0x68
# myaddr= [0x02 ]#0xfa
# clock_I2C.write( myslave, myaddr, mystop)
# #time.sleep(0.1)
# res= clock_I2C.read( myslave, nwords)
# print " CLOCK EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
#
#CLOCK CONFIGURATION BEGIN
zeClock=si5345(master_I2C, 0x68)
res= zeClock.getDeviceVersion()
zeClock.checkDesignID()
#zeClock.setPage(0, True)
#zeClock.getPage(True)
clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
zeClock.writeConfiguration(clkRegList)######
zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
iopower= zeClock.readRegister(0x0949, 1)
print " Clock IO power: 0x%X" % iopower[0]
lol= zeClock.readRegister(0x000E, 1)
print " Clock LOL (0x000E): 0x%X" % lol[0]
los= zeClock.readRegister(0x000D, 1)
print " Clock LOS (0x000D): 0x%X" % los[0]
#CLOCK CONFIGURATION END
#DAC CONFIGURATION BEGIN
zeDAC1=AD5665R(master_I2C, 0x13)
zeDAC1.setIntRef(intRef= False, verbose= True)
zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
zeDAC2=AD5665R(master_I2C, 0x1F)
zeDAC2.setIntRef(intRef= False, verbose= True)
zeDAC2.writeDAC(0x2fff, 3, verbose= True)
#DAC CONFIGURATION END
#EEPROM BEGIN
zeEEPROM= E24AA025E48T(master_I2C, 0x50)
res=zeEEPROM.readEEPROM(0xfa, 6)
result=" EEPROM ID:\n\t"
for iaddr in res:
result+="%02x "%(iaddr)
print result
#EEPROM END
# #I2C EXPANDER CONFIGURATION BEGIN
IC6=PCA9539PW(master_I2C, 0x74)
#BANK 0
IC6.setInvertReg(0, 0x00)# 0= normal
IC6.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC6.setOutputs(0, 0x77)
IC6.setOutputs(0, 0xF0)
res= IC6.getInputs(0)
print "IC6 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC6.setInvertReg(1, 0x00)# 0= normal
IC6.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC6.setOutputs(1, 0x77)
IC6.setOutputs(1, 0xFF)
res= IC6.getInputs(1)
print "IC6 read back bank 1: 0x%X" % res[0]
# # #
IC7=PCA9539PW(master_I2C, 0x75)
#BANK 0
IC7.setInvertReg(0, 0x00)# 0= normal
IC7.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC7.setOutputs(0, 0x00)
IC7.setOutputs(0, 0x0E)
res= IC7.getInputs(0)
print "IC7 read back bank 0: 0x%X" % res[0]
#
#BANK 1
# LEDs and HDMI power
IC7.setInvertReg(1, 0x00)# 0= normal
IC7.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
#IC7.setOutputs(1, 0xB0)
IC7.setOutputs(1, 0xFF)
res= IC7.getInputs(1)
print "IC7 read back bank 1: 0x%X" % res[0]
# #I2C EXPANDER CONFIGURATION END
# #Reset counters
#cmd = int("0x0", 16) #write 0x2 to reset
#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
#hw.dispatch()
#print "Trigger Reset: 0x%X" % restatus
## #Read trigger inputs
#myreg= [-1, -1, -1, -1, -1, -1]
#for inputN in range(0, 6):
# regString= "triggerInputs.ThrCount%dR" % inputN
# myreg[inputN]= hw.getNode(regString).read()
# hw.dispatch()
# print regString, myreg[inputN]
## Read ev formatter
#cmd = int("0x0", 16) #
##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
#hw.dispatch()
#print "Event Formatter Record: 0x%X" % efstatus
projects/TLU_v1e/scripts/TLU_v1e.py
View file @ 75e77d84
......@@ -12,11 +12,15 @@ from I2CuHal import I2CCore
from si5345 import si5345 # Library for clock chip
from AD5665R import AD5665R # Library for DAC
from PCA9539PW import PCA9539PW # Library for serial line expander
from I2CDISP import CFA632 #Library for display
from TLU_powermodule import PWRLED
from ATSHA204A import ATSHA204A
class TLU:
"""docstring for TLU"""
def __init__(self, dev_name, man_file, parsed_cfg):
uhal.setLogLevelTo(uhal.LogLevel.NOTICE) ## Get rid of initial flood of IPBUS messages
self.isRunning= False
section_name= "Producer.fmctlu"
......@@ -55,6 +59,15 @@ class TLU:
enableCore= True #Only need to run this once, after power-up
self.enableCore()
####### EEPROM AX3 testing
doAtmel= False
if doAtmel:
self.ax3eeprom= ATSHA204A(self.TLU_I2C, 0x64)
print "shiftR\tdatBit\tcrcBit\tcrcReg \n", self.ax3eeprom._CalculateCrc([255, 12, 54, 28, 134, 89], 3)
self.ax3eeprom._wake(True, True)
print self.ax3eeprom._GetCommandPacketSize(8)
#self.eepromAX3read()
####### EEPROM AX3 testing end
# Instantiate clock chip and configure it (if necessary)
#self.zeClock=si5345(self.TLU_I2C, 0x68)
......@@ -64,7 +77,7 @@ class TLU:
if (int(parsed_cfg.get(section_name, "CONFCLOCK"), 16)):
#clkRegList= self.zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
clkRegList= self.zeClock.parse_clk(parsed_cfg.get(section_name, "CLOCK_CFG_FILE"))
self.zeClock.writeConfiguration(clkRegList)######
self.zeClock.writeConfiguration(clkRegList, self.verbose)######
self.zeClock.checkDesignID()
......@@ -101,6 +114,43 @@ class TLU:
self.IC7.setIOReg(1, 0x00)# 0= output, 1= input
self.IC7.setOutputs(1, 0xB0)# If output, set to XX
#Instantiate Display
self.DISP=CFA632(self.TLU_I2C, 0x2A) #
#Instantiate Power/Led Module
dac_addr_module= int(parsed_cfg.get(section_name, "I2C_DACModule_Addr"), 16)
exp1_addr= int(parsed_cfg.get(section_name, "I2C_EXP1Module_Addr"), 16)
exp2_addr= int(parsed_cfg.get(section_name, "I2C_EXP2Module_Addr"), 16)
pmtCtrVMax= parsed_cfg.getfloat(section_name, "PMT_vCtrlMax")
self.pwdled= PWRLED(self.TLU_I2C, dac_addr_module, pmtCtrVMax, exp1_addr, exp2_addr)
#self.pwdled.setIndicatorRGB(1, [0, 0, 1])
#self.pwdled.setIndicatorRGB(2, [0, 0, 1])
#self.pwdled.setIndicatorRGB(3, [0, 0, 1])
#self.pwdled.setIndicatorRGB(4, [0, 0, 1])
#self.pwdled.setIndicatorRGB(5, [0, 0, 1])
#self.pwdled.setIndicatorRGB(6, [0, 0, 1])
#self.pwdled.setIndicatorRGB(7, [0, 0, 1])
#self.pwdled.setIndicatorRGB(8, [0, 0, 1])
#self.pwdled.setIndicatorRGB(9, [0, 0, 1])
#self.pwdled.setIndicatorRGB(10, [0, 0, 1])
#self.pwdled.setIndicatorRGB(11, [0, 0, 1])
self.pwdled.allGreen()
time.sleep(0.1)
self.pwdled.allBlue()
time.sleep(0.1)
self.pwdled.allBlack()
time.sleep(0.1)
#self.pwdled.kitt()
time.sleep(0.1)
#self.pwdled.allBlack()
#self.pwdled.allRed()
#time.sleep(0.1)
self.pwdled.allWhite()
##################################################################################################################################
##################################################################################################################################
......@@ -180,7 +230,10 @@ class TLU:
newStatus= oldStatus & ~mask #set both bits to zero
outStat= ""
if clkSrc==0:
newStatus = newStatus | mask
#--- ./TLU_v1e.py 183
# newStatus = newStatus | mask
#+++ /users/phdgc/firmware_AIDA_PaoloGB/firmware_AIDA/TLU_v1e/scripts/TLU_v1e.py 233
newStatus = newStatus
outStat= "disabled"
elif clkSrc==1:
newStatus = newStatus | maskLow
......@@ -194,6 +247,23 @@ class TLU:
self.IC7.setOutputs(bank, newStatus)
return newStatus
def eepromAX3read(self):
mystop=True
print " Reading AX3 eeprom (not working 100% yet):"
myslave= 0x64
self.TLU_I2C.write(myslave, [0x02, 0x00])
nwords= 5
res= self.TLU_I2C.read( myslave, nwords)
print "\tAX3 awake: ", res
mystop=True
nwords= 7
#mycmd= [0x03, 0x07, 0x02, 0x00, 0x00, 0x00, 0x1e, 0x2d]#conf 0?
mycmd= [0x03, 0x07, 0x02, 0x00, 0x01, 0x00, 0x17, 0xad]#conf 1 <<< seems to reply with correct error code (0)
#mycmd= [0x03, 0x07, 0x02, 0x02, 0x00, 0x00, 0x1d, 0xa8]#data 0?
self.TLU_I2C.write(myslave, mycmd, mystop)
res= self.TLU_I2C.read( myslave, nwords)
print "\tAX3 EEPROM: ", res
def enableClkLEMO(self, enable= False, verbose= False):
## Enable or disable the output clock to the differential LEMO output
bank=1
......@@ -634,12 +704,8 @@ class TLU:
self.getVetoDUT()
def setVetoShutters(self, newState):
if newState:
print " IgnoreShutterVetoW SET TO LISTEN FOR VETO FROM SHUTTER"
cmd= int("0x0",16)
else:
print " IgnoreShutterVetoW SET TO IGNORE VETO FROM SHUTTER"
cmd= int("0x1",16)
cmd = int(newState)
print " Setting IgnoreShutterVetoW to ", hex(newState)
self.hw.getNode("DUTInterfaces.IgnoreShutterVetoW").write(cmd)
self.hw.dispatch()
self.getVetoShutters()
......@@ -866,6 +932,16 @@ class TLU:
cmd = int("0x0",16)
self.setInternalTrg(cmd)
# # Set the control voltages for the PMTs
PMT1_V= parsed_cfg.getfloat(section_name, "PMT1_V")
PMT2_V= parsed_cfg.getfloat(section_name, "PMT2_V")
PMT3_V= parsed_cfg.getfloat(section_name, "PMT3_V")
PMT4_V= parsed_cfg.getfloat(section_name, "PMT4_V")
self.pwdled.setVch(0, PMT1_V, True)
self.pwdled.setVch(1, PMT2_V, True)
self.pwdled.setVch(2, PMT3_V, True)
self.pwdled.setVch(3, PMT4_V, True)
# # Set pulse stretches
str0= parsed_cfg.getint(section_name, "in0_STR")
str1= parsed_cfg.getint(section_name, "in1_STR")
......
projects/TLU_v1e/scripts/initTLU_merged.py 0 → 100644
View file @ 75e77d84
#
# Function to initialize TLU
#
# David Cussans, October 2015
#
# Nasty hack - use both PyChips and uHAL ( for block read ... )
from PyChipsUser import *
from FmcTluI2c import *
import uhal
import sys
import time
def startTLU( uhalDevice , pychipsBoard , writeTimestamps):
print "RESETTING FIFO"
pychipsBoard.write("EventFifoCSR",0x2)
eventFifoFillLevel = pychipsBoard.read("EventFifoFillLevel")
print "FIFO FILL LEVEL AFTER RESET= " , eventFifoFillLevel
if writeTimestamps:
print "ENABLING DATA RECORDING"
pychipsBoard.write("Enable_Record_Data",1)
else:
print "Disabling data recording"
pychipsBoard.write("Enable_Record_Data",0)
print "Pulsing T0"
pychipsBoard.write("PulseT0",1)
print "Turning off software trigger veto"
pychipsBoard.write("TriggerVetoW",0)
print "TLU is running"
def stopTLU( uhalDevice , pychipsBoard ):
print "Turning on software trigger veto"
pychipsBoard.write("TriggerVetoW",1)
print "TLU triggers are stopped"
def initTLU( uhalDevice , pychipsBoard , listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage ):
print "SETTING UP AIDA TLU"
fwVersion = uhalDevice.getNode("version").read()
uhalDevice.dispatch()
print "\tVersion (uHAL)= " , hex(fwVersion)
print "\tTurning on software trigger veto"
pychipsBoard.write("TriggerVetoW",1)
# Check the bus for I2C devices
pychipsBoardi2c = FmcTluI2c(pychipsBoard)
print "\tScanning I2C bus:"
scanResults = pychipsBoardi2c.i2c_scan()
#print scanResults
print '\t', ', '.join(scanResults), '\n'
boardId = pychipsBoardi2c.get_serial_number()
print "\tFMC-TLU serial number= " , boardId
resetClocks = 0
resetSerdes = 0
# set DACs to -200mV
print "\tSETTING ALL DAC THRESHOLDS TO" , thresholdVoltage , "V"
pychipsBoardi2c.set_threshold_voltage(7, thresholdVoltage)
clockStatus = pychipsBoard.read("LogicClocksCSR")
print "\tCLOCK STATUS (should be 3 if all clocks locked)= " , hex(clockStatus)
assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
if resetClocks:
print "Resetting clocks"
pychipsBoard.write("LogicRst", 1 )
clockStatus = pychipsBoard.read("LogicClocksCSR")
print "Clock status after reset = " , hex(clockStatus)
inputStatus = pychipsBoard.read("SerdesRstR")
print "Input status = " , hex(inputStatus)
if resetSerdes:
pychipsBoard.write("SerdesRstW", 0x00000003 )
inputStatus = pychipsBoard.read("SerdesRstR")
print "Input status during reset = " , hex(inputStatus)
pychipsBoard.write("SerdesRstW", 0x00000000 )
inputStatus = pychipsBoard.read("SerdesRstR")
print "Input status after reset = " , hex(inputStatus)
pychipsBoard.write("SerdesRstW", 0x00000004 )
inputStatus = pychipsBoard.read("SerdesRstR")
print "Input status during calibration = " , hex(inputStatus)
pychipsBoard.write("SerdesRstW", 0x00000000 )
inputStatus = pychipsBoard.read("SerdesRstR")
print "Input status after calibration = " , hex(inputStatus)
inputStatus = pychipsBoard.read("SerdesRstR")
print "\tINPUT STATUS= " , hex(inputStatus)
count0 = pychipsBoard.read("ThrCount0R")
print "\t Count 0= " , count0
count1 = pychipsBoard.read("ThrCount1R")
print "\t Count 1= " , count1
count2 = pychipsBoard.read("ThrCount2R")
print "\t Count 2= " , count2
count3 = pychipsBoard.read("ThrCount3R")
print "\t Count 3= " , count3
# Stop internal triggers until setup complete
pychipsBoard.write("InternalTriggerIntervalW",0)
print "\tSETTING INPUT COINCIDENCE WINDOW TO",pulseStretch,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
pychipsBoard.write("PulseStretchW",int(pulseStretch))
pulseStretchR = pychipsBoard.read("PulseStretchR")
print "\t Pulse stretch read back as:", hex(pulseStretchR)
# assert (int(pulseStretch) == pulseStretchR) , "Pulse stretch read-back doesn't equal written value"
print "\tSETTING INPUT TRIGGER DELAY TO",pulseDelay , "[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
pychipsBoard.write("PulseDelayW",int(pulseDelay))
pulseDelayR = pychipsBoard.read("PulseDelayR")
print "\t Pulse delay read back as:", hex(pulseDelayR)
print "\tSETTING TRIGGER PATTERN (for external triggers) TO 0x%08X. Two 16-bit patterns packed into 32 bit word " %(triggerPattern)
pychipsBoard.write("TriggerPatternW",int(triggerPattern))
triggerPatternR = pychipsBoard.read("TriggerPatternR")
print "\t Trigger pattern read back as: 0x%08X " % (triggerPatternR)
print "\tENABLING DUT(s): Mask= " , hex(DUTMask)
pychipsBoard.write("DUTMaskW",int(DUTMask))
DUTMaskR = pychipsBoard.read("DUTMaskR")
print "\t DUTMask read back as:" , hex(DUTMaskR)
print "\tSETTING ALL DUTs IN AIDA MODE"
pychipsBoard.write("DUTInterfaceModeW", 0xFF)
DUTInterfaceModeR = pychipsBoard.read("DUTInterfaceModeR")
print "\t DUT mode read back as:" , DUTInterfaceModeR
print "\tSET DUT MODE MODIFIER"
pychipsBoard.write("DUTInterfaceModeModifierW", 0xFF)
DUTInterfaceModeModifierR = pychipsBoard.read("DUTInterfaceModeModifierR")
print "\t DUT mode modifier read back as:" , DUTInterfaceModeModifierR
if listenForTelescopeShutter:
print "\tSET IgnoreShutterVetoW TO LISTEN FOR VETO FROM SHUTTER"
pychipsBoard.write("IgnoreShutterVetoW",0)
else:
print "\tSET IgnoreShutterVetoW TO IGNORE VETO FROM SHUTTER"
pychipsBoard.write("IgnoreShutterVetoW",1)
IgnoreShutterVeto = pychipsBoard.read("IgnoreShutterVetoR")
print "\t IgnoreShutterVeto read back as:" , IgnoreShutterVeto
print "\tSETTING IGNORE VETO BY DUT BUSY MASK TO" , hex(ignoreDUTBusy)
pychipsBoard.write("IgnoreDUTBusyW",int(ignoreDUTBusy))
IgnoreDUTBusy = pychipsBoard.read("IgnoreDUTBusyR")
print "\t IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusy)
#print "Enabling handshake: No-handshake"
#board.write("HandshakeTypeW",1)
print "\tSETTING INTERNAL TRIGGER INTERVAL TO" , triggerInterval , "(zero= no internal triggers)"
if triggerInterval == 0:
internalTriggerFreq = 0
else:
internalTriggerFreq = 160000.0/triggerInterval
print "\tINTERNAL TRIGGER FREQUENCY= " , internalTriggerFreq , " kHz"
pychipsBoard.write("InternalTriggerIntervalW",triggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
trigIntervalR = pychipsBoard.read("InternalTriggerIntervalR")
print "\t Trigger interval read back as:", trigIntervalR
print "AIDA TLU SETUP COMPLETED"
projects/TLU_v1e/scripts/localConf.conf
View file @ 75e77d84
......@@ -16,6 +16,13 @@ HDMI2_clk = 1
HDMI3_clk = 1
HDMI4_clk = 1
# Control voltages for the PMTs <
PMT1_V= 0.5
PMT2_V= 0.7
PMT3_V= 0.9
PMT4_V= 1
# Enable/disable differential LEMO CLOCK
LEMOclk = 1
......@@ -45,7 +52,7 @@ DACThreshold4 = -0.12
DACThreshold5 = -0.12
# Define which DUTs are ON
DutMask = F
DutMask = 0xF
# Define mode of DUT (00 EUDET, 11 AIDA)
DUTMaskMode= 0xFFFFFFFF
......@@ -54,16 +61,18 @@ DUTMaskMode= 0xFFFFFFFF
DUTMaskModeModifier= 0x0
# Ignore busy from a specific DUT
DUTIgnoreBusy = F
DUTIgnoreBusy = 0xF
# Ignore the SHUTTER veto on a specific DUT
# Ignore the SHUTTER veto
DUTIgnoreShutterVeto = 0x0
# Generate internal triggers (in Hz, 0= no triggers)
InternalTriggerFreq = 1000000
#InternalTriggerFreq = 0
ShutterControl = 0
# Bit-0 of shutter control = enable shutter. Bit-1 = enable internal shutter generator
ShutterControl = 3
ShutterSource = 5
InternalShutterInterval = 1024
ShutterOnTime = 200
......
projects/TLU_v1e/scripts/localIni.ini
View file @ 75e77d84
......@@ -25,10 +25,19 @@ I2C_ID_Addr = 0x50
I2C_EXP1_Addr = 0x74
#I2C address of 2st expander PCA9539PW
I2C_EXP2_Addr = 0x75
#I2C address of AD5665R on powermodule
I2C_DACModule_Addr = 0x1C
# Max value for control voltage on PMTs (usually 1 V)
PMT_vCtrlMax= 1.0
#I2C address of 1st expander PCA9539PW on powermodule
I2C_EXP1Module_Addr = 0x76
#I2C address of 2nd expander PCA9539PW on powermodule
I2C_EXP2Module_Addr = 0x77
##CONFCLOCK 0= skip clock configuration, 1= configure si5345
CONFCLOCK= 0
CLOCK_CFG_FILE = /users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/scripts/localClock.txt
CONFCLOCK= 1
CLOCK_CFG_FILE = ./localClock.txt
[LogCollector.log]
......
projects/TLU_v1e/scripts/packages/AD5665R.py
View file @ 75e77d84
......@@ -20,7 +20,8 @@ class AD5665R:
cmdDAC= [0x38,0x00,0x00]
self.i2c.write( self.slaveaddr, cmdDAC, mystop)
if verbose:
print "DAC int ref:", intRef
print " AD5665R"
print "\tDAC int ref:", intRef
def writeDAC(self, dacCode, channel, verbose=False):
......
projects/TLU_v1e/scripts/packages/ADN2814ACPZ.py 0 → 100644
View file @ 75e77d84
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
import math
class ADN2814ACPZ:
#Class to configure the ADN2814 clock and data recovery chip (CDR)
# The I2C address can either be 0x40 or 0x60
def __init__(self, i2c, slaveaddr=0x40):
self.i2c = i2c
self.slaveaddr = slaveaddr
self.regDictionary= {'freq0': 0x0, 'freq1': 0x1, 'freq2': 0x2, 'rate': 0x3, 'misc': 0x4, 'ctrla': 0x8, 'ctrlb': 0x9, 'ctrlc': 0x11}
def writeReg(self, regN, regContent, verbose=False):
#Basic functionality to write to register.
regContent= regContent & 0xFF
mystop=True
cmd= [regN, regContent]
self.i2c.write( self.slaveaddr, cmd, mystop)
def readReg(self, regN, nwords, verbose=False):
#Basic functionality to read from register.
mystop=False
self.i2c.write( self.slaveaddr, [regN], mystop)
res= self.i2c.read( self.slaveaddr, nwords)
return res
def readf0(self, verbose=False):
res= self.readReg(self.regDictionary['freq0'], 1, False)
if verbose:
print "\tfreq0 is", res[0]
return res[0]
def readf1(self, verbose=False):
res= self.readReg(self.regDictionary['freq1'], 1, False)
if verbose:
print "\tfreq1 is", res[0]
return res[0]
def readf2(self, verbose=False):
res= self.readReg(self.regDictionary['freq2'], 1, False)
if verbose:
print "\tfreq2 is", res[0]
return res[0]
def readFrequency(self, verbose=False):
# write 1 to CTRLA[1]
# reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3]
# read back MISC[2], if 0 the measurement is not complete (typ 80 ms). If 1 the data rate can be read by reading FREQ[22:0]
# read FREQ2, FREQ1, FREQ0
# rate= (FREQ[22:0]xFrefclk)/2^(14+SEL_RATE)
return
def readLOLstatus(self, verbose=False):
# return the status of the LOL bit MISC[3] and the STATIC LOL MISC[4]
# the STATIC LOL is asserted if a LOL condition occurred and remains asserted
# until cleared by writing 1 followed by 0 to the CTRLB[6] bit
misc= self.readReg(self.regDictionary['misc'], 1, False)[0]
staticLOL= (misc & 0x10000) >> 4
LOL= (misc & 0x1000) >> 3
if verbose:
print "MISC=", misc, "LOL=", LOL, "StaticLOL=", staticLOL
return [LOL, staticLOL]
def readRate(self, verbose=False):
rate_msb= self.readReg(self.regDictionary['rate'], 1, False)[0]
rate_lsb= self.readReg(self.regDictionary['misc'], 1, False)[0]
rate_lsb= 0x1 & rate_lsb
rate= (rate_msb << 1) | rate_lsb
if verbose:
print "\tcoarse rate is", rate
return rate
def _writeCTRLA(self, fRef, dataRatio, measureDataRate, lockToRef, verbose=False):
#write content to register CTRLA:
# fRef: reference frequency in MHz; range is [10 : 160]
# dataRatio: integer in range [0 : 8] equal to Data Rate/Div_FREF Ratio
# measureDataRate: set to 1 to measure data rate
# lockToRef= 0 > lock to input data; 1 > lock to reference clock
regContent= 0x0
if fRef < 10:
print "fRef must be comprised between 10 and 160. Coherced to 10"
fRef = 10
if fRef > 160:
print "fRef must be comprised between 10 and 160. Coherced to 160"
fRef = 160
fRefRange={
10<= fRef <20 : 0x00,
20<= fRef <40 : 0x01,
40<= fRef <80 : 0x02,
80<= fRef <=160 : 0x03,
}[1]
fRefRange= fRefRange << 6
regContent= regContent | fRefRange
if ((1 <= dataRatio <= 256) & (isinstance(dataRatio, (int, long) )) ):
ratioValue= math.log(dataRatio, 2)
ratioValue= int(ratioValue)
else:
print " dataRatio should be an integer in the form 2^n with 0<= n <= 8. Coherced to 0"
ratioValue= 0
if verbose:
print "\tratioValue=", ratioValue
ratioValue = ratioValue << 2
regContent= regContent | ratioValue
measureDataRate= (measureDataRate & 0x1) << 1
lockToRef= lockToRef & 0x1
regContent= regContent | measureDataRate | lockToRef
self.writeReg( self.regDictionary['ctrla'], regContent, verbose=False)
return
def _writeCTRLB(self, confLOL, rstMisc4, systemReset, rstMisc2, verbose=False):
#write content to register CTRLB:
# confLOL=0 > LOL pin normal operation; 1 > LOL pin is static LOL
# rstMisc4= Write a 1 followed by 0 to reset MISC[4] (staticLOL)
# systemReset= Write 1 followed by 0 to reset ADN2814
# rsttMisc2= Write a 1 followed by 0 to reset MISC[2] (data read measure complete)
regContent= 0x0
confLOL= (confLOL & 0x1) << 7
rstMisc4= (rstMisc4 & 0x1) << 6
systemReset= (systemReset & 0x1) << 5
rstMisc2= (rstMisc2 & 0x1) << 3
regContent= regContent | confLOL | rstMisc4 | systemReset | rstMisc2
self.writeReg( self.regDictionary['ctrlb'], regContent, verbose=False)
return
def _writeCTRLC(self, confLOS, squelch, outBoost, verbose=False):
#write content to register CTRLC:
# confLOS= 0 > active high LOS; 1 > active low LOS
# squelch= 0 > squelch CLK and DATA; 1 > squelch CLK or DATA
# outBoost= 0 > default swing; boost output swing
regContent= 0x0
confLOS= (confLOS & 0x1) << 2
squelch= (squelch & 0x1) << 1
outBoost= (outBoost & 0x1)
regContent= regContent | confLOS | squelch | outBoost
self.writeReg( self.regDictionary['ctrlc'], regContent, verbose=False)
return
projects/TLU_v1e/scripts/packages/ATSHA204A.py 0 → 100644
View file @ 75e77d84
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
import numpy as np
class ATSHA204A:
#Class for Atmel ATSHA204A eeprom
def __init__(self, i2c, slaveaddr= 0x64):
self.i2c = i2c
self.slaveaddr = slaveaddr
#Slot size, in bytes.
self.SLOT_SIZE_BYTES = 32;
#Word size, in bytes. This is the base unit for all reads and writes.
self.WORD_SIZE_BYTES = 4;
#Maximum word offset per slot
self.MAX_WORD_OFFSET = 7;
#Size of the configuration zone, in bytes
self.CONFIGURATION_ZONE_SIZE_BYTES = 88;
#Number of slots in the configuration zone
self.CONFIGURATION_ZONE_SIZE_SLOTS = 3;
#Slot 3 in the configuration zone is only 24 bytes rather than 32, so the max word offset is limited to 5.
self.CONFIGURATION_ZONE_SLOT_2_MAX_WORD_OFFSET = 5;
#Size of the OTP zone, in bytes
self.OTP_ZONE_SIZE_BYTES = 64;
#Number of slots in the OTP zone
self.OTP_ZONE_SIZE_SLOTS = 2;
#Size of the data zone, in bytes
self.DATA_ZONE_SIZE_BYTES = 512;
#Number of slots in the data zone
self.DATA_ZONE_SIZE_SLOTS = 16;
#The data slot used for module configuration data
self.DATA_ZONE_SLOT_MODULE_CONFIGURATION = 0;
#Byte index of the OTP mode byte within its configuration word.
self.OTP_MODE_WORD_BYTE_INDEX = 2;
#-------------------------------------------------------------------------------------------------
# Command packets and I/O
#-------------------------------------------------------------------------------------------------
#Command execution status response block size
self.STATUS_RESPONSE_BLOCK_SIZE_BYTES = 4;
#Byte index of count in response block
self.STATUS_RESPONSE_COUNT_BYTE_INDEX = 0;
#Byte index of status code in response block
self.STATUS_RESPONSE_STATUS_BYTE_INDEX = 1;
#Checksum size
self.CHECKSUM_LENGTH_BYTES = 2;
#Index of the count byte in a command packet
self.COMMAND_PACKET_COUNT_BYTE_INDEX = 0;
#Size of count in a command packet
self.COMMAND_PACKET_COUNT_SIZE_BYTES = 1;
#Index of the opcode byte in a command packet
self.COMMAND_PACKET_OPCODE_BYTE_INDEX = 1;
#Size of the opcode byte in a command packet
self.COMMAND_PACKET_OPCODE_LENGTH_BYTES = 1;
#Index of param 1 in a command packet
self.COMMAND_PACKET_PARAM1_BYTE_INDEX = 2;
#Size of param 1 in a command packet
self.COMMAND_PACKET_PARAM1_SIZE_BYTES = 1;
#Index of param 2 in a command packet
self.COMMAND_PACKET_PARAM2_BYTE_INDEX = 3;
#Size of param 2 in a command packet
self.COMMAND_PACKET_PARAM2_SIZE_BYTES = 2;
def _CalculateCrc(self, pData, dataLengthBytes):
# Calculate a CRC-16 used when communicating with the device. Code taken from Atmel's library.
#The Atmel documentation only specifies that the CRC algorithm used on the ATSHA204A is CRC-16 with polynomial
#0x8005; compared to a standard CRC-16, however, the used algorithm doesn't use remainder reflection.
#@param pData The data to calculate the CRC for
#@param dataLengthBytes The number of bytes to process
#@return The CRC
polynomial = 0x8005
crcRegister = 0
if not pData:
print "_CalculateCrc: No data to process"
return 0
for counter in range(0, dataLengthBytes):
shiftRegister= 0x01
for iShift in range(0, 8):
if (pData[counter] & shiftRegister) :
dataBit= 1
else:
dataBit=0
crcBit= ((crcRegister) >> 15)
crcRegister <<= 1
crcRegister= crcRegister & 0xffff
#print shiftRegister, "\t", dataBit, "\t", crcBit, "\t", crcRegister
shiftRegister= shiftRegister << 1
if (dataBit != crcBit):
#print "poly"
crcRegister ^= polynomial;
return crcRegister
def _wake(self, verifyDeviceIsAtmelAtsha204a, debug):
dummyWriteData = 0x00
mystop=True
self.i2c.write( self.slaveaddr, [dummyWriteData], mystop)
if (verifyDeviceIsAtmelAtsha204a):
expectedStatusBlock= [ 0x04, 0x11, 0x33, 0x43 ];
nwords= 4
res= self.i2c.read( self.slaveaddr, nwords)
if (res != expectedStatusBlock):
print "Attempt to awake Atmel ATSHA204A failed"
print res
def _GetCommandPacketSize(self, additionalDataLengthBytes):
packetSizeBytes = self.COMMAND_PACKET_COUNT_SIZE_BYTES + self.COMMAND_PACKET_OPCODE_LENGTH_BYTES \
+ self.COMMAND_PACKET_PARAM1_SIZE_BYTES + self.COMMAND_PACKET_PARAM2_SIZE_BYTES \
+ additionalDataLengthBytes + self.CHECKSUM_LENGTH_BYTES;
return packetSizeBytes
projects/TLU_v1e/scripts/packages/I2CDISP.py 0 → 100644
View file @ 75e77d84
# -*- coding: utf-8 -*-
import uhal
from I2CuHal2 import I2CCore
import StringIO
import time
class CFA632:
#Class to configure the CFA632 display
def __init__(self, i2c, slaveaddr=0x2A):
self.i2c = i2c
self.slaveaddr = slaveaddr
def test(self):
print "Testing the display"
return
def writeSomething(self, i2ccmd):
mystop= True
print "Write to CFA632"
print "\t", i2ccmd
#myaddr= [int(i2ccmd)]
self.i2c.write( self.slaveaddr, i2ccmd, mystop)
return
class LCD09052:
#Class to configure the LCD09052 display
def __init__(self, i2c, slaveaddr=0x3A):
self.i2c = i2c
self.slaveaddr = slaveaddr
def test(self):
print "\tTesting display (LCD09052)"
self.clear()
self.setBrightness(0)
time.sleep(0.2)
self.setBrightness(250)
time.sleep(0.2)
self.setBrightness(0)
time.sleep(0.2)
self.setBrightness(250)
for ipos in range(1, 18):
self.writeChar(33)
self.posCursor(1, ipos-1)
time.sleep(0.1)
self.writeChar(254)
self.posCursor(2, 1)
for ipos in range(1, 18):
self.writeChar(33)
self.posCursor(2, ipos-1)
time.sleep(0.1)
self.writeChar(254)
return
def clear(self):
### Clears the display and locates the curson on position (1,1), i.e. top left
i2ccmd= [4]
mystop= True
self.i2c.write( self.slaveaddr, i2ccmd, mystop)
def posCursor(self, line, pos):
### Position the cursor on a specific location
## line can be 1 (top) or 2 (bottom)
## pos can be [1, 16}
if ((line==1) or (line==2) and (1 <= pos <= 16)):
i2ccmd= [2, line, pos]
mystop= True
self.i2c.write( self.slaveaddr, i2ccmd, mystop)
else:
print "Cursor line can only be 1 or 2, position must be in range [1, 16]"
def setBrightness(self, value= 250):
### Sets the brightness level of the backlight.
## Value is an integer in range [0, 250]. 0= no light, 250= maximum light.
if value < 0:
print "setBrightness: minimum value= 0. Coherced to 0"
value = 0
if value > 250:
print "setBrightness: maximum value= 250. Coherced to 250"
value = 250
i2ccmd= [7, value]
mystop= True
self.i2c.write( self.slaveaddr, i2ccmd, mystop)
def writeChar(self, value):
### Writes a char in the current cursor position
## The curso is then shifted right one position
## value must be an integer corresponding to the ascii code of the character
i2ccmd= [1, value]
mystop= True
self.i2c.write( self.slaveaddr, i2ccmd, mystop)
def writeSomething(self, i2ccmd):
mystop= True
print "Write to LCD09052"
print "\t", i2ccmd
#myaddr= [int(i2ccmd)]
self.i2c.write( self.slaveaddr, i2ccmd, mystop)
return
projects/TLU_v1e/scripts/packages/I2CuHal.py
View file @ 75e77d84
......@@ -77,8 +77,8 @@ class I2CCore:
self.target.dispatch()
#Write pre-scale register
#prescale = int(self.wishboneclock / (5.0 * self.i2cclock)) - 1
#prescale = int(self.wishboneclock / (5.0 * self.i2cclock))
prescale = 0x0100 #FOR NOW HARDWIRED, TO BE MODIFIED
#prescale = 0x2710 #FOR NOW HARDWIRED, TO BE MODIFIED
self.prescale_low.write(prescale & 0xff)
self.prescale_high.write((prescale & 0xff00) >> 8)
#Enable core
......
projects/TLU_v1e/scripts/packages/I2CuHal2.py 0 → 100644
View file @ 75e77d84
# -*- coding: utf-8 -*-
"""
"""
import time
import uhal
verbose = True
################################################################################
# /*
# I2C CORE
# */
################################################################################
### Same as the class defined in I2CuHal.py but the register names are changed to
### comply with D. Newbold's notation. To be used in the Dune SFP Fanout (pc059a)
class I2CCore:
"""I2C communication block."""
# Define bits in cmd_stat register
startcmd = 0x1 << 7
stopcmd = 0x1 << 6
readcmd = 0x1 << 5
writecmd = 0x1 << 4
ack = 0x1 << 3
intack = 0x1
recvdack = 0x1 << 7
busy = 0x1 << 6
arblost = 0x1 << 5
inprogress = 0x1 << 1
interrupt = 0x1
def __init__(self, target, wclk, i2cclk, name="i2c", delay=None):
self.target = target
self.name = name
self.delay = delay
self.prescale_low = self.target.getNode("%s.ps_lo" % name)
self.prescale_high = self.target.getNode("%s.ps_hi" % name)
self.ctrl = self.target.getNode("%s.ctrl" % name)
self.data = self.target.getNode("%s.data" % name)
self.cmd_stat = self.target.getNode("%s.cmd_stat" % name)
self.wishboneclock = wclk
self.i2cclock = i2cclk
self.config()
def state(self):
status = {}
status["ps_low"] = self.prescale_low.read()
status["ps_hi"] = self.prescale_high.read()
status["ctrl"] = self.ctrl.read()
status["data"] = self.data.read()
status["cmd_stat"] = self.cmd_stat.read()
self.target.dispatch()
status["prescale"] = status["ps_hi"] << 8
status["prescale"] |= status["ps_low"]
for reg in status:
val = status[reg]
bval = bin(int(val))
if verbose:
print "\treg %s = %d, 0x%x, %s" % (reg, val, val, bval)
def clearint(self):
self.ctrl.write(0x1)
self.target.dispatch()
def config(self):
#INITIALIZATION OF THE I2S MASTER CORE
#Disable core
self.ctrl.write(0x0 << 7)
self.target.dispatch()
#Write pre-scale register
#prescale = int(self.wishboneclock / (5.0 * self.i2cclock)) - 1
#prescale = int(self.wishboneclock / (5.0 * self.i2cclock))
prescale = 0x0100 #FOR NOW HARDWIRED, TO BE MODIFIED
self.prescale_low.write(prescale & 0xff)
self.prescale_high.write((prescale & 0xff00) >> 8)
#Enable core
self.ctrl.write(0x1 << 7)
self.target.dispatch()
def checkack(self):
inprogress = True
ack = False
while inprogress:
cmd_stat = self.cmd_stat.read()
self.target.dispatch()
inprogress = (cmd_stat & I2CCore.inprogress) > 0
ack = (cmd_stat & I2CCore.recvdack) == 0
return ack
def delayorcheckack(self):
ack = True
if self.delay is None:
ack = self.checkack()
else:
time.sleep(self.delay)
ack = self.checkack()#Remove this?
return ack
################################################################################
# /*
# I2C WRITE
# */
################################################################################
def write(self, addr, data, stop=True):
"""Write data to the device with the given address."""
# Start transfer with 7 bit address and write bit (0)
nwritten = -1
addr &= 0x7f
addr = addr << 1
startcmd = 0x1 << 7
stopcmd = 0x1 << 6
writecmd = 0x1 << 4
#Set transmit register (write operation, LSB=0)
self.data.write(addr)
#Set Command Register to 0x90 (write, start)
self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
self.target.dispatch()
ack = self.delayorcheckack()
if not ack:
self.cmd_stat.write(I2CCore.stopcmd)
self.target.dispatch()
print "no ack from I2C address", hex(addr>>1)
return nwritten
nwritten += 1
for val in data:
val &= 0xff
#Write slave memory address
self.data.write(val)
#Set Command Register to 0x10 (write)
self.cmd_stat.write(I2CCore.writecmd)
self.target.dispatch()
ack = self.delayorcheckack()
if not ack:
self.cmd_stat.write(I2CCore.stopcmd)
self.target.dispatch()
return nwritten
nwritten += 1
if stop:
self.cmd_stat.write(I2CCore.stopcmd)
self.target.dispatch()
return nwritten
################################################################################
# /*
# I2C READ
# */
################################################################################
def read(self, addr, n):
"""Read n bytes of data from the device with the given address."""
# Start transfer with 7 bit address and read bit (1)
data = []
addr &= 0x7f
addr = addr << 1
addr |= 0x1 # read bit
self.data.write(addr)
self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
self.target.dispatch()
ack = self.delayorcheckack()
if not ack:
self.cmd_stat.write(I2CCore.stopcmd)
self.target.dispatch()
return data
for i in range(n):
if i < (n-1):
self.cmd_stat.write(I2CCore.readcmd) # <---
else:
self.cmd_stat.write(I2CCore.readcmd | I2CCore.ack | I2CCore.stopcmd) # <--- This tells the slave that it is the last word
self.target.dispatch()
ack = self.delayorcheckack()
val = self.data.read()
self.target.dispatch()
data.append(val & 0xff)
#self.cmd_stat.write(I2CCore.stopcmd)
#self.target.dispatch()
return data
################################################################################
# /*
# I2C WRITE-READ
# */
################################################################################
# def writeread(self, addr, data, n):
# """Write data to device, then read n bytes back from it."""
# nwritten = self.write(addr, data, stop=False)
# readdata = []
# if nwritten == len(data):
# readdata = self.read(addr, n)
# return nwritten, readdata
"""
SPI core XML:
<node description="SPI master controller" fwinfo="endpoint;width=3">
<node id="d0" address="0x0" description="Data reg 0"/>
<node id="d1" address="0x1" description="Data reg 1"/>
<node id="d2" address="0x2" description="Data reg 2"/>
<node id="d3" address="0x3" description="Data reg 3"/>
<node id="ctrl" address="0x4" description="Control reg"/>
<node id="divider" address="0x5" description="Clock divider reg"/>
<node id="ss" address="0x6" description="Slave select reg"/>
</node>
"""
class SPICore:
go_busy = 0x1 << 8
rising = 1
falling = 0
def __init__(self, target, wclk, spiclk, basename="io.spi"):
self.target = target
# Only a single data register is required since all transfers are
# 16 bit long
self.data = target.getNode("%s.d0" % basename)
self.control = target.getNode("%s.ctrl" % basename)
self.control_val = 0b0
self.divider = target.getNode("%s.divider" % basename)
self.slaveselect = target.getNode("%s.ss" % basename)
self.divider_val = int(wclk / spiclk / 2.0 - 1.0)
self.divider_val = 0x7f
self.configured = False
def config(self):
"Configure SPI interace for communicating with ADCs."
self.divider_val = int(self.divider_val) % 0xffff
if verbose:
print "Configuring SPI core, divider = 0x%x" % self.divider_val
self.divider.write(self.divider_val)
self.target.dispatch()
self.control_val = 0x0
self.control_val |= 0x0 << 13 # Automatic slave select
self.control_val |= 0x0 << 12 # No interrupt
self.control_val |= 0x0 << 11 # MSB first
# ADC samples data on rising edge of SCK
self.control_val |= 0x1 << 10 # change ouput on falling edge of SCK
# ADC changes output shortly after falling edge of SCK
self.control_val |= 0x0 << 9 # read input on rising edge
self.control_val |= 0x10 # 16 bit transfers
if verbose:
print "SPI control val = 0x%x = %s" % (self.control_val, bin(self.control_val))
self.configured = True
def transmit(self, chip, value):
if not self.configured:
self.config()
assert chip >= 0 and chip < 8
value &= 0xffff
self.data.write(value)
checkdata = self.data.read()
self.target.dispatch()
assert checkdata == value
self.control.write(self.control_val)
self.slaveselect.write(0xff ^ (0x1 << chip))
self.target.dispatch()
self.control.write(self.control_val | SPICore.go_busy)
self.target.dispatch()
busy = True
while busy:
status = self.control.read()
self.target.dispatch()
busy = status & SPICore.go_busy > 0
self.slaveselect.write(0xff)
data = self.data.read()
ss = self.slaveselect.read()
status = self.control.read()
self.target.dispatch()
#print "Received data: 0x%x, status = 0x%x, ss = 0x%x" % (data, status, ss)
return data
projects/TLU_v1e/scripts/packages/NHDC0220Biz.py 0 → 100644
View file @ 75e77d84
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
class NHDC0220Biz:
#Class to configure the EEPROM
def __init__(self, i2c, slaveaddr=0x3c):
self.i2c = i2c
self.slaveaddr = 0x2a#slaveaddr
def test(self):
print "Testing the display"
return
def writeSomething(self):
mystop= True
print "Write random stuff"
myaddr= [0x08, 0x38]
self.i2c.write( self.slaveaddr, myaddr, mystop)
return
projects/TLU_v1e/scripts/packages/PCA9548ADW.py 0 → 100644
View file @ 75e77d84
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
class PCA9548ADW:
#Class to configure the I2C multiplexer
def __init__(self, i2c, slaveaddr=0x74):
self.i2c = i2c
self.slaveaddr = slaveaddr
def disableAllChannels(self, verbose=False):
#Disable all channels so that none of the MUX outputs is visible
# to the upstream I2C bus
mystop=True
cmd= [0x0]
self.i2c.write( self.slaveaddr, cmd, mystop)
def getChannelStatus(self, verbose=False):
#Basic functionality to read the status of the control register and determine
# which channel is currently enabled.
mystop=False
cmd= []
self.i2c.write( self.slaveaddr, cmd, mystop)
res= self.i2c.read( self.slaveaddr, 1)
return res[0]
def setActiveChannel(self, channel, verbose=False):
#Basic functionality to activate one channel
# In principle multiple channels can be active at the same time (see
# function "setMultipleChannels")
if (channel < 0) | (channel > 7):
print "PCA9539PW - ERROR: channel number should be in range [0:7]"
return
mystop=True
cmd= [0x1 << channel]
#print "\tChannel is ", channel, "we write ", cmd
self.i2c.write( self.slaveaddr, cmd, mystop)
def setMultipleChannels(self, channels, verbose=False):
#Basic functionality to activate multiple channels
# channels is a byte: each bit set to one will set the corresponding channels
# as active. The slave connected to that channel will be visible on the I2C bus.
# NOTE: this can lead to address clashes!
channels = channels & 0xFF
mystop=True
cmd= [channels]
#print "\tChannel is ", channel, "we write ", cmd
self.i2c.write( self.slaveaddr, cmd, mystop)
projects/TLU_v1e/scripts/packages/SFPI2C.py 0 → 100644
View file @ 75e77d84
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
class SFPI2C:
#Class to configure the EEPROM
def __init__(self, i2c, slaveaddr=0x50):
self.i2c = i2c
self.slaveaddr = slaveaddr
"""def readEEPROM(self, startadd, nBytes):
#Read EEPROM memory locations
mystop= False
myaddr= [startadd]#0xfa
self.i2c.write( self.slaveaddr, [startadd], mystop)
res= self.i2c.read( self.slaveaddr, nBytes)
return res"""
def _listToString(self, mylist):
mystring= ""
for iChar in mylist:
mystring= mystring + str(unichr(iChar))
return mystring
def writeReg(self, regN, regContent, verbose=False):
#Basic functionality to write to register.
if (regN < 0) | (regN > 7):
print "PCA9539PW - ERROR: register number should be in range [0:7]"
return
regContent= regContent & 0xFF
mystop=True
cmd= [regN, regContent]
self.i2c.write( self.slaveaddr, cmd, mystop)
def readReg(self, regN, nwords, verbose=False):
#Basic functionality to read from register.
mystop=False
self.i2c.write( self.slaveaddr, [regN], mystop)
res= self.i2c.read( self.slaveaddr, nwords)
return res
def getConnector(self):
"""Code for connector type (table 3.4)"""
conntype= self.readReg(2, 1, False)[0]
print "Connector type:", hex(conntype)
return conntype
def getDiagnosticsType(self):
"""Types of diagnostics available (table 3.9)"""
diaType= self.readReg(92, 1, False)[0]
print "Available Diagnostics:", hex(diaType)
return diaType
def getEncoding(self):
encoding= self.readReg(11, 1, False)[0]
print "Encoding", encoding
return encoding
def getEnhancedOpt(self):
enOpt= self.readReg(93, 1, False)[0]
print "Enhanced Options:", enOpt
return enOpt
def getTransceiver(self):
res= self.readReg(3, 8, False)
return res
def getVendorId(self):
""" Returns the OUI vendor id"""
vendID= self.readReg(37, 3, False)
return vendID
def getVendorName(self):
res= self.readReg( 20 , 16, False)
mystring= self._listToString(res)
return mystring
def getVendorPN(self):
""" Returns the part number defined by the vendor"""
pn=[]
mystring= ""
res= self.readReg( 40 , 16, False)
mystring= self._listToString(res)
return mystring
def scanI2C(self):
mystop=True
for iAddr in range (0, 128):
self.i2c.write( iAddr, [], mystop)
projects/TLU_v1e/scripts/packages/TLU_powermodule.py 0 → 100644
View file @ 75e77d84
This diff is collapsed.
projects/TLU_v1e/scripts/packages/si5345.py
View file @ 75e77d84
......@@ -3,6 +3,7 @@ import uhal
from I2CuHal import I2CCore
import StringIO
import csv
import sys
class si5345:
#Class to configure the Si5344 clock generator
......@@ -87,7 +88,7 @@ class si5345:
self.i2c.write( self.slaveaddr, myaddr, mystop)
#time.sleep(0.1)
res= self.i2c.read( self.slaveaddr, nwords)
print " Si5345 EPROM: "
print " Si5345 EEPROM: "
result="\t"
for iaddr in reversed(res):
result+="%#02x "%(iaddr)
......@@ -119,17 +120,28 @@ class si5345:
print "\t ", len(regSettingList), "elements"
return regSettingList
def writeConfiguration(self, regSettingList):
def writeConfiguration(self, regSettingList, verbose= 0):
print " Si5345 Writing configuration:"
toolbar_width = 38
if (verbose==1):
sys.stdout.write(" [%s]" % (" " * toolbar_width))
sys.stdout.flush()
sys.stdout.write("\b" * (toolbar_width+1)) # return to start of line, after '['
#regSettingList= list(regSettingCsv)
counter=0
for item in regSettingList:
regAddr= int(item[0], 16)
regData=[0]
regData[0]= int(item[1], 16)
print "\t", counter, "Reg:", hex(regAddr), "Data:", regData
if (verbose > 1):
print "\t", counter, "Reg:", hex(regAddr), "Data:", regData
counter += 1
self.writeRegister(regAddr, regData, False)
if (not(counter % 10) and (verbose==1)):
sys.stdout.write("-")
sys.stdout.flush()
sys.stdout.write("\n")
print "\tSi5345 configuration done"
def checkDesignID(self):
regAddr= 0x026B
......
projects/TLU_v1e/scripts/startTLU_v1e.py
View file @ 75e77d84
......@@ -83,8 +83,8 @@ class MyPrompt(cmd.Cmd):
else:
runN= arglist[0]
# logdata= True
logdata= False
logdata= True
# logdata= False
#TLU.start(logdata)
if (TLU.isRunning): #Prevent double start
......
projects/TLU_v1e/scripts/startTLU_v1e.sh
View file @ 75e77d84
......@@ -8,7 +8,8 @@ echo "============"
echo "SETTING PATHS"
#export PYTHONPATH=$CURRENT_DIR/../../../../../Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
#export PYTHONPATH=~/Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
export PYTHONPATH=../../packages:$PYTHONPATH
#export PYTHONPATH=../../packages:$PYTHONPATH
export PYTHONPATH=./packages:$PYTHONPATH
echo "PYTHON PATH= " $PYTHONPATH
export LD_LIBRARY_PATH=/opt/cactus/lib:$LD_LIBRARY_PATH
echo "LD_LIBRARY_PATH= " $LD_LIBRARY_PATH
......
projects/TLU_v1e/scripts/startTLU_v1e_merged.py 0 → 100644
View file @ 75e77d84
# -*- coding: utf-8 -*-
# miniTLU test script
#from PyChipsUser import *
#from FmcTluI2c import *
import uhal
import sys
import time
from datetime import datetime
import threading
# from ROOT import TFile, TTree
# from ROOT import gROOT
from datetime import datetime
from TLU_v1e import TLU
# Use to have interactive shell
import cmd
# Use to have config file parser
import ConfigParser
# Use root
from ROOT import TFile, TTree, gROOT, AddressOf
from ROOT import *
import numpy as numpy
## Define class that creates the command user inteface
class MyPrompt(cmd.Cmd):
# def do_initialise(self, args):
# """Processes the INI file and writes its values to the TLU. To use a specific file type:\n
# parseIni path/to/filename.ini\n
# (without quotation marks)"""
# print "COMMAND RECEIVED: PARSE INI"
# parsed_cfg= self.open_cfg_file(args, "/users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/scripts/localIni.ini")
# try:
# theID = parsed_cfg.getint("Producer.fmctlu", "initid")
# print theID
# theSTRING= parsed_cfg.get("Producer.fmctlu", "ConnectionFile")
# print theSTRING
# #TLU= TLU("tlu", theSTRING, parsed_cfg)
# except IOError:
# print "\t Could not retrieve INI data."
# return
def do_configure(self, args):
"""Processes the CONF file and writes its values to the TLU. To use a specific file type:\n
parseIni path/to/filename.conf\n
(without quotation marks)"""
print "==== COMMAND RECEIVED: PARSE CONFIG"
#self.testme()
parsed_cfg= self.open_cfg_file(args, "./localConf.conf")
try:
theID = parsed_cfg.getint("Producer.fmctlu", "confid")
print "\t", theID
TLU.configure(parsed_cfg)
except IOError:
print "\t Could not retrieve CONF data."
return
def do_i2c(self, args):
arglist = args.split()
if len(arglist) == 0:
print "\tno command specified"
else:
i2ccmd= arglist[0]
results = list(map(int, arglist))
TLU.DISP.writeSomething(results)
print "Sending i2c command to display"
return
def do_id(self, args):
"""Interrogates the TLU and prints it unique ID on screen"""
TLU.getSN()
return
def do_triggers(self, args):
"""Interrogates the TLU and prints the number of triggers seen by the input discriminators"""
TLU.getChStatus()
TLU.getAllChannelsCounts()
TLU.getPostVetoTrg()
return
def do_startRun(self, args):
"""Starts the TLU run. If a number is specified, this number will be appended to the file name as Run_#"""
print "==== COMMAND RECEIVED: STARTING TLU RUN"
#startTLU( uhalDevice = self.hw, pychipsBoard = self.board, writeTimestamps = ( options.writeTimestamps == "True" ) )
arglist = args.split()
if len(arglist) == 0:
print "\tno run# specified, using 1"
runN= 1
else:
runN= arglist[0]
logdata= True
#TLU.start(logdata)
if (TLU.isRunning): #Prevent double start
print " Run already in progress"
return
else:
now = datetime.now().strftime('%Y%m%d_%H%M%S')
default_filename = "./datafiles/"+ now + "_tluData_" + str(runN) + ".root"
rootFname= default_filename
print "OPENING ROOT FILE:", rootFname
self.root_file = TFile( rootFname, 'RECREATE' )
# Create a root "tree"
root_tree = TTree( 'T', 'TLU Data' )
#highWord =0
#lowWord =0
#evtNumber=0
#timeStamp=0
#evtType=0
#trigsFired=0
#bufPos = 0
#https://root-forum.cern.ch/t/long-integer/1961/2
gROOT.ProcessLine(
"struct MyStruct {\
UInt_t raw0;\
UInt_t raw1;\
UInt_t raw2;\
UInt_t raw3;\
UInt_t raw4;\
UInt_t raw5;\
UInt_t evtNumber;\
ULong64_t tluTimeStamp;\
UChar_t tluEvtType;\
UChar_t tluTrigFired;\
};" );
mystruct= MyStruct()
# Create a branch for each piece of data
root_tree.Branch('EVENTS', mystruct, 'raw0/i:raw1/i:raw2/i:raw3/i:raw4/i:raw5/i:evtNumber/i:tluTimeStamp/l:tluEvtType/b:tluTrigFired/b' )
# root_tree.Branch( 'tluHighWord' , highWord , "HighWord/l")
# root_tree.Branch( 'tluLowWord' , lowWord , "LowWord/l")
# root_tree.Branch( 'tluExtWord' , extWord , "ExtWord/l")
# root_tree.Branch( 'tluTimeStamp' , timeStamp , "TimeStamp/l")
# root_tree.Branch( 'tluBufPos' , bufPos , "Bufpos/s")
# root_tree.Branch( 'tluEvtNumber' , evtNumber , "EvtNumber/i")
# root_tree.Branch( 'tluEvtType' , evtType , "EvtType/b")
# root_tree.Branch( 'tluTrigFired' , trigsFired, "TrigsFired/b")
#self.root_file.Write()
daq_thread= threading.Thread(target = TLU.start, args=(logdata, runN, mystruct, root_tree))
daq_thread.start()
def do_endRun(self, args):
"""Stops the TLU run"""
print "==== COMMAND RECEIVED: STOP TLU RUN"
if TLU.isRunning:
TLU.isRunning= False
TLU.stop(False, False)
self.root_file.Write()
self.root_file.Close()
else:
print " No run to stop"
def do_quit(self, args):
"""Quits the program."""
print "==== COMMAND RECEIVED: QUITTING TLU CONSOLE"
if TLU.isRunning:
TLU.isRunning= False
TLU.stop(False, False)
self.root_file.Write()
self.root_file.Close()
print "Terminating run"
return True
def testme(self):
print "This is a test"
def open_cfg_file(self, args, default_file):
# Parse the user arguments, attempts to opent the file and performs a (minimal)
# check to verify the file exists (but not that its content is correct)
arglist = args.split()
if len(arglist) == 0:
print "\tno file specified, using default"
fileName= default_file
print "\t", fileName
else:
fileName= arglist[0]
if len(arglist) > 1:
print "\tinvalid: too many arguments. Max 1."
return
parsed_file = ConfigParser.RawConfigParser()
try:
with open(fileName) as f:
parsed_file.readfp(f)
print "\t", parsed_file.sections()
except IOError:
print "\t Error while parsing the specified file."
return
return parsed_file
# # Override methods in Cmd object ##
# def preloop(self):
# """Initialization before prompting user for commands.
# Despite the claims in the Cmd documentaion, Cmd.preloop() is not a stub.
# """
# cmd.Cmd.preloop(self) # # sets up command completion
# self._hist = [] # # No history yet
# self._locals = {} # # Initialize execution namespace for user
# self._globals = {}
# print "\nINITIALIZING"
# now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
# default_filename = './rootfiles/tluData_' + now + '.root'
# print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
# self.manager = uhal.ConnectionManager("file://./connection.xml")
# self.hw = self.manager.getDevice("minitlu")
# self.device_id = self.hw.id()
#
# # Point to TLU in Pychips
# self.bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
#
# # Assume DIP-switch controlled address. Switches at 2
# self.board = ChipsBusUdp(self.bAddrTab,"192.168.200.32",50001)
#################################################
if __name__ == "__main__":
print "TLU v1E MAIN"
prompt = MyPrompt()
prompt.prompt = '>> '
parsed_ini= prompt.open_cfg_file("", "./localIni.ini")
TLU= TLU("tlu", "file://./TLUconnection.xml", parsed_ini)
###TLU.configure(parsed_cfg)
###logdata= True
###TLU.start(logdata)
###time.sleep(5)
###TLU.stop(False, False)
# Start interactive prompt
print "===================================================================="
print "==========================TLU TEST CONSOLE=========================="
print "===================================================================="
prompt.cmdloop("Type 'help' for a list of commands.")
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