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AIDA-2020 TLU
Commit 881ea109 authored by Alvaro Dosil's avatar Alvaro Dosil
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bidirectional clk ports to/from DUT

parent e957e57c
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Showing with 27 additions and 38 deletions
firmware/hdl/common/DUTInterfaces_rtl.vhd
View file @ 881ea109
......@@ -66,9 +66,9 @@ ENTITY DUTInterfaces IS
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
ipbus_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic; -- ! goes high every 4th clock cycle
--trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
--trigger_number_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_i : IN std_logic; -- goes high when trigger logic issues a trigger
clk_to_dut_i : IN std_logic ; -- ! clock to DUT
clk_to_dut_i : IN std_logic ; -- ! clock to DUT
reset_or_clk_to_dut_i : IN std_logic;
AIDAhandshake_i : IN std_logic; -- AIDA/EUDET handshake
ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
......@@ -93,8 +93,9 @@ ARCHITECTURE rtl OF DUTInterfaces IS
signal s_strobe_4x_logic_d1 : std_logic;
signal s_clk_to_DUT , s_busy_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0);
signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs not used
signal s_clk_is_input, s_clk_is_input_b : std_logic := '0'; --! Indicates the direction of the clock in the RJ45 DUT
signal s_clk_to_tlu : std_logic := '0';
signal s_clk_is_input : std_logic := '0'; --! Indicates the direction of the clock in the RJ45 DUT
signal s_clk_is_input_b : std_logic_vector(g_NUM_DUTS-1 downto 0);
signal s_clk_to_tlu : std_logic_vector(g_NUM_DUTS-1 downto 0);
constant c_N_CTRL : positive := 1;
constant c_N_STAT : positive := 1;
......@@ -105,7 +106,6 @@ BEGIN
-- Dummy code.
s_intermediate_busy_or(0) <= '0';
--s_busy_from_dut(g_NUM_DUTS-1 downto 0) <= (others=>'0');
-----------------------------------------------------------------------------
-- IPBus interface
......@@ -152,37 +152,17 @@ BEGIN
s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
-- These instances need to be out of the loop because the RJ45 permits a bidirectional clock
clk_to_DUT_OBUFDS_inst_0 : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => clk_to_dut_p_o(0), -- Diff_p output (connect directly to top-level port)
OB => clk_to_dut_n_o(0), -- Diff_n output (connect directly to top-level port)
I => s_clk_to_dut(0) -- Buffer output
);
clk_to_DUT_OBUFDS_inst_1 : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => clk_to_dut_p_o(1), -- Diff_p output (connect directly to top-level port)
OB => clk_to_dut_n_o(1), -- Diff_n output (connect directly to top-level port)
I => s_clk_to_dut(1) -- Buffer output
);
clk_to_DUT_OBUFDS_inst_2 : IOBUFDS
generic map (
IOSTANDARD => "BLVDS_25")
port map (
O => s_clk_to_tlu, -- Buffer output
IO => clk_to_dut_p_o(2), -- Diff_p inout (connect directly to top-level port)
IOB => clk_to_dut_n_o(2), -- Diff_n inout (connect directly to top-level port)
I => s_clk_to_dut(2), -- Buffer input
T => s_clk_is_input_b -- 3-state enable input, high=input, low=output
);
-----------------------------------------------------------------------------
-- Signals to/from DUT
-----------------------------------------------------------------------------
s_clk_is_input <= not AIDAhandshake_i;
--When an ODDR2 primitive is used in conjunction with a 3-state output, the T control pin must
duts: for dut in 1 to g_NUM_DUTS generate
--When an ODDR2 primitive is used in conjunction with a 3-state output, the T control pin must
--also use an ODDR2 primitive configured in the same mode as the ODDR2 primitive used for data
--output.
ddr_for_clk_to_DUT_tristate : ODDR2
......@@ -191,7 +171,7 @@ BEGIN
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => s_clk_is_input_b, -- 1-bit output data
Q => s_clk_is_input_b(dut-1), -- 1-bit output data
C0 => clk_to_dut_i, -- 1-bit clock input
C1 => not clk_to_dut_i, --not s_clk160_internal, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
......@@ -200,8 +180,17 @@ BEGIN
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
duts: for dut in 1 to g_NUM_DUTS generate
clk_to_DUT_OBUFDS_inst : IOBUFDS
generic map (
IOSTANDARD => "BLVDS_25")
port map (
O => s_clk_to_tlu(dut-1), -- Buffer output
IO => clk_to_dut_p_o(dut-1), -- Diff_p inout (connect directly to top-level port)
IOB => clk_to_dut_n_o(dut-1), -- Diff_n inout (connect directly to top-level port)
I => s_clk_to_dut(dut-1), -- Buffer input
T => s_clk_is_input_b(dut-1) -- 3-state enable input, high=input, low=output
);
busy_IBUFDS_inst : IBUFDS
generic map (
......
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
View file @ 881ea109
......@@ -433,9 +433,9 @@ BEGIN
ipbus_i => ipbw(0),
ipbus_reset_i => ipbus_reset,
strobe_4x_logic_i => strobe_4x_logic,
--trigger_counter_i => trigger_count,
--trigger_number_i => --trigger_count,
clk_to_dut_i => s_DUT_clk,
trigger_i => s_Trig_TO_DUT, --overall_trigger,
trigger_i => s_Trig_TO_DUT,
reset_or_clk_to_dut_i => s_rst_or_clk_to_dut,
AIDAhandshake_i => s_AIDAhandshake, -- RJ45 DUT clock as output/input (1/0)
ipbus_o => ipbr(0),
......
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