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AIDA-2020 TLU
Commit 9de93149 authored by David Cussans's avatar David Cussans
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Checking in changes after debugging

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firmware/config/ise14/sp605/build_bitstream.tcl
View file @ 9de93149
project open fmc-mtlu
puts "Regenerating cores"
cd $::env(FW_WORKSPACE)/workspace/ipcore_dir
catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
##puts "Regenerating cores"
##cd $::env(FW_WORKSPACE)/workspace/ipcore_dir
##catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
##catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
# catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
##catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
##catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
### catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
##catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
process run "Synthesize"
......
firmware/config/ise14/sp605/setup_project.tcl
View file @ 9de93149
......@@ -129,13 +129,14 @@ xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
# xfile add fmc-mtlu/firmware/hdl/common/TPx3Logic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/TPx3Logic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/GPP_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
xfile add fmc-mtlu/firmware/hdl/common/coincidenceLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/stretchPulse_rtl.vhd
# Then add the HDL-Designer generated files..
#xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
......
firmware/hdl/common/DUTInterfaces_rtl.vhd
View file @ 9de93149
......@@ -9,8 +9,7 @@
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
--
--! @brief \n
--! \n
--! @brief Interfaces to Device Under Test (DUT) connectors.
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
......@@ -19,14 +18,13 @@
--! @version v0.1
--
--! @details
--! Address map:\n
--! 5-bit decoded
--! 0x00000001 - DUT mask(write). 1 = active , 0 = inactive. Inactive DUT don't contribute to BUSY. \n
--! Up to 12 inputs. One bit per DUT XXXXXXXXXXXXXXXXXXXXXXBA9876543210\n
--! 0x0000000
--! 0x00000000 - DUT interface mode, two bits per DUT. Up to 12 inputs XXXXXXXXBBAA99887766554433221100\n
--! mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved\n
--! 0x00000002 - DUT mask ( read )
--! IPBUS Address map:
--! - 0x00000000 - DUT mask(write). 1 = active , 0 = inactive. Inactive DUT don't contribute to BUSY. One bit per DUT XXXXXXXXXXXXXXXXXXXXXXBA9876543210
--! - 0x00000001 - Ignore DUT busy. 1 = ignore BUSY from this connector
--! - 0x00000002 - Ignore shutter veto. 0 = raising shutter vetos triggers.
--! - 0x00000003 - DUT interface mode, two bits per DUT. Up to 12 inputs
--XXXXXXXXBBAA99887766554433221100 mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
--! - 0x00000004 - DUT mask ( read )
--!
--! DUT(0) = RJ45 ( J3 )
--! DUT(1) = HDMI ( J1 ) , furthest from RJ45
......@@ -69,7 +67,8 @@ ENTITY DUTInterfaces IS
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_i : IN std_logic; -- goes high when trigger logic issues a trigger
-- clk_to_dut_i : IN std_logic; --! clock to DUT
reset_or_clk_to_dut_i : IN std_logic;
reset_or_clk_to_dut_i : IN std_logic; --! For interface to TPix3 telescope this is the T0 sync signal
shutter_to_dut_i : IN std_logic; --! For interface to TPix3 telescope this shutter
-- IPBus signals.
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
......@@ -84,12 +83,14 @@ ENTITY DUTInterfaces IS
reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Either reset line or trigger
trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger output
trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger output
shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 1); --! Shutter output. Output 0 (RJ45) has no shutter signal
shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 1); --! Shutter output
veto_o : OUT std_logic --! goes high when one or more DUT are busy
);
-- Declarations
END DUTInterfaces ;
END ENTITY DUTInterfaces ;
--
ARCHITECTURE rtl OF DUTInterfaces IS
......@@ -100,10 +101,12 @@ ARCHITECTURE rtl OF DUTInterfaces IS
signal s_clk_to_DUT , s_busy_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0);
signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs used. 1 = active
signal s_DUT_ignore_busy : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! set bit to 1 for BUSY to be ignored.
signal s_IgnoreShutterVeto : std_logic := '0'; -- --! When high the shutter won't veto triggers when low.
signal s_clk_to_tlu : std_logic := '0';
constant c_N_CTRL : positive := 2;
constant c_N_STAT : positive := 2;
constant c_N_CTRL : positive := 4;
constant c_N_STAT : positive := 4;
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
signal s_dut_clk : std_logic := '0'; -- ! internal clock that gets copied to DUT outputs
......@@ -118,7 +121,7 @@ BEGIN
-- Dummy code.
s_intermediate_busy_or(0) <= '0';
--s_busy_from_dut(g_NUM_DUTS-1 downto 0) <= (others=>'0');
-----------------------------------------------------------------------------
......@@ -162,15 +165,18 @@ BEGIN
-- Map the control registers
s_DUT_mask <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
s_DUT_ignore_busy <= s_sync_control_from_ipbus(1)(g_NUM_DUTS-1 downto 0);
s_IgnoreShutterVeto <= s_sync_control_from_ipbus(2)(0);
-- Map the status registers
s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
s_status_to_ipbus(1) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_ignore_busy;
s_status_to_ipbus(2) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-1)) & s_IgnoreShutterVeto;
s_intermediate_busy_or(0) <= '0';
duts: for dut in 1 to g_NUM_DUTS generate
-- This is a bodge - RJ45 needs to have a bi-directional clock.
clk_to_DUT_OBUFDS_inst_0 : OBUFDS
-- This is a bodge - Eventually RJ45 needs to have a bi-directional clock....
clk_to_DUT_OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
......@@ -208,6 +214,7 @@ BEGIN
OB => reset_or_clk_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
I => reset_or_clk_to_dut_i --s_reset_or_clk_to_dut(dut-1) and s_DUT_mask(dut-1) -- Buffer input
);
s_intermediate_busy_or(dut) <= s_intermediate_busy_or(dut-1) or
(s_busy_from_dut(dut-1)
......@@ -234,6 +241,16 @@ BEGIN
end generate duts;
-- BODGE BODGE BODGE. Hard wire only one DUT with shutter.
shutter_OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => shutter_to_dut_p_o(1), -- Diff_p output (connect directly to top-level port)
OB => shutter_to_dut_n_o(1), -- Diff_n output (connect directly to top-level port)
I => shutter_to_dut_i
);
-- purpose: generates a clock from 4x clock and strobe ( high once every 4 cycles )
-- should produce 11001100... etc. ie. 40MHz clock from 160MHz clock
-- type : combinational
......@@ -294,15 +311,21 @@ BEGIN
register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
begin -- process register_signals
if rising_edge(clk_4x_logic_i) then
veto_o <= s_veto;
s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
--s_reset_or_clk_to_dut <= ( others => (s_strobe_4x_logic_d1 or strobe_4x_logic_i));
--s_trigger_to_dut <= ( others => trigger_i );
--shutter_to_dut <= ( others => shutter_i );
--! Copy clock to array of clocks.
s_clk_to_dut <= ( others => s_dut_clk );
-- hardwire to shutter for now
veto_o <= ((not s_IgnoreShutterVeto ) and (not shutter_to_dut_i)) or s_veto;
end if;
end process register_signals;
END ARCHITECTURE rtl;
firmware/hdl/common/IPBusInterface_rtl.vhd
View file @ 9de93149
......@@ -46,7 +46,8 @@ USE work.ipbus.all;
ENTITY IPBusInterface IS
GENERIC(
NUM_EXT_SLAVES : positive := 5
NUM_EXT_SLAVES : positive := 5;
BUILD_SIMULATED_ETHERNET : integer := 0 --! Set to 1 to build simulated Ethernet interface using Modelsim FLI
);
PORT(
gmii_rx_clk_i : IN std_logic;
......@@ -80,7 +81,7 @@ ARCHITECTURE rtl OF IPBusInterface IS
--! Number of slaves inside the IPBusInterface block.
constant c_NUM_INTERNAL_SLAVES : positive := 1;
signal clk125, locked, rst_125, rst_ipb: STD_LOGIC;
signal clk125, rst_125, rst_ipb: STD_LOGIC;
signal mac_txd, mac_rxd : STD_LOGIC_VECTOR(7 downto 0);
signal mac_txdvld, mac_txack, mac_rxclko, mac_rxdvld, mac_rxgoodframe, mac_rxbadframe : STD_LOGIC;
signal ipb_master_out : ipb_wbus;
......@@ -97,8 +98,14 @@ ARCHITECTURE rtl OF IPBusInterface IS
signal pkt_rx, pkt_tx, pkt_rx_led, pkt_tx_led, sys_rst: std_logic;
BEGIN
-- Connect IPBus clock and reset to output ports.
ipb_clk_o <= s_ipb_clk;
ipb_rst_o <= rst_ipb;
--! By default generate a physical MAC
generate_physicalmac: if ( BUILD_SIMULATED_ETHERNET /= 1 ) generate
-- DCM clock generation for internal bus, ethernet
clocks: entity work.clocks_s6_extphy port map(
sysclk_p => sysclk_p_i,
......@@ -111,11 +118,7 @@ BEGIN
rsto_ipb => rst_ipb,
onehz => onehz_o
);
-- Connect IPBus clock and reset to output ports.
ipb_clk_o <= s_ipb_clk;
ipb_rst_o <= rst_ipb;
-- leds <= ('0', '0', locked, onehz);
-- Ethernet MAC core and PHY interface
......@@ -144,8 +147,41 @@ BEGIN
rx_error => mac_rx_error
);
phy_rstb_o <= '1';
end generate generate_physicalmac;
--! Set generic BUILD_SIMULATED_ETHERNET to 1 to generate a simulated MAC
generate_simulatedmac: if ( BUILD_SIMULATED_ETHERNET = 1 ) generate
sim_clocks: entity work.clock_sim
port map (
clko125 => clk125,
clko25 => s_ipb_clk,
clko40 => open,
nuke => '0',
rsto => rst_125
);
rst_ipb <= rst_125;
clocks_locked_o <= '1';
-- clk125 <= sysclk_i; -- *must* run this simulation with 125MHz sysclk...
simulated_eth: entity work.eth_mac_sim
port map(
clk => clk125,
rst => rst_125,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
end generate generate_simulatedmac;
phy_rstb_o <= '1';
-- ipbus control logic
ipbus: entity work.ipbus_ctrl
generic map (
......
firmware/hdl/common/TPx3_iface.vhd
View file @ 9de93149
--! Simple module to interface AIDA TLU to LHCb TimePix3 telescope.
--! Accepts T0 sync signal and shutter signal from telescope and re-transmits.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
......@@ -9,11 +9,15 @@ use unisim.VComponents.all;
entity TPx3_iface is
port (
clk_4x_i : in std_logic; -- system clock
clk_4x_strobe : in std_logic; -- strobes high for one cycle every 4 of clk_4x
T0_p_i : in std_logic; -- T0 signal from timepix telescope clk/sync system
T0_n_i : in std_logic; -- T0 signal from timepix telescope clk/sync system
T0_o : out std_logic); -- T0 signal retimed onto system clock
clk_4x_i : in std_logic; --! system clock
clk_4x_strobe : in std_logic; --! strobes high for one cycle every 4 of clk_4x
T0_p_i : in std_logic; --! T0 signal from timepix telescope clk/sync system
T0_n_i : in std_logic; --! T0 signal from timepix telescope clk/sync system
T0_o : out std_logic; --! T0 signal retimed onto system clock
shutter_p_i : in std_logic; --! shutter signal from timepix telescope clk/sync system
shutter_n_i : in std_logic; --! shutter signal from timepix telescope clk/sync system
shutter_o : out std_logic --! shutter signal retimed onto system clock
);
end entity TPx3_iface;
......@@ -22,6 +26,8 @@ architecture rtl of TPx3_iface is
signal s_T0 , s_T0_d1 , s_T0_d2 , s_stretch_T0_in: std_logic := '0'; -- signal after IBufDS and sampled onto clk_4x
signal s_stretch_T0_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by T0ger_i
signal s_T0_out_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
signal s_shutter , s_shutter_d1 , s_shutter_d2 : std_logic := '0'; -- signal after IBufDS and sampled onto clk_4x
begin -- architecture rtl
......@@ -43,7 +49,7 @@ begin -- architecture rtl
s_T0_d1 <= s_T0;
s_T0_d2 <= s_T0_d1;
-- Stretch T0ger_i pulse to 4 clock cycles on clk4x
-- Stretch T0_i pulse to 4 clock cycles on clk4x
if s_T0_d1 = '1' then
s_stretch_T0_in <= '1';
s_stretch_T0_in_sr <= "111";
......@@ -65,5 +71,25 @@ begin -- architecture rtl
end if;
end process p_T0_retime;
cmp_IBUFDS_shutter : IBUFDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25")
port map (
O => s_shutter, -- Buffer output
I => shutter_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => shutter_n_i -- Diff_n buffer input (connect directly to top-level port)
);
-- Just retime onto the 4x clock. Probably should retime onto 1x clock.
p_shutter_retime: process (s_shutter , clk_4x_i) is
begin -- process p_shutter_retime
if rising_edge(clk_4x_i) then
s_shutter_d1 <= s_shutter;
s_shutter_d2 <= s_shutter_d1;
shutter_o <= s_shutter_d2;
end if;
end process p_shutter_retime;
end architecture rtl;
firmware/hdl/common/coincidenceLogic_rtl.vhd 0 → 100644
View file @ 9de93149
--=============================================================================
--! @file stretchPulse_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
--
--! @brief Takes a set of input pulses and produces an output pulse based on trigger pattern
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Include UNISIM to get CFGLUT5 definition
Library UNISIM;
use UNISIM.vcomponents.all;
entity coincidenceLogic is
generic (
g_nInputs : positive := 4; -- --! Number of trigger inputs. Must be four for this implementation
g_patternWidth : positive := 32); -- --! Width of trigger pattern. Must be 32 in this implementation
port (
configClk_i : in std_logic; -- --! Rising edge active
logicClk_i : in std_logic; -- --! Rising edge active
triggers_i : in std_logic_vector(g_nInputs-1 downto 0); -- --! Array of trigger inputs
trigger_o : out std_logic; -- --! Goes high when trigger pattern matched
auxTrigger_o : out std_logic; -- --! Goes high when auxillary trigger pattern matched
triggerPattern_i : in std_logic_vector(g_patternWidth-1 downto 0); -- --! Pattern to match triggers with
loadPattern_i : in std_logic); -- --! Pattern is loaded when loadPattern goes high.
end entity coincidenceLogic;
architecture rtl of coincidenceLogic is
signal s_configDataSR , s_configEnableSR: std_logic_vector( triggerPattern_i'range ) := ( others => '0' ); -- --! shift reg for config data
signal s_configBit , s_configEnable : std_logic := '0'; -- --! Take high to shift in configuration data.
signal s_trigOut , s_auxTrigOut : std_logic := '0'; -- registers for output data.
begin -- architecture rtl
--assert g_nInputs /= 4 report "Wrong number of inputs in coincidence logic" severity failure;
--assert g_patternWidth /= 32 report "Wrong pattern width in coincidence logic" severity failure;
-- See Xilinx UG615 ( Spartan-6 Libraries guide for HDL Designs"
CFGLUT5_inst : CFGLUT5
generic map (
INIT => X"FFFEFFFE") --! Default to "OR" of all inputs
port map (
CDO => open, -- Reconfiguration cascade output
O5 => s_trigOut , -- 4-LUT output
O6 => s_auxTrigOut, -- 5-LUT output
CDI => s_configBit, -- Reconfiguration data input
CE => s_configEnable, -- Reconfiguration enable input
CLK => configClk_i, -- Clock input
I0 => triggers_i(0), -- Logic data input
I1 => triggers_i(1), -- Logic data input
I2 => triggers_i(2), -- Logic data input
I3 => triggers_i(3), -- Logic data input
I4 => '1' --! Tie high to set O5 and O6 to different functions.
);
p_controlInit: process (configClk_i , triggerPattern_i , loadPattern_i) is
begin -- process p_controlInit
if rising_edge(configClk_i) then
-- Contol configuration
if ( loadPattern_i = '1' ) then -- Load pattern into shift register
s_configDataSR <= triggerPattern_i;
s_configEnableSR <= ( others => '1');
s_configBit <= '0';
s_configEnable <= '0';
else -- If load isn't active then shift data out.
s_configBit <= s_configDataSR( s_configDataSR'left ); --! Shift in MSB first.
s_configDataSR <= s_configDataSR( s_configDataSR'left-1 downto 0) & '0'; --! Shift up
s_configEnable <= s_configEnableSR ( s_configEnableSR'left); --! enable will stay high for as long as there is data in config data SR
s_configEnableSR <= s_configEnableSR( s_configEnableSR'left-1 downto 0) & '0'; --! Shift up
end if;
end if;
end process p_controlInit;
--! Register output data
p_registerData: process (logicClk_i) is
begin -- process p_registerData
if rising_edge(logicClk_i) then
trigger_o <= s_trigOut;
auxTrigger_o <= s_auxTrigOut;
end if;
end process p_registerData;
end architecture rtl;
firmware/hdl/common/eventFormatter_rtl.vhd
View file @ 9de93149
......@@ -93,7 +93,6 @@ ENTITY eventFormatter IS
ipbus_o : OUT ipb_rbus;
data_strobe_o : OUT std_logic; -- goes high when data ready to load into event buffer
event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
event_number_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
reset_timestamp_i : IN std_logic; --! Taking high causes timestamp to be reset. Combined with internal timestmap reset and written to reset_timestamp_o
reset_timestamp_o : OUT std_logic; --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
trigger_count_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0)
......@@ -169,7 +168,7 @@ ARCHITECTURE rtl OF eventFormatter IS
signal trigger_inputs_fired_d1 : std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0) := (others => '0');
signal trigger_times_d1 : t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0) := (others => (others=>'0'));
signal s_reset_timestamp_4x : std_logic := '0'; --! Single pulse on 4x domain
signal s_reset_timestamp_4x, s_reset_timestamp_4x_ipbus , s_reset_timestamp_4x_external , s_reset_timestamp_4x_external_p1 , s_reset_timestamp_4x_external_p2 : std_logic := '0'; --! Single pulse on 4x domain
signal s_reset_timestamp_ipbus : std_logic := '0'; --! Single pulse on IPBus clock domain
signal s_ipbus_ack : std_logic := '0'; -- used to produce a delayed IPBus ack signal
......@@ -234,8 +233,23 @@ BEGIN
clk_input_i => ipbus_clk_i,
pulse_i => s_reset_timestamp_ipbus,
clk_output_i => clk_4x_logic_i,
pulse_o => s_reset_timestamp_4x
pulse_o => s_reset_timestamp_4x_ipbus
);
-- Combine reset timestamp from IPBus and external source
-- purpose: combines resets from IPBus and external source onto clk_4x_logic_i
-- type : combinational
-- inputs : clk_4x_logic_i
-- outputs: s_reset_timestamp_4x
p_combine_reset_timestamps: process (clk_4x_logic_i) is
begin -- process p_combine_reset_timestamps
if rising_edge(clk_4x_logic_i) then
s_reset_timestamp_4x_external_p2 <= reset_timestamp_i;
s_reset_timestamp_4x_external_p1 <= s_reset_timestamp_4x_external_p2 ;
s_reset_timestamp_4x_external <= s_reset_timestamp_4x_external_p1 ;
s_reset_timestamp_4x <= s_reset_timestamp_4x_external or s_reset_timestamp_4x_ipbus;
end if;
end process p_combine_reset_timestamps;
reset_timestamp_o <= s_reset_timestamp_4x;
......
firmware/hdl/common/ipbus_ver.vhd
View file @ 9de93149
......@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is
begin
ipbus_out.ipb_rdata <= X"a5f0" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_rdata <= X"a603" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
......
firmware/hdl/common/stretchPulse_rtl.vhd 0 → 100644
View file @ 9de93149
--=============================================================================
--! @file stretchPulse_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
--
--! @brief Takes a pulse on input, stretches it and delays it.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity stretchPulse is
generic (
g_PARAM_WIDTH : positive := 4); --! number of bits in parameters (width, delay)
port (
clk_i : in std_logic; --! Active high
pulse_i : in std_logic; --! Active high
pulse_o : out std_logic; --! delayed and stretched
pulseWidth_i : in std_logic_vector(g_PARAM_WIDTH-1 downto 0); --! Minimum pulse width ( in clock cycles )
pulseDelay_i : in std_logic_vector(g_PARAM_WIDTH-1 downto 0) --! Delay is pulseDelay_i +1 clock cycles
);
end entity stretchPulse;
architecture rtl of stretchPulse is
begin -- architecture rtl
--! Dummy for now. Just pass input to output
p_registerPulse: process (clk_i , pulse_i) is
begin -- process p_registerPulse
if rising_edge(clk_i) then
pulse_o <= pulse_i;
end if;
end process p_registerPulse;
end architecture rtl;
firmware/hdl/common/triggerLogic_rtl.vhd
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firmware/hdl/miniTLU/top_extphy_struct.vhd
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firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/IPBusInterface_rtl.vhd.rlnk deleted 100644 → 0
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../../../../hdl/common/IPBusInterface_rtl.vhd
\ No newline at end of file
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/arrivalTimeLUT_rtl.vhd.rlnk deleted 100644 → 0
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../../../../hdl/common/arrivalTimeLUT_rtl.vhd
\ No newline at end of file
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/dualSERDES_1to4_rtl.vhd.rlnk deleted 100644 → 0
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../../../../hdl/common/dualSERDES_1to4_rtl.vhd
\ No newline at end of file
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eventBuffer_rtl.vhd.rlnk deleted 100644 → 0
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../../../../hdl/common/eventBuffer_rtl.vhd
\ No newline at end of file
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eventFormatter_rtl.vhd.rlnk deleted 100644 → 0
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../../../../hdl/common/eventFormatter_rtl.vhd
\ No newline at end of file
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_rtl.vhd deleted 100644 → 0
View file @ bc0f68cf
--=============================================================================
--! @file top_extphy_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.top_extphy.rtl
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:11:55 11/09/12
--
--! @version v0.1
--
--! @details
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY top_extphy IS
GENERIC(
NUM_DUTS : positive := 3;
NUM_TRIG_INPUTS : positive := 4
);
PORT(
busy_i : IN std_logic_vector (NUM_DUTS-1 DOWNTO 0);
cfd_discr_i : IN std_logic_vector (NUM_TRIG_INPUTS-1 DOWNTO 0);
dut_clk : IN std_logic_vector (NUM_DUTS-1 DOWNTO 0);
gmii_rx_clk_i : IN std_logic;
gmii_rx_dv_i : IN std_logic;
gmii_rx_er_i : IN std_logic;
gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
sysclk_n_i : IN std_logic;
sysclk_p_i : IN std_logic; -- ! 200 MHz xtal clock
threshold_discr_i : IN std_logic_vector (NUM_TRIG_INPUTS-1 DOWNTO 0);
gmii_gtx_clk_o : OUT std_logic;
gmii_tx_en_o : OUT std_logic;
gmii_tx_er_o : OUT std_logic;
gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
i2c_scl_o : OUT std_logic;
leds_o : OUT std_logic_vector (3 DOWNTO 0);
phy_rstb_o : OUT std_logic;
reset_or_clk_o : OUT std_logic_vector (NUM_DUTS-1 DOWNTO 0);
triggers_o : OUT std_logic_vector (NUM_DUTS-1 DOWNTO 0);
i2c_sda_d : INOUT std_logic
);
-- Declarations
END ENTITY top_extphy ;
--
ARCHITECTURE rtl OF top_extphy IS
BEGIN
END ARCHITECTURE rtl;
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
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/users/phdgc/IPBus_stuff/fmc_tlu_test_tpix3_nov14/fmc-mtlu/firmware/hdl/miniTLU/top_extphy_struct.vhd
\ No newline at end of file
../../../../hdl/miniTLU/top_extphy_struct.vhd
\ No newline at end of file
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_dutinterfaces._epf
View file @ 9de93149
DEFAULT_ARCHITECTURE atom rtl
DEFAULT_FILE atom ../../../../hdl/common/DUTInterfaces_rtl.vhd
DEFAULT_FILE atom DUTInterfaces_rtl.vhd
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_eventformatter._epf
View file @ 9de93149
DEFAULT_ARCHITECTURE atom rtl
DEFAULT_FILE atom ../../../../hdl/common/eventFormatter_rtl.vhd
DEFAULT_FILE atom eventFormatter_rtl.vhd
firmware/scripts/aida_mini_tlu_addr_map.txt
View file @ 9de93149
*RegName RegAddr RegMask R W
*-------------------------------------------------------------
FirmwareId 0x00000000 0xffffffff 1 0
*
* DUT interfaces base = 0x020
DUTMaskW 0x00000020 0xffffffff 0 1
DUTIgnoreBusyW 0x00000021 0xffffffff 0 1
DUTMaskR 0x00000022 0xffffffff 1 0
DUTIgnoreBusyR 0x00000023 0xffffffff 1 0
IgnoreDUTBusyW 0x00000021 0xffffffff 0 1
IgnoreShutterVetoW 0x00000022 0xffffffff 0 1
DUTMaskR 0x00000024 0xffffffff 1 0
IgnoreDUTBusyR 0x00000025 0xffffffff 1 0
IgnoreShutterVetoR 0x00000026 0xffffffff 0 1
*
* trigger inputs = 0x040
SerdesRstW 0x00000040 0xffffffff 0 1
......@@ -16,16 +19,18 @@ ThrCount2R 0x0000004b 0xffffffff 1 0
ThrCount3R 0x0000004c 0xffffffff 1 0
*
* trigger logic = 0x060 **Note the different read and write directions
InternalTriggerIntervalW 0x00000062 0xffffffff 1 1
TriggerMaskW 0x00000063 0xffffffff 1 1
TriggerVetoW 0x00000064 0xffffffff 1 1
ResetCountersW 0x00000066 0xffffffff 0 1
PostVetoTriggersR 0x00000068 0xffffffff 1 0
PreVetoTriggersR 0x00000069 0xffffffff 1 0
InternalTriggerIntervalR 0x0000006a 0xffffffff 1 1
TriggerMaskR 0x0000006b 0xffffffff 1 1
TriggerVetoR 0x0000006c 0xffffffff 1 1
ExternalTriggerVetoR 0x0000006d 0xffffffff 1 0
InternalTriggerIntervalW 0x00000062 0xffffffff 1 1
InternalTriggerIntervalR 0x0000006A 0xffffffff 1 1
TriggerPatternW 0x00000063 0xffffffff 1 1
TriggerPatternR 0x0000006B 0xffffffff 1 1
TriggerVetoW 0x00000064 0xffffffff 1 1
TriggerVetoR 0x0000006C 0xffffffff 1 1
ExternalTriggerVetoR 0x0000006D 0xffffffff 1 0
ResetCountersW 0x00000066 0xffffffff 0 1
PulseStretchW 0x00000067 0xffffffff 1 1
PulseStretchR 0x0000006F 0xffffffff 1 1
*
* event buffer = 0x080
EventFifoData 0x00000080 0xffffffff 1 0
......@@ -46,45 +51,9 @@ i2c_rx 0x000000C3 0x000000ff 1 0
i2c_cmd 0x000000C4 0x000000ff 0 1
i2c_status 0x000000C4 0x000000ff 1 0
*
* trigger generator = 0x0E0
TriggerLength 0x000000E0 0xffffffff 1 1
TrigStartupDeadTime 0x000000E1 0xffffffff 1 1
TrigInterpulseDeadTime 0x000000E2 0xffffffff 1 1
TriggerDelay 0x000000E3 0xffffffff 1 1
NMaxTriggers 0x000000E4 0xffffffff 1 1
TrigEvtNumber 0x000000E5 0xffffffff 1 0
RstTriggerCounter 0x000000E6 0xffffffff 1 1
TrigRearmDeadTime 0x000000E7 0xffffffff 1 1
*
* shutter generator = 0x100
ShutterLength 0x00000100 0xffffffff 1 1
ShutStartupDeadTime 0x00000101 0xffffffff 1 1
ShutInterpulseDeadTime 0x00000102 0xffffffff 1 1
ShutterDelay 0x00000103 0xffffffff 1 1
NMaxShutters 0x00000104 0xffffffff 1 1
ShutEvtNumber 0x00000105 0xffffffff 1 0
RstShutterCounter 0x00000106 0xffffffff 1 1
ShutRearmDeadTime 0x00000107 0xffffffff 1 1
*
* spill generator = 0x120
SpillLength 0x00000120 0xffffffff 1 1
SpillStartupDeadTime 0x00000121 0xffffffff 1 1
SpillInterpulseDeadTime 0x00000122 0xffffffff 1 1
SpillDelay 0x00000123 0xffffffff 1 1
NMaxSpills 0x00000124 0xffffffff 1 1
SpillEvtNumber 0x00000125 0xffffffff 1 0
RstSpillCounter 0x00000126 0xffffffff 1 1
SpillRearmDeadTime 0x00000127 0xffffffff 1 1
*
* Event formatter = 0x140
Enable_Record_Data 0x00000140 0xffffffff 1 1
ResetTimestampW 0x00000141 0xffffffff 0 1
CurrentTimestampLR 0x00000142 0xffffffff 1 0
CurrentTimestampHR 0x00000143 0xffffffff 1 0
*
* Handshakes = 0x160
HandshakeTypeW 0x00000160 0xffffffff 0 1
HandshakeConfW 0x00000161 0xffffffff 0 1
TPx3_T0SyncLenW 0x00000162 0xffffffff 0 1
HandshakeTypeR 0x00000168 0xffffffff 1 0
HandshakeConfR 0x00000169 0xffffffff 1 0
TPx3_T0SyncLenR 0x0000016a 0xffffffff 1 0
TPx3_ShDTimeLenR 0x0000016b 0xffffffff 1 0
firmware/scripts/test_aida_tlu_internal_triggers.py 0 → 100644
View file @ 9de93149
#
# Script to exercise AIDA mini-TLU
#
# David Cussans, December 2012
#
# Hacked to only test internal triggers
from PyChipsUser import *
from FmcTluI2c import *
import sys
import time
def mean(TS):
val=0
for i in range(1,len(TS)):
val+=TS[i]-TS[i-1]
return val/(len(TS)-1)
def pulseT0(board):
# set T0 bit to 1
PulseBits = board.read("ConfBits")
# print "ConfBits before pulseT0: ", hex(PulseBits)
PulseBits = PulseBits | 0x2
# board.write("ConfBits", PulseBits)
# print "ConfBits after pulseT0: ", hex(PulseBits)
# reset T0 bit
PulseBits = board.read("ConfBits")
PulseBits = PulseBits & 0xfffffffd
board.write("ConfBits", PulseBits)
PulseBits = board.read("ConfBits")
# print "ConfBits after reseting pulseT0: ", hex(PulseBits)
# Point to TPix3 fanout
fanoutAddrTab = AddressTable("./tpix3_fanout_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 1
fanoutBoard = ChipsBusUdp(fanoutAddrTab,"192.168.200.16",50001)
# set T0 width
T0width = 0x10
fanoutBoard.write("T0syncLength", T0width)
T0width = fanoutBoard.read("T0syncLength")
print "T0width = ", T0width
# POint to TLU
bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 2
board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
# Check the bus for I2C devices
boardi2c = FmcTluI2c(board)
firmwareID=board.read("FirmwareId")
print "Firmware = " , hex(firmwareID)
print "Scanning I2C bus:"
scanResults = boardi2c.i2c_scan()
print scanResults
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
resetClocks = 0
resetSerdes = 0
# set DACs to -200mV
print "Setting all threshold DAC to -200mV "
boardi2c.set_threshold_voltage(7, -0.2)
clockStatus = board.read("LogicClocksCSR")
print "Clock status = " , hex(clockStatus)
if resetClocks:
print "Resetting clocks"
board.write("LogicRst", 1 )
clockStatus = board.read("LogicClocksCSR")
print "Clock status after reset = " , hex(clockStatus)
inputStatus = board.read("SerdesRstR")
print "Input status = " , hex(inputStatus)
if resetSerdes:
board.write("SerdesRstW", 0x00000003 )
inputStatus = board.read("SerdesRstR")
print "Input status during reset = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000000 )
inputStatus = board.read("SerdesRstR")
print "Input status after reset = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000004 )
inputStatus = board.read("SerdesRstR")
print "Input status during calibration = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000000 )
inputStatus = board.read("SerdesRstR")
print "Input status after calibration = " , hex(inputStatus)
inputStatus = board.read("SerdesRstR")
print "Input status = " , hex(inputStatus)
count0 = board.read("ThrCount0R")
print " Count 0 = " , count0
count1 = board.read("ThrCount1R")
print " Count 1 = " , count1
count2 = board.read("ThrCount2R")
print " Count 2 = " , count2
count3 = board.read("ThrCount3R")
print " Count 3 = " , count3
board.write("InternalTriggerIntervalW",0)
print "Enabling DUT 0"
board.write("DUTMaskW",1)
DUTMask = board.read("DUTMaskR")
print "DUTMaskR = " , DUTMask
print "Ignore veto on DUT 1"
board.write("IgnoreDUTBusyW",2)
IgnoreDUTBusy = board.read("IgnoreDUTBusyR")
print "IgnoreDUTBusyR = " , IgnoreDUTBusy
print "Turning off software trigger veto"
board.write("TriggerVetoW",0)
print "Reseting FIFO"
board.write("EventFifoCSR",0x2)
print "Disabling data recording"
board.write("Enable_Record_Data",0)
#print "Enabling handshake: No-handshake"
#board.write("HandshakeTypeW",1)
TriggerInterval = 160
print "Setting internal trigger interval to " , TriggerInterval
board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
trigInterval = board.read("InternalTriggerIntervalR")
print "Trigger interval read back as ", trigInterval
numLoops = 500000
for iLoop in range(0,numLoops):
# print "\n\nBefore reset"
preVetotriggerCount = board.read("PreVetoTriggersR")
postVetotriggerCount = board.read("PostVetoTriggersR")
print "pre , post veto triggers = " , preVetotriggerCount , postVetotriggerCount
timestampHigh = board.read("CurrentTimestampHR")
timestampLow = board.read("CurrentTimestampLR")
print "Current timestamp High,Low (hex) = " , hex(timestampHigh) , hex(timestampLow)
# print "\nresetting timestamp\n"
# pulseT0(fanoutBoard)
# preVetotriggerCount = board.read("PreVetoTriggersR")
# postVetotriggerCount = board.read("PostVetoTriggersR")
# print "pre , post veto triggers = " , preVetotriggerCount , postVetotriggerCount
# timestampHigh = board.read("CurrentTimestampHR")
# timestampLow = board.read("CurrentTimestampLR")
# print "Current timestamp High,Low (hex) = " , hex(timestampHigh) , hex(timestampLow)
time.sleep( 1.0)
firmware/simulation/scripts/setup.sh
View file @ 9de93149
#!/bin/sh
#export MODELSIM_ROOT="/software/CAD/Mentor/2013_2014/Questa/HDS_2012.2b/questasim/"
export MODELSIM_ROOT="/eda/mentor/2014-15/RHELx86/QUESTA-SV-AFV_10.4/questasim/"
export MODELSIM_ROOT="/software/CAD/Mentor/2014_2015/HDS_2013.1b/questasim/"
#export MODELSIM_ROOT="/eda/mentor/2014-15/RHELx86/QUESTA-SV-AFV_10.4/questasim/"
export ISE_VHDL_MTI="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.4/lin64/"
export ISE_VLOG_MTI="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.4/lin64/"
export FW_WORKSPACE=../../../..
......
firmware/ucf/sp605_FMC_mTLU_v1a.ucf
View file @ 9de93149
......@@ -86,6 +86,8 @@ NET "busy_p_i[1]" LOC = H13;
## "FMC_LA14_P" , C18 on FMC
# Hack to communicate with TPix3 telescope
#NET "busy_p_i[2]" LOC = C17;
NET "T0_p_i" LOC = C17; # seems to be swapped with shutter
#NET "T0_p_i" LOC = T12; # after swapping
## "FMC_LA20_P" , G21 on FMC
NET "triggers_p_o[0]" LOC = R9;
......@@ -95,11 +97,14 @@ NET "triggers_p_o[1]" LOC = C5;
# Hack to communicate with TPix3 telescope
#NET "triggers_p_o[2]" LOC = B18;
# Remove shutters ( also known as SPARE ) for now
# Connector J2 used by TPix connection
#NET "SPARE_N_O<1>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC
#NET "SPARE_N_O<2>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
#NET "SPARE_P_O<1>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC
#NET "SPARE_N_O<2>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
#NET "SPARE_P_O<2>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
NET "shutter_to_dut_n_o[1]" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
NET "shutter_to_dut_p_o[1]" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
## "FMC_LA27_P" , C26 on FMC
......@@ -119,7 +124,8 @@ NET "reset_or_clk_p_o[1]" LOC = B2;
## "FMC_LA18_P" , C22 on FMC
# Hack to communicate with TPix3 telescope
#D NET "reset_or_clk_p_o[2]" LOC = T12;
NET "T0_p_i" LOC = T12;
NET "TPix_Shutter_p_i" LOC = T12; # Seems to be swapped with T0....
#NET "TPix_Shutter_p_i" LOC = C17; # after swapping.
# Trigger Inputs
......@@ -170,6 +176,11 @@ NET "extclk_n_b" LOC = G11;
#NET "HDMI_POWER_ENABLE1" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA15_N" , H20 on FMC
## SP605 GPIO header.
NET "gpio_hdr[0]" LOC = "G7"; ## 1 on U52 (level shifter, U52.20 <-> GPIO_HEADER_0 <-> series R280 200 ohm <-> 1 on J55
NET "gpio_hdr[1]" LOC = "H6"; ## 3 on U52 (level shifter, U52.18 <-> GPIO_HEADER_0 <-> series R281 200 ohm <-> 2 on J55
NET "gpio_hdr[2]" LOC = "D1"; ## 4 on U52 (level shifter, U52.17 <-> GPIO_HEADER_0 <-> series R282 200 ohm <-> 3 on J55
NET "gpio_hdr[3]" LOC = "R7"; ## 5 on U52 (level shifter, U52.16 <-> GPIO_HEADER_0 <-> series R283 200 ohm <-> 4 on J55
## GPIO pins for debugging.
### 1 on J13 (thru series R100 200 ohm)
......
firmware/ucf/sp605_FMC_mTLU_v1a_tpixJ2.ucf 0 → 100644
View file @ 9de93149
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