\item[version] Returns the current version of firmware used to program the \gls{tlu}
\item[------------------------]
\item[DUTINTERFACES]
\item[DUTMaskW] Writing to this register allows to define which \gls{dut}s are active when in AIDA mode. The lower 4 bits of the register can be used to define the status of the \gls{dut}s: 1 for active, 0 for masked. \verb|hdmi1| is defined by bit 0, \verb|hdmi2| is defined by bit 1, \verb|hdmi3| is defined by bit 2, \verb|hdmi4| is defined by bit 3.
\item[IgnoreDUTBusyW] Writing to this register allows to ignore the busy signal from a particular \gls{dut} while in AIDA mode. The lower 4 bits are used to define the status for each device. A 1 indicates that the logic should ignore busy signals from the specific \gls{dut}.
\item[IgnoreShutterVetoW] The \gls{lsb} of this register can be written to define whether the \gls{dut} should ignore the shutter veto signal. Normally, when the shutter signal is asserted the \gls{dut} reports busy. If this bit is flag the \gls{dut} will ignore the shutter signal.
\item[DUTInterfaceModeW] Write register to define the mode of operation for a \gls{dut}. Two bits per device can be used to define the mode; currently only two modes are available (AIDA, EUDET).\\
\item[DUTInterfaceModeW] Write register to define the mode of operation for a \gls{dut}. Two bits per device can be used to define the mode; currently only two modes are available (AIDA, EUDET) but the second but is reserved for additional modes introduced in the future.\\
The bit pairs are packed from the \gls{lsb} starting with \verb|hdmi1| (bits 0, 1), \verb|hdmi2| (bits 2, 3), \verb|hdmi3| (bits 4, 5), \verb|hdmi4| (bits 6, 7).
\begin{itemize}
\item bit pair X0: EUDET
\item bit pair X1: AIDA
\item bit pair \texttt{X0}: EUDET
\item bit pair \texttt{X1}: AIDA
\end{itemize}
\item[DUTInterfaceModeModifierW] Write register. This register only affects the EUDET mode of operation. For each \gls{dut} two bits can be configured although cyrrently only the lower of the pair is considere. The bit packing is done in a manner similar to the DUTInterfaceMode. Set bit high to allow asynchronous veto using \verb|DUT_CLK| when in EUDET mode.
\item[DUTInterfaceModeR] Read the content of the DUTInterfaceMode register.
...
...
@@ -236,7 +236,7 @@
\item[ThrCount5R] Read register. Returns the number of pulses above threshold for the trigger input.
\end{description}
\begin{description}\label{ch:triggerLogic}
\begin{description}\label{ch:triggerLogicAdd}
\item[------------------------]
\item[TRIGGERLOGIC]
\item[PostVetoTriggersR] Read register. Returns the number of triggers recorded in the \gls{tlu} after the veto is applied. These are the triggers actually sent to the \gls{dut}s.
@@ -23,10 +23,10 @@ The status register (SerdesRst) is as follows:
9 bits are used to determine trigger edges. 8 are from the deserializers, 1 is added as the LSB and is the MSB from the previous word.
\section{Trigger logic}\label{ch:triggerLogic}
The TLU has six trigger inputs than can be used to generate a valid trigger event. The number of possible different trigger combinations is $2^6=64$ so a 64-bit word can be used to decide the valid combinations. In the hardware the 64-bit word is split into two 32-bit words and the rules to generate the trigger can be specified by the user by writing in the two 32-bit registers \verb|TriggerPattern_highW| and \verb|TriggerPattern_lowW|: the first stores the 32 most significative bits of the trigger word, the latter stores the least significative bits.\\
The TLU has six trigger inputs than can be used to generate a valid trigger event. The number of possible different trigger combinations is $2^6=64$ so a 64-bit word can be used to decide the valid combinations. In the hardware the 64-bit word is split into two 32-bit words (indicated as \gls{msb} and \gls{lsb} word) and the rules to generate the trigger can be specified by the user by writing in the two 32-bit registers \verb|TriggerPattern_highW| and \verb|TriggerPattern_lowW|: the first stores the 32 most significative bits of the trigger word, the latter stores the least significative bits.\\
The user can select any combination of the trigger inputs and declare it a valid trigger pattern by setting a 1 in the corresponding trigger configuration word.
Tables~\ref{tab:trigconfigLow} and ~\ref{tab:trigconfigHigh} show an example of how to determine the trigger configuration words: whenever a valid trigger combination is encountered, the user should put a 1 in the corresponding row under the PATTERN column. The pattern thus obtained is the required word to write in the configuration register.\\
It is important to note that this solution allows the user to set veto pattern as well: for instance if only word 31 from table~\ref{tab:trigconfigLow} were picked, then the \gls{tlu} would only register a trigger when the combination $\overline{I_{5}}$+ $I_{4}$ + $I_{3}$ + $I_{2}$ + $I_{1}$ + $I_{0}$ was presented at its inputs. In other words, in this specific case $I_{5}$ would act as a veto signal.
It is important to note that this solution allows the user to set veto pattern as well: for instance if only word 31 from table~\ref{tab:trigconfigLow} were picked, then the \gls{tlu} would only register a trigger when the combination $\overline{I_{5}}$* $I_{4}$ * $I_{3}$ * $I_{2}$ * $I_{1}$ * $I_{0}$ was presented at its inputs. In other words, in this specific case $I_{5}$ would act as a veto signal and the \gls{tlu} would \textbf{not} produce a trigger if $I_{5}$=1.
% Please add the following required packages to your document preamble:
A ``1'' in the logic table means that the corresponding input must be active to produce a valid trigger. Similarly, a ``0'' indicates that the corresponding input must be inactive (i.e. is a veto, not an ignore). Any change in input configuration will cause the logic to re-assess the trigger status. The following section gives a brief example.\\
\end{alertinfo}
\begin{alertinfo}{Bit 0 meaning}
A 1 in the lowest bit of the \gls{lsb} word indicates that $\overline{I_{5}}$ * $\overline{I_{4}}$ * $\overline{I_{3}}$ * $\overline{I_{2}}$ * $\overline{I_{1}}$ * $\overline{I_{0}}$ is a valid trigger combination, so the \gls{tlu} will produce a trigger when all the inputs are unactive (i.e. even if all the inputs are unplugged). Apart from very specific cases, this is generally not a desired behaviour.
\end{alertinfo}
\subsubsection{Example}
In this example we have connected a pulser to two inputs of the \gls{tlu}, namely input 0 and input 4. The inputs fire with a small, random delay with respect to each other.\\
In order to ensure that the signals overlap adequately, we use the \emph{stretch} register (see chapter~\ref{ch:triggerLogic}) to increase the length of the pulses: we extend \emph{in0} to 10 clock cycles and \emph{in4} to 8 clock cycles. The resulting signals are shown in figure~\ref{Fig:exampleExtendedTriggers}.
In order to ensure that the signals overlap adequately, we use the \emph{stretch} register (see chapter~\ref{ch:triggerLogic}) to increase the length of the pulses: we extend \emph{in0} to 10 clock cycles and \emph{in4} to 8 clock cycles, where the clock has a frequency of 160~MHz. The resulting signals are shown in figure~\ref{Fig:exampleExtendedTriggers}.
