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AIDA-2020 TLU
Commit c0e9d64f authored by David Cussans's avatar David Cussans
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Merged Alvaro's branch back to trunk

parent bab8d6ee
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firmware/config/ise14/sp601/setup_project.tcl
View file @ c0e9d64f
......@@ -74,6 +74,7 @@ xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd
#xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
# Add Opencores files for i2c interface
xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
......@@ -124,9 +125,13 @@ xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/TPx3Logic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/GPP_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
# Then add the HDL-Designer generated files..
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
......
firmware/config/ise14/sp605/coregen.cgp
View file @ c0e9d64f
......@@ -2,8 +2,8 @@ SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET flowvendor = Other
SET package = fgg484
SET speedgrade = -3
SET verilogsim = true
SET verilogsim = false
SET vhdlsim = true
firmware/config/ise14/sp605/setup_project.tcl
View file @ c0e9d64f
......@@ -8,6 +8,8 @@ project set "Enable Multi-Threading" "2" -process "Map"
project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" -process "Map"
project set "Enable Multi-Threading" "2" -process "Place & Route"
project set "Enable BitStream Compression" TRUE -process "Generate Programming File"
project set "Preferred Language" "VHDL"
project set "Set SPI Configuration Bus Width spartan6" 4
# source $::env(REPOS_FW_DIR)/firmware/example_designs/scripts/addfiles.tcl
......@@ -68,9 +70,10 @@ xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd
xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd
#xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
# Add Opencores files for i2c interface
......@@ -115,7 +118,7 @@ xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/serdesCalibrateFSM_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/IODELAYCal_FSM_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
#xfile add fmc-mtlu/firmware/hdl/common/sync_reg.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
......@@ -124,6 +127,16 @@ xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/TPx3Logic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/GPP_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/TPx3Logic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
# Then add the HDL-Designer generated files..
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
......@@ -133,7 +146,7 @@ xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vh
# Add user constraints file
xfile add fmc-mtlu/firmware/ucf/sp605_FMC_mTLU.ucf
xfile add fmc-mtlu/firmware/ucf/sp605_FMC_mTLU_v1a.ucf
project close
......
firmware/hdl/common/DUTInterfaces_rtl.vhd
View file @ c0e9d64f
This diff is collapsed.
firmware/hdl/common/GPP_rtl.vhd 0 → 100644
View file @ c0e9d64f
This diff is collapsed.
firmware/hdl/common/serdesCalibrateFSM_rtl.vhd → firmware/hdl/common/IODELAYCal_FSM_rtl.vhd
View file @ c0e9d64f
--=============================================================================
--! @file serdesCalibrateFSM_rtl.vhd
--! @file IODELAYCal_FSM_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
......@@ -12,7 +12,7 @@
--! Iserdes, IDelay
--! based on code by Alvaro Dosil\n
--
--! @author Alvaro Dosil (David Cussans , David.Cussans@bristol.ac.uk)
--! @author Alvaro Dosil
--
--! @date 22/Feb/2014
--
......@@ -29,33 +29,31 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity serdesCalibrateFSM is
port (
serdes_reset_i : in std_logic; --! Take high to start calibration
fsm_clock_i : in std_logic;
busy_idelay_m_i , busy_idelay_m_i : in std_logic; --! Status of IDELAY elements.
calibrate_o , reset_o : out std_logic --! Output from FSM to calibrate and reset lines
entity IODELAYCal_FSM is
port (
clk_i : in std_logic; --! Global clock
startcal_i : in std_logic; --! Start calibration
busy_i : in std_logic; --! Status of the IDELAY component
calibrate_o : out std_logic; --! Calibration signals to IODELAY
reset_o : out std_logic --! Reset to IODELAY component
);
end entity serdesCalibrateFSM;
end entity IODELAYCal_FSM;
architecture rtl of serdesCalibrateFSM is
architecture rtl of IODELAYCal_FSM is
signal s_calibration : std_logic := '0'; -- Start calibration
--! Calibration FSM state values
type state_values is (st0, st1, st2, st3, st4);
type state_values is (st0, st1, st2, st3);
signal pres_state, next_state: state_values := st0;
signal s_initial_cal : std_logic := '1'; -- Start up calibration flag
signal s_cal_FSM : std_logic := '0'; -- IODELAY reset
signal s_rst_FSM : std_logic := '0'; -- IODELAY reset
begin -- rtl
--! Calibration start condition
s_calibration <= serdes_reset_i or s_initial_cal;
--! Calibration FSM register
statereg: process(fabricClk_i, serdes_reset_i)
statereg: process(clk_i)
begin
if rising_edge(fabricClk_i) then
if rising_edge(clk_i) then
pres_state <= next_state; -- Move to next state
end if;
......@@ -63,7 +61,7 @@ begin -- rtl
--! Calibration FSM combinational block
fsm: process(pres_state, s_calibration, s_busy_idelay_m)
fsm: process(pres_state, startcal_i, busy_i)
begin
next_state <= pres_state;
-- Default values
......@@ -74,36 +72,26 @@ begin -- rtl
-- st0 - IDLE
when st0=>
if ( s_calibration = '1') then
if ( startcal_i = '1') then
next_state <= st1; -- Next state is "st1 - SEND CALIBRATION SIGNAL"
end if;
-- st1 - SEND CALIBRATION SIGNAL
-- st1 - SEND CALIBRATION SIGNAL
when st1=>
s_cal_FSM <= '1';
s_initial_cal <= '0';
if s_busy_idelay_m = '1' then
next_state <= st2; -- Next state is "st2 - WAIT BUSY = '0'"
end if;
next_state <= st2; -- Next state is "st2 - WAIT BUSY = '0'"
-- st2 - WAIT BUSY = '0'
-- st2 - WAIT BUSY = '0'
when st2=>
if s_busy_idelay_m = '0' then
if busy_i = '0' then
next_state <= st3; -- Next state is "st3 - RESET STATE"
end if;
-- st3 - RESET STATE
when st3=>
s_Rst_FSM <= '1';
if s_busy_idelay_m = '1' then
next_state <= st4; -- Next state is "st4 - WAIT BUSY = '0'"
end if;
-- st4 - WAIT BUSY = '0'
when st4=>
if s_busy_idelay_m = '0' then
next_state <= st0; -- Next state is "st0 - IDLE"
end if;
next_state <= st0; -- Next state is "st0 - IDLE"
end case;
end process fsm;
......
firmware/hdl/common/TPx3Logic_rtl.vhd 0 → 100644
View file @ c0e9d64f
--=============================================================================
--! @file TPx3Logic_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Santiago de Compostela, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.TPx3Logic.rtl
--
--! @brief Produces shutters \n
--! IPBus address map:\n
--
--! @author Alvaro Dosil , alvaro.dosil@usc.es
--
--! @date 16:06:19 11/06/14
--
--! @version v0.1
--
--! @details
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! Move all IPBus stuff into ipbus_syncreg_v , which also handles clock domain
--! crossing. 20/Feb/2014 , David Cussans
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
ENTITY TPx3Logic IS
GENERIC(
g_IPBUS_WIDTH : positive := 32
);
PORT(
clk_i : IN std_logic; -- ! Rising edge active
Start_T0sync_i : IN std_logic;
T0syncLen_i : IN std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
logic_reset_i : IN std_logic; -- active high. Synchronous with clk_4x_logic
Busy_i : IN std_logic;
Veto_i : IN std_logic;
Shutter_o : OUT std_logic;
T0sync_o : OUT std_logic
);
-- Declarations
END ENTITY TPx3Logic ;
--
ARCHITECTURE rtl OF TPx3Logic IS
type state_values is (st0, st1);
signal pres_state, next_state: state_values;
signal s_Enable : std_logic := '0';
signal s_Shutter, s_Shutter_d1f, s_Shutter_d1, s_T0sync, s_T0sync_d1f : std_logic := '0';
signal s_Start_T0sync, s_Start_T0sync_d1, s_Start_T0sync_d2, s_Start_T0sync_d3 : std_logic;
signal Rst_T0sync, T0syncT : std_logic; --Load signal and flag for the T0sync
signal s_RunNumber : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- ! counters for runs
BEGIN
-----------------------------------------------------------------------------
-- Counters
-----------------------------------------------------------------------------
--T0sync counter
c_T0sync: entity work.CounterDown
generic map(
MAX_WIDTH => g_IPBUS_WIDTH
)
port map(
Clk => clk_i,
Reset => '0',
Load => Rst_T0sync,
InitVal => std_logic_vector(unsigned(T0syncLen_i)-1),
Count => open,
Q => T0syncT
);
-----------------------------------------------------------------------------
-- FSM register
-----------------------------------------------------------------------------
statereg: process(clk_i)
begin
if rising_edge(clk_i) then
pres_state <= next_state; --Move to the next state
end if;
end process statereg;
-----------------------------------------------------------------------------
-- FSM combinational block
-----------------------------------------------------------------------------
fsm: process(pres_state, s_Start_T0sync, T0syncT)
begin
next_state<=pres_state;
s_T0sync <='0';
Rst_T0sync <= '1';
case pres_state is
when st0=>
if s_Start_T0sync = '1' then
next_state <= st1; --Next state is "Whait for end of T0sync signal"
end if;
when st1 =>
Rst_T0sync <='0';
s_T0sync <='1';
if T0syncT = '1' then
next_state<=st0; --Next state is "Whait for end of T0-sync counter"
end if;
when others=>
next_state<=st0; --Next state is "Whait for T0sync start"
end case;
end process fsm;
-----------------------------------------------------------------------------
-- Busy signals
-----------------------------------------------------------------------------
s_Enable <= not Veto_i;
s_Shutter <= not Busy_i and not Veto_i;
--Shutter_o <= s_Shutter;
--T0sync_o <= s_T0sync;
-----------------------------------------------------------------------------
-- Count runs and synchronization
-----------------------------------------------------------------------------
p_run_counter: process (clk_i )
begin -- process p_run_counter
if rising_edge(clk_i) then
s_Start_T0sync_d1 <= Start_T0sync_i;
s_Start_T0sync_d2 <= s_Start_T0sync_d1;
s_Start_T0sync_d3 <= s_Start_T0sync_d2;
s_Start_T0sync <= s_Start_T0sync_d2 and ( not s_Start_T0sync_d3);
s_Shutter_d1 <= s_Shutter;
if logic_reset_i = '1' then
s_RunNumber <= (others => '0');
elsif s_Shutter='1' and s_Shutter_d1='0' then
s_RunNumber <= s_RunNumber + 1;
end if;
end if;
-- Signals synchronous with falling edge clock
if falling_edge(clk_i) then
s_Shutter_d1f <= s_Shutter;
Shutter_o <= s_Shutter_d1f;
s_T0sync_d1f <= s_T0sync;
T0sync_o <= s_T0sync_d1f;
end if;
end process p_run_counter;
END ARCHITECTURE rtl;
firmware/hdl/common/arrivalTimeLUT_rtl.vhd
View file @ c0e9d64f
......@@ -157,7 +157,7 @@ BEGIN
-- type : combinational
-- inputs : clk_4x_logic_i
-- outputs: arrival_time_o , rising_edge_o , falling_edge_o
examine_lut: process (clk_4x_logic_i , deserialized_data_i)
examine_lut: process (clk_4x_logic_i) -- , deserialized_data_i)
-- variable v_LUT_entry : std_logic_vector(g_NUM_FINE_BITS+2-1 downto 0); --! Entry in LUT pointed to by deserialized data
begin -- process examine_lut
......@@ -169,7 +169,7 @@ BEGIN
last_falling_edge_time_o <= s_coarse_bits & s_LUT_ENTRY(g_NUM_FINE_BITS-1 downto 0);
rising_edge_o <= s_LUT_ENTRY(c_RISING_EDGE_BIT);
falling_edge_o <= s_LUT_ENTRY(c_FALLING_EDGE_BIT);
multiple_edges_o <= s_LUT_ENTRY(c_MULTI_EDGE_BIT);
multiple_edges_o <= s_LUT_ENTRY(c_MULTI_EDGE_BIT);
end if;
end process examine_lut;
......@@ -190,7 +190,7 @@ BEGIN
PORT MAP (
clock_i => clk_4x_logic_i,
enable_i => '1',
reset_i => strobe_4x_logic_i, --'0',
reset_i => strobe_4x_logic_i, -- Synchronous reset, so the counter will present result_o="11" when reset_i='1'
result_o => s_coarse_bits
);
......
firmware/hdl/common/counterDown.vhd 0 → 100644
View file @ c0e9d64f
--Counter down
--Outputs: Q<='1' while counting
-- Q<='0' if not counting
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY CounterDown IS
GENERIC(
MAX_WIDTH: positive := 32
);
PORT(
Clk : in std_logic;
Reset : in std_logic;
Load : in std_logic;
InitVal : in std_logic_vector(MAX_WIDTH-1 downto 0);
Count : out Std_logic_vector(MAX_WIDTH-1 downto 0);
Q : out std_logic
);
END ENTITY CounterDown;
architecture rtl of CounterDown is
signal cnt : std_logic_vector(MAX_WIDTH-1 downto 0);
signal Qtmp : std_logic;
begin
Counter: process (Clk, Reset)
begin
if (Reset='1') then
cnt <= (others =>'0');
elsif rising_edge(Clk) then
if (Load='1') then
cnt <= InitVal;
else
if Qtmp='0' then
cnt <= std_logic_vector(unsigned(cnt) - 1);
end if;
end if;
end if;
end process;
Qtmp <= '1' when cnt=(cnt'range=>'0') else
'0';
Count <= cnt;
Q <= Qtmp;
end rtl;
firmware/hdl/common/dualSERDES_1to4_rtl.vhd
View file @ c0e9d64f
......@@ -49,7 +49,7 @@ use unisim.vcomponents.all;
ENTITY dualSERDES_1to4 IS
PORT(
reset_i : IN std_logic; --! Resets IODELAY
calibrate_i : IN std_logic; --! Starts IODELAY calibration.
--calibrate_i : IN std_logic; --! Starts IODELAY calibration.
data_i : IN std_logic; --! from input buffer.
fastClk_i : IN std_logic; --! 4x fabric clock. e.g. 640MHz
fabricClk_i : IN std_logic; --! clock for output to FPGA. e.g. 160MHz
......@@ -57,7 +57,6 @@ ENTITY dualSERDES_1to4 IS
data_o : OUT std_logic_vector (7 DOWNTO 0); --! Deserialized data. Interleaved between prompt and delayed serdes.
--! data_o(0) is the oldest data
status_o : OUT std_logic_vector(1 downto 0) --! outputs from IODELAY "busy" 0=prompt,1=delayed
);
-- Declarations
......@@ -71,46 +70,45 @@ ARCHITECTURE rtl OF dualSERDES_1to4 IS
signal s_Data_i_d_p : std_logic;
signal s_Data_i_d_d : std_logic;
-- signal s_busy_idelay_m : std_logic; -- Indicates that the IDELAY isn't calibrating.
-- signal s_busy_idelay_s : std_logic; -- Indicates that the IDELAY isn't calibrating.
signal s_busy_idelay_p : std_logic; -- Busy from iodelay.
signal s_busy_idelay_d : std_logic; -- Busy from iodelay.
signal s_busy : std_logic; -- Busy from the two iodelays.
signal s_data_o : std_logic_vector(7 downto 0); --! Deserialized data
-- signal s_rst : std_logic := '0'; -- IODELAY and ISERDES reset
-- signal s_cal_FSM : std_logic := '0'; --! Take high to calibrate the IDELAY components
signal s_cal : std_logic := '0'; --! Calibration signal
signal s_rst_cal : std_logic := '0'; --! reset after calibration process
BEGIN
-- calibration_fsm: entity work.serdesCalibrateFSM
-- port map (
-- fsm_clk_i => fabricClk_i,
-- serdes_reset_i => serdes_reset_i,
-- busy_idelay_m_i => s_busy_idelay_m,
-- calibrate_o => s_cal_FSM,
-- reset_o => s_rst);
-- IODELAYs calibration FSM
IODELAYCal: entity work.IODELAYCal_FSM
port map (
clk_i => fabricClk_i,
startcal_i => reset_i,
busy_i => s_busy,
calibrate_o => s_cal,
reset_o => s_rst_cal);
IODELAY2_Prompt : IODELAY2
generic map (
COUNTER_WRAPAROUND => "WRAPAROUND" , -- "STAY_AT_LIMIT" or "WRAPAROUND"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT" , -- "STAY_AT_LIMIT" or "WRAPAROUND"
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
SERDES_MODE => "NONE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX",
IDELAY_VALUE => 0, -- Amount of taps for fixed input delay (0-255)
SIM_TAPDELAY_VALUE=> 75 -- Per tap delay used for simulation in ps
IDELAY_TYPE => "VARIABLE_FROM_ZERO",
IDELAY_VALUE => 0 -- Amount of taps for fixed input delay (0-255)
--SIM_TAPDELAY_VALUE=> 10 -- Per tap delay used for simulation in ps
)
port map (
-- BUSY => s_busy_idelay_m, -- 1-bit output: Busy output after CAL
BUSY => status_o(1), -- 1-bit output: Busy output after CAL
BUSY => s_busy_idelay_p, -- 1-bit output: Busy output after CAL
DATAOUT => s_Data_i_d_p, -- 1-bit output: Delayed data output to ISERDES/input register
DATAOUT2 => open, -- 1-bit output: Delayed data output to general FPGA fabric
DOUT => open, -- 1-bit output: Delayed data output
TOUT => open, -- 1-bit output: Delayed 3-state output
-- CAL => s_cal_FSM, -- 1-bit input: Initiate calibration input
CAL => calibrate_i, -- 1-bit input: Initiate calibration input
CAL => s_cal, -- 1-bit input: Initiate calibration input
CE => '0', -- 1-bit input: Enable INC input
CLK => fabricClk_i, -- 1-bit input: Clock input
IDATAIN => data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
......@@ -118,33 +116,29 @@ BEGIN
IOCLK0 => fastClk_i, -- 1-bit input: Input from the I/O clock network
IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
--RST => s_rst, -- 1-bit input: reset_i to zero or 1/2 of total delay period
RST => reset_i, -- 1-bit input: reset_i to 1/2 of total delay period
RST => s_rst_cal, -- 1-bit input: reset_i to 1/2 of total delay period
T => '1' -- 1-bit input: 3-state input signal
);
status_o(1) <= s_busy_idelay_p;
IODELAY2_Delayed : IODELAY2
generic map (
COUNTER_WRAPAROUND => "WRAPAROUND", -- "STAY_AT_LIMIT" or "WRAPAROUND"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- "STAY_AT_LIMIT" or "WRAPAROUND"
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
SERDES_MODE => "NONE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "VARIABLE_FROM_ZERO",
IDELAY_VALUE => 0, -- Amount of taps for fixed input delay (0-255) 10->0.75nS, 11->0.825nS
IDELAY2_VALUE => 0, -- Delay value when IDELAY_MODE="PCI" (0-255)
ODELAY_VALUE => 0, -- Amount of taps fixed output delay (0-255)
SIM_TAPDELAY_VALUE => 75 -- Per tap delay used for simulation in ps
IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX",
IDELAY_VALUE => 0, -- Amount of taps for fixed input delay (0-255)
IDELAY2_VALUE => 0 -- Delay value when IDELAY_MODE="PCI" (0-255)
--SIM_TAPDELAY_VALUE => 10 -- Per tap delay used for simulation in ps
)
port map (
-- BUSY => s_busy_idelay_s, -- 1-bit output: Busy output after CAL
BUSY => status_o(0), -- 1-bit output: Busy output after CAL
BUSY => s_busy_idelay_d, -- 1-bit output: Busy output after CAL
DATAOUT => s_Data_i_d_d, -- 1-bit output: Delayed data output to ISERDES/input register
DATAOUT2 => open, -- 1-bit output: Delayed data output to general FPGA fabric
DOUT => open, -- 1-bit output: Delayed data output
TOUT => open, -- 1-bit output: Delayed 3-state output
-- CAL => s_cal_FSM, -- 1-bit input: Initiate calibration input
CAL => calibrate_i, -- 1-bit input: Initiate calibration input
CAL => s_cal, -- 1-bit input: Initiate calibration input
CE => '0', -- 1-bit input: Enable INC input
CLK => fabricClk_i, -- 1-bit input: Clock input
IDATAIN => data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
......@@ -152,11 +146,12 @@ BEGIN
IOCLK0 => fastClk_i, -- 1-bit input: Input from the I/O clock network
IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
--RST => s_rst, -- 1-bit input: reset_i to zero or 1/2 of total delay period
RST => reset_i, -- 1-bit input: reset_i to zero
RST => s_rst_cal, -- 1-bit input: reset_i to zero
T => '1' -- 1-bit input: 3-state input signal
);
status_o(0) <= s_busy_idelay_d;
s_busy <= s_busy_idelay_p or s_busy_idelay_d;
ISERDES2_Prompt : ISERDES2
generic map (
......@@ -168,10 +163,10 @@ BEGIN
)
port map (
-- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
Q1 => s_Data_o(0), -- oldest data
Q2 => s_Data_o(2),
Q3 => s_Data_o(4),
Q4 => s_Data_o(6), -- most recent data
Q1 => s_Data_o(1), -- Oldest data
Q2 => s_Data_o(3),
Q3 => s_Data_o(5),
Q4 => s_Data_o(7), -- most recent data
--SHIFTOUT => SHIFTOUTsig, -- 1-bit output Cascade output signal for master/slave I/O
VALID => open, -- 1-bit output Output status of the phase detector
BITSLIP => '0', -- 1-bit input Bitslip enable input
......@@ -194,11 +189,11 @@ BEGIN
SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
)
port map (
-- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
Q1 => s_Data_o(1), -- Oldest data
Q2 => s_Data_o(3),
Q3 => s_Data_o(5),
Q4 => s_Data_o(7), -- most recent data
-- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
Q1 => s_Data_o(0), -- oldest data
Q2 => s_Data_o(2),
Q3 => s_Data_o(4),
Q4 => s_Data_o(6), -- most recent data
--SHIFTOUT => SHIFTOUTsig, -- 1-bit output Cascade output signal for master/slave I/O
VALID => open, -- 1-bit output Output status of the phase detector
BITSLIP => '0', -- 1-bit input Bitslip enable input
......
firmware/hdl/common/eventBuffer_rtl.vhd
View file @ c0e9d64f
......@@ -54,8 +54,8 @@ ENTITY eventBuffer IS
GENERIC(
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_WRITE_COUNTER_WIDTH : positive := 13;
g_READ_COUNTER_WIDTH : positive := 14
g_WRITE_COUNTER_WIDTH : positive := 15;
g_READ_COUNTER_WIDTH : positive := 16
);
PORT(
clk_4x_logic_i : IN std_logic;
......@@ -65,8 +65,9 @@ ENTITY eventBuffer IS
ipbus_i : IN ipb_wbus;
ipbus_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic;
trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not yet used.
buffer_full_o : OUT std_logic; --! Goes high when event buffer almost full
--trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
rst_fifo_o : OUT std_logic; --! rst signal to first level fifos
buffer_full_o : OUT std_logic; --! Goes high when event buffer almost full
ipbus_o : OUT ipb_rbus;
logic_reset_i : IN std_logic -- reset buffers when high. Synch withclk_4x_logic
);
......@@ -84,10 +85,11 @@ ARCHITECTURE rtl OF eventBuffer IS
signal s_wr_data_count , s_wr_data_count_reg : std_logic_vector(g_WRITE_COUNTER_WIDTH-1 downto 0) := (others =>'0');
signal s_rd_data_count : std_logic_vector(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0');
signal s_fifo_fill_level : unsigned(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0'); -- read-counter - 2*write_count
--signal s_fifo_fill_level : unsigned(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0'); -- read-counter - 2*write_count
signal s_fifo_fill_level : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others =>'0'); -- read-counter - 2*write_count
signal s_write_strobe : std_logic := '0';
signal s_rst_fifo : std_logic := '0'; -- ! Take high to reset FIFO pointers.
signal s_rst_fifo, s_rst_fifo_ipb : std_logic := '0'; -- ! Take high to reset FIFO pointers.
signal s_fifo_prog_full : std_logic := '0'; -- ! Controlled by programmable-full flag of FIFO core
signal s_fifo_rd_en : std_logic := '0'; -- ! Take high to clock data out of FIFO
signal s_fifo_dout : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- ! Output from FIFO ( fall-through mode)
......@@ -103,7 +105,8 @@ BEGIN
--! Generate FIFO read enable
s_fifo_rd_en <= '1' when ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '0' and ipbus_i.ipb_addr(1 downto 0) = "00" else '0';
s_fifo_valid <= '1';
--! Generate IPBus ACK
ipbus_o.ipb_ack <= (ipbus_i.ipb_strobe and not s_fifo_rd_en) or (s_fifo_valid and s_fifo_rd_en);
ipbus_o.ipb_err <= '0';
......@@ -111,26 +114,28 @@ BEGIN
--! Multiplex output data.
with ipbus_i.ipb_addr(1 downto 0) select ipbus_o.ipb_rdata <=
s_fifo_dout when "00",
s_fifo_fill_level_d1 when "01",
s_fifo_fill_level when "01",
s_fifo_status_ipb when "10",
(others => '1') when others;
ipbus_write: process (ipbus_clk_i)
begin -- process ipbus_write
if rising_edge(ipbus_clk_i) then
s_rst_fifo_ipb <= '0';
if ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_addr(1 downto 0) = "10" and ipbus_i.ipb_write = '1' then
s_rst_fifo <= '1';
else
s_rst_fifo <= '0';
s_rst_fifo_ipb <= '1';
end if;
end if;
-- Register data onto IPBus clock domain to ease timing closure.
s_fifo_status_ipb <= X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty;
s_fifo_fill_level_d1 <= X"0000" & "00" & std_logic_vector(s_fifo_fill_level);
--s_fifo_fill_level_d1 <= X"0000" & "00" & std_logic_vector(s_fifo_fill_level);
s_fifo_fill_level <= X"0000" & s_rd_data_count;
end if;
end process ipbus_write;
rst_fifo_o <= s_rst_fifo_ipb;
s_rst_fifo <= s_rst_fifo_ipb or logic_reset_i;
-----------------------------------------------------------------------------
-- FIFO and fill-level calculation
-----------------------------------------------------------------------------
......@@ -173,8 +178,8 @@ BEGIN
---- multiply s_wr_data_count by 2 before subraction
--! wr_data_count and rd_data_count provide exactly the same information but in different clock domains
---- s_fifo_fill_level <= (unsigned(std_logic_vector(s_wr_data_count_reg) & "0") - unsigned(s_rd_data_count));
s_fifo_fill_level <= unsigned(s_rd_data_count);
--s_fifo_fill_level <= (unsigned(std_logic_vector(s_wr_data_count_reg) & "0") - unsigned(s_rd_data_count));
--s_fifo_fill_level <= unsigned(s_rd_data_count);
END ARCHITECTURE rtl;
firmware/hdl/common/eventFormatter_rtl.vhd
View file @ c0e9d64f
This diff is collapsed.
firmware/hdl/common/handshakes_rtl.vhd 0 → 100644
View file @ c0e9d64f
--=============================================================================
--! @file handshakes_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Santiago de Compostela, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.handshakes.rtl
--
--! @brief Handshakes between TLU and DUTs. \n
--
--
--! @author Alvaro Dosil , alvaro.dosil@usc.es
--
--! @date 12:08:30 25/06/14
--
--! @version v0.1
--
--! @details
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by: </b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
ENTITY handshakes IS
GENERIC(
g_IPBUS_WIDTH : positive := 32
);
PORT(
clk_i : IN std_logic;
Trigger_i : IN std_logic;
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
ipbus_reset_i : IN std_logic;
ipbus_o : OUT ipb_rbus;
logic_reset_i : IN std_logic;
Busy_i : IN std_logic;
AIDAhandshake_o : OUT std_logic; -- running an AIDA handshake or the old EUDET handshake
Trigger_o : OUT std_logic;
rst_or_clk_o : OUT std_logic -- CONT in schematics
);
-- Declarations
END ENTITY handshakes ;
--
ARCHITECTURE rtl OF handshakes IS
signal s_handshakeEnabled : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);
signal s_Shutter, s_T0sync : std_logic;
signal s_Trigger, s_TrigAux : std_logic := '0';
signal s_Busy, s_Busy_d1, s_Busy_d2, s_Busy_d3 : std_logic;
signal TPx3_T0syncLen : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000004"; --! T0-sync length
signal TPx3_Start_T0sync : std_logic; --! Flag to start the T0-sync signal
signal s_Veto : std_logic := '0';
signal s_WU : std_logic := '0';
signal s_NMaxPulses : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
signal s_SuDTime : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
signal s_PulseLen : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000001";
signal s_IpDTime : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000001";
signal s_RearmTime : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"10000000";
signal s_PulseDelay : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
signal s_MaxPulses : std_logic;
signal s_pulse : std_logic;
constant c_N_CTRL : positive := 13;
constant c_N_STAT : positive := 13;
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
BEGIN
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
ipbus_registers: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => c_N_CTRL,
N_STAT => c_N_STAT
)
port map(
clk => ipbus_clk_i,
reset=> '0',--ipbus_reset_i ,
ipbus_in=> ipbus_i,
ipbus_out=> ipbus_o,
d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb=> open
);
-- Synchronize registers from logic clock to ipbus.
sync_status: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_i,
data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
-- Synchronize registers from logic clock to ipbus.
sync_ctrl: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_CTRL )
port map (
clk_input_i => ipbus_clk_i,
data_i => s_control_from_ipbus,
data_o => s_sync_control_from_ipbus,
clk_output_i => clk_i);
-----------------------------------------------------------------------------
-- Logic not ready to use
-----------------------------------------------------------------------------
--Map the control registers
s_handshakeEnabled <= s_sync_control_from_ipbus(0);
s_status_to_ipbus(0) <= s_handshakeEnabled;
-- No handshake registers
s_NMaxPulses <= s_sync_control_from_ipbus(5);
s_SuDTime <= s_sync_control_from_ipbus(6);
s_PulseLen <= s_sync_control_from_ipbus(7);
s_IpDTime <= s_sync_control_from_ipbus(8);
s_RearmTime <= s_sync_control_from_ipbus(9);
s_PulseDelay <= s_sync_control_from_ipbus(10);
s_Veto <= s_sync_control_from_ipbus(11)(0);
s_WU <= s_sync_control_from_ipbus(11)(1);
s_status_to_ipbus(5) <= s_NMaxPulses;
s_status_to_ipbus(6) <= s_SuDTime;
s_status_to_ipbus(7) <= s_PulseLen;
s_status_to_ipbus(8) <= s_IpDTime;
s_status_to_ipbus(9) <= s_RearmTime;
s_status_to_ipbus(10) <= s_PulseDelay;
s_status_to_ipbus(11) <= x"0000000"& "00" & s_WU & s_Veto;
s_status_to_ipbus(12) <= x"0000000"& "000" & s_MaxPulses;
-- TPx3 registers
TPx3_Start_T0sync <= s_sync_control_from_ipbus(1)(0);
TPx3_T0syncLen <= x"00000001" when s_sync_control_from_ipbus(2)<x"000000002" else
s_sync_control_from_ipbus(2);
s_status_to_ipbus(1) <= x"0000000" & "000" & TPx3_Start_T0sync;
s_status_to_ipbus(2) <= TPx3_T0syncLen;
-----------------------------------------------------------------------------
-- Synchronization - Rewrite!!!
-----------------------------------------------------------------------------
p_trigger : process(Trigger_i, s_Trigger)
begin
if Trigger_i = '1' then
s_TrigAux <= '1';
elsif s_Trigger = '1' then
s_TrigAux <= '0';
end if;
end process p_trigger;
p_sync: process (clk_i )
begin -- process p_run_counter
if rising_edge(clk_i) then
s_Trigger <= s_TrigAux;
s_Busy_d1 <= Busy_i;
s_Busy_d2 <= s_Busy_d1;
s_Busy_d3 <= s_Busy_d2;
s_Busy <= s_Busy_d2;
end if;
end process p_sync;
-----------------------------------------------------------------------------
-- I/O
-----------------------------------------------------------------------------
Trigger_o <= s_Trigger when s_handshakeEnabled(1 downto 0) = "00" and s_Busy = '0' else
s_pulse when s_handshakeEnabled(1 downto 0) = "01" else -- No handshake
s_Shutter when s_handshakeEnabled(1 downto 0) = "10" else -- TPx3 handshake
'0';
rst_or_clk_o <= s_T0sync when s_handshakeEnabled(1 downto 0) = "10" else
'0';
AIDAhandshake_o <= not s_handshakeEnabled(3); -- s_handshakeEnabled = x"00001000" => EUDET handshake.
-- All handshakes with s_handshakeEnabled(3)='0' are AIDA handshakes
-- No Handshake (GPP)
No_handshake: entity work.GPP
GENERIC MAP(
g_IPBUS_WIDTH => g_IPBUS_WIDTH)
PORT MAP(
clk_i => clk_i,
Enable_i => not (s_Busy or s_Veto),
Reset_i => logic_reset_i,
RstPulsCnt_i => '0',
Trigger_i => s_Trigger,
NMaxPulses_i => s_NMaxPulses,
SuDTime_i => s_SuDTime,
PulsLen_i => s_PulseLen,
IpDTime_i => s_IpDTime,
RearmTime_i => s_RearmTime,
Force_PullDown_i => s_Busy or s_Veto,
WU_i => s_WU,
PulseDelay_i => s_PulseDelay,
event_number_o => open,
MaxPulses_o => s_MaxPulses,
Pulse_o => s_pulse,
Pulse_d_o => open);
-- TPx3 Handshake
TPx3_logic: entity work.TPx3Logic
PORT MAP(
clk_i => clk_i,
Start_T0sync_i => TPx3_Start_T0sync,
T0syncLen_i => TPx3_T0syncLen,
logic_reset_i => logic_reset_i,
Busy_i => s_Busy,
Veto_i => s_Veto,
Shutter_o => s_Shutter,
T0sync_o => s_T0sync
);
END ARCHITECTURE rtl;
firmware/hdl/common/ipbus_addr_decode.vhd
View file @ c0e9d64f
......@@ -43,8 +43,10 @@ package body ipbus_addr_decode is
sel := 8; -- Spill_Generator / base 00000120 / mask 0000001f
elsif std_match(addr, "-----------------------1010-----") then
sel := 9; -- Event_Formatter / base 00000140 / mask 0000001f
elsif std_match(addr, "-----------------------0000---0-") then
sel := 10; -- version / base 00000000 / mask 00000000
elsif std_match(addr, "-----------------------1011-----") then
sel := 10; -- Handshakes / base 00000160 / mask 0000001f
elsif std_match(addr, "-----------------------0000-----") then
sel := 11; -- version / base 00000000 / mask 00000000
else
sel := 99;
end if;
......
firmware/hdl/common/logic_clocks_rtl.vhd
View file @ c0e9d64f
......@@ -80,9 +80,9 @@ ENTITY logic_clocks IS
ipbus_o : OUT ipb_rbus;
strobe_16x_logic_o : OUT std_logic; -- strobes once every 4 cycles of clk_16x
strobe_4x_logic_o : OUT std_logic; -- one pulse every 4 cycles of clk_4x
extclk_p_b : OUT std_logic; -- either external clock in, or a clock being driven out
extclk_n_b : OUT std_logic;
clk_logic_o : OUT std_logic;
extclk_p_b : INOUT std_logic; -- either external clock in, or a clock being driven out
extclk_n_b : INOUT std_logic;
DUT_clk_o : OUT std_logic;
logic_clocks_locked_o : OUT std_logic;
logic_reset_o : OUT std_logic -- Goes high to reset counters etc. Sync with clk_4x_logic
);
......@@ -101,14 +101,15 @@ ARCHITECTURE rtl OF logic_clocks IS
-- signal s_clk40_copy : std_logic; -- Clock generated by DDR register to feed out of chip.
-- Eventually connect up clock control & status lines to IPBus
signal s_extclk_is_input : std_logic := '1';
--signal s_extclk_is_input : std_logic := '0';
-- signal s_extclk_is_input_buf : std_logic := '1';
signal s_clk_is_xtal : std_logic := '1';
signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '1';
-- signal s_logic_clk_rst : std_logic := '0';
signal s_locked_pll, s_locked_bufpll : std_logic;
signal s_clk : std_logic;
--signal s_extclk : std_logic;
signal s_DUT_Clk, s_DUT_Clk_o, s_DUT_ClkG : std_logic;
signal s_extclk, s_extclkG : std_logic;
-- signal s_clk_d1 , s_strobe_4x_p1 , s_strobe_4x_logic : std_logic;
signal s_clkfbout_buf , s_clkfbout : std_logic;
......@@ -132,8 +133,7 @@ ARCHITECTURE rtl OF logic_clocks IS
signal s_clock_status_ipb : std_logic_vector( ipbus_o.ipb_rdata'range ); --! Hold status of clocks
BEGIN
-----------------------------------------------------------------------------
-- IPBus write
-----------------------------------------------------------------------------
......@@ -148,7 +148,6 @@ BEGIN
case ipbus_i.ipb_addr(1 downto 0) is
when "00" =>
s_clk_is_xtal <= ipbus_i.ipb_wdata(2) ; -- select clock source
s_extclk_is_input <= ipbus_i.ipb_wdata(3); -- select direction
when "01" =>
s_logic_reset_ipb <= ipbus_i.ipb_wdata(0) ; -- write to reset
......@@ -163,7 +162,8 @@ BEGIN
s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
-- register the clock status signals onto IPBus domain.
s_clock_status_ipb <= x"0000000" & s_extclk_is_input & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
--s_clock_status_ipb <= x"0000000" & s_extclk_is_input & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
s_clock_status_ipb <= x"0000000" & '0' & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
end if;
end process ipbus_write;
......@@ -196,45 +196,71 @@ BEGIN
logic_reset_o <= s_logic_reset;
logic_clocks_locked_o <= s_locked_bufpll and s_locked_pll;
ext_clk_obuf : OBUFDS
ext_clk_obuf : IOBUFDS
generic map (
IOSTANDARD => "LVDS_25")
IOSTANDARD => "BLVDS_25")
port map (
O => extclk_p_b , -- Diff_p output (connect directly to top-level port)
OB => extclk_n_b , -- Diff_n output (connect directly to top-level port)
I => s_extclk_internal -- Buffer input
O => s_extclk, -- Buffer output
IO => extclk_p_b, -- Diff_p inout (connect directly to top-level port)
IOB => extclk_n_b, -- Diff_n inout (connect directly to top-level port)
I => s_DUT_Clk_o, -- Buffer input
T => s_clk_is_ext_buf -- 3-state enable input, high=input, low=output
);
ddr_for_extclk_output : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => s_extclk_internal, -- 1-bit output data
C0 => s_clk160_internal, -- 1-bit clock input
C1 => not s_clk160_internal, -- 1-bit clock input
Q => s_DUT_Clk_o, -- 1-bit output data
C0 => clk_logic_xtal_i, -- 1-bit clock input
C1 => not clk_logic_xtal_i, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
--When an ODDR2 primitive is used in conjunction with a 3-state output, the T control pin must
--also use an ODDR2 primitive configured in the same mode as the ODDR2 primitive used for data
--output.
ddr_for_40MHz_tristate : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => s_clk_is_ext_buf, -- 1-bit output data
C0 => clk_logic_xtal_i, -- 1-bit clock input
C1 => not clk_logic_xtal_i, --not s_clk160_internal, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
D0 => not s_clk_is_xtal, -- 1-bit data input (associated with C0)
D1 => '0', --not s_clk_is_xtal, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
s_clk <= clk_logic_xtal_i;
-- --! For now just connect input of PLL to clock from Xtal...
-- clock_mux : BUFGMUX
-- generic map (
-- CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
-- )
-- port map (
-- O => s_clk, -- 1-bit output: Clock buffer output
-- I0 => s_extclk, -- 1-bit input: Clock buffer input (S=0)
-- I1 => clk_logic_xtal_i, -- 1-bit input: Clock buffer input (S=1)
-- S => s_clk_is_xtal -- 1-bit input: Clock buffer select
-- );
--! Clock selection
clock_mux : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => s_DUT_Clk, -- 1-bit output: Clock buffer output
I0 => s_extclkG, -- 1-bit input: Clock buffer input (S=0)
I1 => clk_logic_xtal_i, -- 1-bit input: Clock buffer input (S=1)
S => s_clk_is_xtal -- 1-bit input: Clock buffer select
);
extclk_buf : BUFG
port map(
O => s_extclkG,
I => s_extclk);
-- IBUFG_inst : IBUFG
-- generic map (
......@@ -245,7 +271,6 @@ BEGIN
-- I => Reset_i -- Clock buffer input (connect directly to top-level port)
-- );
-- s_clk <= clk_logic_xtal_i;
--! Clocking primitive
-------------------------------------
......@@ -259,13 +284,13 @@ BEGIN
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 16,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2, -- 1-->2 move from 640 to 320
CLKOUT0_DIVIDE => 1, -- 1-->2 move from 640 to 320
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 4-->8 move from 160 to 80
CLKOUT1_DIVIDE => 4, -- 4-->8 move from 160 to 80
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 32, -- 16--> 32 move from 40 to 20
CLKOUT2_DIVIDE => 16, -- 16--> 32 move from 40 to 20
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 25.000,
......@@ -286,7 +311,7 @@ BEGIN
-- Input clock control
-- CLKFBIN => s_clkfbout_buf,
CLKFBIN => s_clkfbout,
CLKIN => s_clk);
CLKIN => clk_logic_xtal_i);
s_reset_pll <= Reset_i or s_logic_reset;
......@@ -303,8 +328,8 @@ BEGIN
PLLIN => s_clk640 -- 1-bit input: Clock input from PLL
);
clk_16x_logic_o <= s_clk640_internal;
clk_16x_logic_o <= s_clk640_internal;
DUT_clk_o <= s_DUT_clk;
......@@ -316,7 +341,7 @@ BEGIN
-- Can't use a clock signal as a combinatorial signal. Hence the baroque
-- method of generating a strobe. Add a mechanism to restart if the '1' gets
-- lost ....
generate_4x_strobe: process (s_clk160 , s_clk40_out)
generate_4x_strobe: process (s_clk160)-- , s_clk40_out)
begin -- process generate_4x_strobe
if rising_edge(s_clk160) then
if s_logic_reset = '1' then
......@@ -357,14 +382,14 @@ BEGIN
clk_4x_logic_o <= s_clk160_internal;
-- buffer 40MHz (1x) clock
--------------------------------------
clk40_o_buf : BUFG
port map(
O => s_clk40_internal,
I => s_clk40);
clk_logic_o <= s_clk40_out;
-- -- buffer 40MHz (1x) clock
-- --------------------------------------
-- clk40_o_buf : BUFG
-- port map(
-- O => s_clk40_internal,
-- I => s_clk40);
-- clk_logic_o <= s_clk40_out;
END ARCHITECTURE rtl;
firmware/hdl/common/triggerInputs_rtl.vhd
View file @ c0e9d64f
......@@ -84,6 +84,7 @@ use work.ipbus_reg_types.all;
USE work.fmcTLU.all;
library unisim ;
use unisim.vcomponents.all;
......@@ -94,14 +95,15 @@ ENTITY triggerInputs IS
);
PORT(
cfd_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);--! Inputs from constant-fraction discriminators
cfd_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 downto 0);--! Input from CFD
cfd_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 downto 0);--! Input from CFD
clk_4x_logic : IN std_logic; --! Rising edge active. By default = 4*40MHz = 160MHz
strobe_4x_logic_i : IN std_logic; --! Pulses high once every 4 cycles of clk_4x_logic
threshold_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! inputs from threshold comparators
threshold_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! inputs from threshold comparators
trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time ( w.r.t. logic_strobe)
trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);--! Goes high on leading edge of trigger, in sync with clk_4x_logic_i
trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
threshold_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! inputs from threshold comparators
reset_i : IN std_logic;
trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time ( w.r.t. logic_strobe)
trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);--! Goes high on leading edge of trigger, in sync with clk_4x_logic_i
trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
edge_rising_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! edge arrival time ( w.r.t. logic_strobe)
edge_falling_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! edge arrival time ( w.r.t. logic_strobe)
edge_rising_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! High when rising edge. Syncronous with clk_4x_logic_i
......@@ -126,7 +128,7 @@ ARCHITECTURE rtl OF triggerInputs IS
signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0); --! inputs from comparator
type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
signal s_deserialized_threshold_data , s_deserialized_cfd_data : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
......@@ -154,7 +156,6 @@ ARCHITECTURE rtl OF triggerInputs IS
signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
BEGIN
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
......@@ -196,9 +197,10 @@ BEGIN
-- Map the control registers...
-- Register that controls IODELAY and ISERDES reset is at address 0
s_rst_iserdes <= s_sync_control_from_ipbus(0)(0);
s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
s_counter_reset <= s_sync_control_from_ipbus(0)(1);
s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
s_status_to_ipbus(0)(0) <= s_rst_iserdes;
s_status_to_ipbus(0)(1) <= s_counter_reset;
s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
......@@ -210,6 +212,7 @@ BEGIN
-- Connect up trigger inputs to deserializers and a LUT to determine
-- arrival time
-----------------------------------------------------------------------------
trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
......@@ -226,8 +229,8 @@ BEGIN
thresholdDeserializer: entity work.dualSERDES_1to4
port map (
reset_i => s_rst_iserdes,
calibrate_i => s_calibrate_idelay,
reset_i => s_rst_iserdes,
--calibrate_i => s_calibrate_idelay,
data_i => s_threshold_discr_input(triggerInput),
fastClk_i => clk_16x_logic_i,
fabricClk_i => clk_4x_logic,
......@@ -235,7 +238,8 @@ BEGIN
data_o => s_deserialized_threshold_data(triggerInput),
status_o => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
);
--s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput)(3 downto 0) & s_deserialized_threshold_data_d(triggerInput)(7 downto 3);
s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
thresholdLUT : entity work.arrivalTimeLUT
port map (
......@@ -275,7 +279,7 @@ BEGIN
CFDDeserializer: entity work.dualSERDES_1to4
port map (
reset_i => s_rst_iserdes,
calibrate_i => s_calibrate_idelay,
--calibrate_i => s_calibrate_idelay,
data_i => s_CFD_discr_input(triggerInput),
fastClk_i => clk_16x_logic_i,
fabricClk_i => clk_4x_logic,
......@@ -283,6 +287,7 @@ BEGIN
data_o => s_deserialized_CFD_data(triggerInput),
status_o => s_status_to_ipbus(0)(13+(2*triggerInput) downto 12+(2*triggerInput))
);
--s_deserialized_CFD_data(triggerInput) <= (others=>'0');
s_deserialized_CFD_data_l(triggerInput) <= s_deserialized_CFD_data(triggerInput) & s_CFD_previous_late_bit(triggerInput);
CFDLUT : entity work.arrivalTimeLUT
......@@ -301,6 +306,7 @@ BEGIN
begin
if rising_edge(clk_4x_logic) then
s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
--s_deserialized_threshold_data_d(triggerInput) <= s_deserialized_threshold_data(triggerInput);
s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
-- Monitor output of serdes - just look at one per serdes
......@@ -325,11 +331,12 @@ BEGIN
end generate trigger_input_loop;
trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
--trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_CFD_discr_input;
--trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
--! Monitor output of deserializer
-- trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_status_to_ipbus(0)(23 downto 20);
--trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_edge_rising;
trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
END ARCHITECTURE rtl;
......
firmware/hdl/common/triggerLogic_rtl.vhd
View file @ c0e9d64f
This diff is collapsed.
firmware/hdl/test/DUTInterfaces_rtl.vhd 0 → 100644
View file @ c0e9d64f
--=============================================================================
--! @file DUTInterfaces_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:09:50 11/09/12
--
--! @version v0.1
--
--! @details
--! Address map:\n
--! 5-bit decoded
--! 0x00000000 - DUT interface mode, two bits per DUT. Up to 12 inputs XXXXXXXXBBAA99887766554433221100\n
--! - mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
--!
--
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> Indicate if the DUT works under AIDA/EUDET style\n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
library unisim;
use unisim.VComponents.all;
ENTITY DUTInterfaces IS
GENERIC(
g_NUM_DUTS : positive := 3;
g_IPBUS_WIDTH : positive := 32
);
PORT(
--busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
--busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
clk_4x_logic_i : IN std_logic;
clk_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
ipbus_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic; -- ! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_i : IN std_logic; -- goes high when trigger logic issues a trigger
--shutter_i : IN std_logic; -- goes high when trigger logic issues a shutter
ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
--reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
--reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
--trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
--trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
--shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
--shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
output_0_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_0_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_1_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_1_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_2_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_2_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_3_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_3_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
veto_o : OUT std_logic -- goes high when one or more DUT are busy
);
-- Declarations
END ENTITY DUTInterfaces ;
--
ARCHITECTURE rtl OF DUTInterfaces IS
signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0); -- OR tree
signal s_veto : std_logic;
signal s_strobe_4x_logic_d1, clk_2x_logic : std_logic;
signal s_busy_from_dut , s_clk_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs not used
signal s_EnableOutput : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
constant c_N_CTRL : positive := 2;
constant c_N_STAT : positive := 2;
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
BEGIN
-- Dummy code.
s_intermediate_busy_or(0) <= '0';
--s_busy_from_dut(g_NUM_DUTS-1 downto 0) <= (others=>'0');
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
ipbus_registers: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => c_N_CTRL,
N_STAT => c_N_STAT
)
port map(
clk => ipbus_clk_i,
reset=> '0',--ipbus_reset_i ,
ipbus_in=> ipbus_i,
ipbus_out=> ipbus_o,
d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb=> open
);
-- Synchronize registers from logic clock to ipbus.
sync_status: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_4x_logic_i,
data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
-- Synchronize registers from logic clock to ipbus.
sync_ctrl: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_CTRL )
port map (
clk_input_i => ipbus_clk_i,
data_i => s_control_from_ipbus,
data_o => s_sync_control_from_ipbus,
clk_output_i => clk_4x_logic_i);
-- Map the control registers
s_DUT_mask <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
s_EnableOutput <= s_sync_control_from_ipbus(1);
-- Map the status registers
s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
s_status_to_ipbus(1) <= s_EnableOutput;
-- purpose: Writes in the positive pin of the signals an 80MHz clock and the strobe_4x_logic_i in the negative one.
--The output signals (one signal is an lvds pair) can be enabled independently in the s_EnableOutput via IPBus.
-- type : combinational
-- inputs : clk_2x_logic , strobe_4x_logic_i, s_EnableOutput
-- outputs: output_0_p, output_0_n, output_1_p, output_1_n, output_2_p, output_2_n, output_3_p, output_3_n
duts: for dut in 1 to g_NUM_DUTS generate
output_0_p_inst : OBUF
port map (
O => output_0_p(dut-1),
I => s_EnableOutput(0) and clk_2x_logic -- Buffer input
);
output_0_n_inst : OBUF
port map (
O => output_0_n(dut-1),
I => s_EnableOutput(0) and strobe_4x_logic_i -- Buffer input
);
output_1_p_inst : OBUF
port map (
O => output_1_p(dut-1),
I => s_EnableOutput(1) and clk_2x_logic -- Buffer input
);
output_1_n_inst : OBUF
port map (
O => output_1_n(dut-1),
I => s_EnableOutput(1) and strobe_4x_logic_i -- Buffer input
);
output_2_p_inst : OBUF
port map (
O => output_2_p(dut-1),
I => s_EnableOutput(2) and clk_2x_logic -- Buffer input
);
output_2_n_inst : OBUF
port map (
O => output_2_n(dut-1),
I => s_EnableOutput(2) and strobe_4x_logic_i -- Buffer input
);
output_3_p_inst : OBUF
port map (
O => output_3_p(dut-1),
I => s_EnableOutput(3) and clk_2x_logic -- Buffer input
);
output_3_n_inst : OBUF
port map (
O => output_3_n(dut-1),
I => s_EnableOutput(3) and strobe_4x_logic_i -- Buffer input
);
s_intermediate_busy_or(dut) <= s_intermediate_busy_or(dut-1) or
(s_busy_from_dut(dut-1) and
s_DUT_mask(dut-1));
end generate duts;
s_veto <= s_intermediate_busy_or(g_NUM_DUTS);
clk_2x_logic <= s_strobe_4x_logic_d1 or strobe_4x_logic_i; --80 MHz clock
-- purpose: register for internal signals and output signals
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
-- outputs: veto_o
register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
begin -- process register_signals
if rising_edge(clk_4x_logic_i) then
veto_o <= s_veto;
s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
s_reset_or_clk_to_dut <= ( others => (s_strobe_4x_logic_d1 or strobe_4x_logic_i));
s_trigger_to_dut <= ( others => trigger_i );
--shutter_to_dut <= ( others => shutter_i );
end if;
end process register_signals;
END ARCHITECTURE rtl;
firmware/hdl/test/sp601_FMC_mTLU.ucf 0 → 100644
View file @ c0e9d64f
NET sysclk_p_i LOC = K15 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
NET sysclk_n_i LOC = K16 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
# remove for now
#NET Reset_i LOC=P4; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET I6/s_clk_is_xtal TIG;
NET leds_o<0> LOC=E13 | IOSTANDARD=LVCMOS25;
NET leds_o<1> LOC=C14 | IOSTANDARD=LVCMOS25;
NET leds_o<2> LOC=C4 | IOSTANDARD=LVCMOS25;
NET leds_o<3> LOC=A4 | IOSTANDARD=LVCMOS25;
NET dip_switch_i<0> LOC=D14;
NET dip_switch_i<1> LOC=E12;
NET dip_switch_i<2> LOC=F12;
NET dip_switch_i<3> LOC=V13;
# Ethernet PHY
TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET gmii_gtx_clk_o LOC=A9 | IOSTANDARD=LVCMOS25 | SLEW=FAST;
NET gmii_txd_o<0> LOC=F8 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<1> LOC=G8 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<2> LOC=A6 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<3> LOC=B6 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<4> LOC=E6 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<5> LOC=F7 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<6> LOC=A5 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<7> LOC=C5 | IOSTANDARD=LVCMOS25;
NET gmii_tx_en_o LOC=B8 | IOSTANDARD=LVCMOS25;
NET gmii_tx_er_o LOC=A8 | IOSTANDARD=LVCMOS25;
NET gmii_rx_clk_i LOC=L16 | IOSTANDARD=LVCMOS25 | TNM_NET= "gmii_rx_clk_i";
TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
NET gmii_rxd_i<0> LOC=M14 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<1> LOC=U18 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<2> LOC=U17 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<3> LOC=T18 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<4> LOC=T17 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<5> LOC=N16 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<6> LOC=N15 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<7> LOC=P18 | IOSTANDARD=LVCMOS25;
NET gmii_rx_dv_i LOC=N18 | IOSTANDARD=LVCMOS25;
NET gmii_rx_er_i LOC=P17 | IOSTANDARD=LVCMOS25;
NET phy_rstb_o LOC=L13 | IOSTANDARD=LVCMOS25;
# Main I2C bus
NET "I2C_SCL_B" LOC = "P11"; ## C30 on FMC
NET "I2C_SDA_B" LOC = "N10"; ## C31 on FMC
#
# I/O to devices under test
#NET "BUSY_P_I<0>" LOC = "D12"; ## "FMC_LA06_P" , C10 on FMC
#NET "BUSY_N_I<0>" LOC = "C12"; ## "FMC_LA06_N" , C11 on FMC
#NET "BUSY_P_I<1>" LOC = "U11"; ## "FMC_LA28_P" , H31 on FMC
#NET "BUSY_N_I<1>" LOC = "V11"; ## "FMC_LA28_N" , H32 on FMC
#NET "BUSY_P_I<2>" LOC = "E7"; ## "FMC_LA07_P" , H13 on FMC
#NET "BUSY_N_I<2>" LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
#NET "TRIGGERS_P_O<0>" LOC = "D8"; ## "FMC_LA10_P" , C14 on FMC
##NET "TRIGGERS_N_O<0>" LOC = "C8"; ## "FMC_LA10_N" , C15 on FMC
#NET "TRIGGERS_P_O<1>" LOC = "U15"; ## "FMC_LA32_P" , H37 on FMC
##NET "TRIGGERS_N_O<1>" LOC = "V15"; ## "FMC_LA32_N" , H38 on FMC
#NET "TRIGGERS_P_O<2>" LOC = "G11"; ## "FMC_LA09_P" , D14 on FMC
##NET "TRIGGERS_N_O<2>" LOC = "F10"; ## "FMC_LA09_N" , D15 on FMC
# Remove for now.
#NET "SHUTTERS_P_O<0>" LOC = "N7"; ## "FMC_LA20_P" , G21 on FMC
##NET "SHUTTERS_N_O<0>" LOC = "P8"; ## "FMC_LA20_N" , G22 on FMC
#NET "SHUTTERS_P_O<1>" LOC = "R10"; ## "FMC_LA18_CC_P" , C22 on FMC
##NET "SHUTTERS_N_O<1>" LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "N6"; ## "FMC_LA19_P" , H22 on FMC
##NET "SHUTTERS_N_O<2>" LOC = "P6"; ## "FMC_LA19_N" , H23 on FMC
#NET "DUT_CLK_P_I<0>" LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
#NET "DUT_CLK_N_I<0>" LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
#NET "DUT_CLK_P_I<1>" LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
#NET "DUT_CLK_N_I<1>" LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
#NET "DUT_CLK_P_I<2>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
#NET "DUT_CLK_N_I<2>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
#NET "RESET_OR_CLK_P_O<0>" LOC = "M10"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
##NET "RESET_OR_CLK_N_O<0>" LOC = "N9"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
#NET "RESET_OR_CLK_P_O<1>" LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
##NET "RESET_OR_CLK_N_O<1>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
#NET "RESET_OR_CLK_P_O<2>" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
##NET "RESET_OR_CLK_N_O<2>" LOC = "A16"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
# Trigger Inputs
# Constant-fraction-discrimiator comparator outputs
#NET "CFD_DISCR_P_I<0>" LOC = "D9"; ## "FMC_LA00_CC_P" , G6 on FMC
#NET "CFD_DISCR_N_I<0>" LOC = "C9"; ## "FMC_LA00_CC_N" , G7 on FMC
#
#NET "CFD_DISCR_P_I<1>" LOC = "B2"; ## "FMC_LA14_P" , C18 on FMC
#NET "CFD_DISCR_N_I<1>" LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
#
#NET "CFD_DISCR_P_I<2>" LOC = "B14"; ## "FMC_LA05_P" , D11 on FMC
#NET "CFD_DISCR_N_I<2>" LOC = "A14"; ## "FMC_LA05_N" , D12 on FMC
#
#NET "CFD_DISCR_P_I<3>" LOC = "B11"; ## "FMC_LA13_P" , D17 on FMC
#NET "CFD_DISCR_N_I<3>" LOC = "A11"; ## "FMC_LA13_N" , D18 on FMC
# Threshold comparator outputs
NET "THRESHOLD_DISCR_P_I<0>" LOC = "D11"; ## "FMC_LA01_CC_P" , D8 on FMC
NET "THRESHOLD_DISCR_N_I<0>" LOC = "C11"; ## "FMC_LA01_CC_N" , D9 on FMC
NET "THRESHOLD_DISCR_P_I<1>" LOC = "C13"; ## "FMC_LA03_P" , G9 on FMC
NET "THRESHOLD_DISCR_N_I<1>" LOC = "A13"; ## "FMC_LA03_N" , G10 on FMC
NET "THRESHOLD_DISCR_P_I<2>" LOC = "D6"; ## "FMC_LA12_P" , G15 on FMC
NET "THRESHOLD_DISCR_N_I<2>" LOC = "C6"; ## "FMC_LA12_N" , G16 on FMC
NET "THRESHOLD_DISCR_P_I<3>" LOC = "C7"; ## "FMC_LA16_P" , G18 on FMC
NET "THRESHOLD_DISCR_N_I<3>" LOC = "A7"; ## "FMC_LA16_N" , G19 on FMC
#NET "SPARE_P<2>" LOC = "R8"; ## "FMC_LA17_CC_P" , D20 on FMC
#NET "SPARE_N<2>" LOC = "T8"; ## "FMC_LA17_CC_N" , D21 on FMC
#NET "SPARE_P<1>" LOC = "T12"; ## "FMC_LA30_P" , H34 on FMC
#NET "SPARE_N<1>" LOC = "V12"; ## "FMC_LA30_N" , H35 on FMC
NET "EXTCLK_P_B" LOC = "C10"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "EXTCLK_N_B" LOC = "A10"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
#NET "HDMI_POWER_ENABLE1" LOC = "C15"; ## "FMC_LA02_P" , H7 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
# GPIO pins for debugging.
#NET "GPIO_HDR<0>" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm)
#NET "GPIO_HDR<1>" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm)
#NET "GPIO_HDR<2>" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm)
#NET "GPIO_HDR<3>" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm)
#NET "GPIO_HDR<4>" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm)
#NET "GPIO_HDR<5>" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm)
#NET "GPIO_HDR<6>" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm)
#NET "GPIO_HDR<7>" LOC = "P12"; ## 8 on J13 (thru series R96 20
NET "output_0_p[0]" LOC = D8;
NET "output_0_p[1]" LOC = U15;
NET "output_0_p[2]" LOC = G11;
NET "output_0_n[0]" LOC = C8;
NET "output_0_n[1]" LOC = V15;
NET "output_0_n[2]" LOC = F10;
NET "output_1_p[0]" LOC = T6;
NET "output_1_p[1]" LOC = U8;
NET "output_1_p[2]" LOC = F11;
NET "output_1_n[0]" LOC = V6;
NET "output_1_n[1]" LOC = V8;
NET "output_1_n[2]" LOC = E11;
NET "output_2_p[0]" LOC = M10;
NET "output_2_p[1]" LOC = T4;
NET "output_2_p[2]" LOC = B16;
NET "output_2_n[0]" LOC = N9;
NET "output_2_n[1]" LOC = V4;
NET "output_2_n[2]" LOC = A16;
NET "output_3_p[0]" LOC = D12;
NET "output_3_p[1]" LOC = U11;
NET "output_3_p[2]" LOC = E7;
NET "output_3_n[0]" LOC = C12;
NET "output_3_n[1]" LOC = V11;
NET "output_3_n[2]" LOC = E8;
\ No newline at end of file
firmware/hdl/test/sp601_FMC_mTLU_v1a.ucf 0 → 100644
View file @ c0e9d64f
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firmware/hdl/test/sp605_FMC_mTLU.ucf 0 → 100644
View file @ c0e9d64f
NET sysclk_p_i LOC = K21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
NET sysclk_n_i LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
#NET Reset_i LOC=F3; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET leds_o<0> LOC=D17 | IOSTANDARD=LVCMOS25;
NET leds_o<1> LOC=AB4 | IOSTANDARD=LVCMOS25;
NET leds_o<2> LOC=D21 | IOSTANDARD=LVCMOS25;
NET leds_o<3> LOC=W15 | IOSTANDARD=LVCMOS25;
NET dip_switch_i<0> LOC=C18;
NET dip_switch_i<1> LOC=Y6;
NET dip_switch_i<2> LOC=W6;
NET dip_switch_i<3> LOC=E4;
# Ethernet PHY
TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<5> LOC=Y9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
# Main I2C bus
#NET i2c_scl_io LOC=P11 | IOSTANDARD=LVCMOS25;
#NET i2c_sda_io LOC=N10 | IOSTANDARD=LVCMOS25;
NET "I2C_SDA_B" LOC = "R22"; ## C30 on FMC
NET "I2C_SCL_B" LOC = "T21"; ## C31 on FMC
#
# I/O to devices under test
#NET "BUSY_P_I<0>" LOC = "D4"; ## "FMC_LA06_P" , C10 on FMC
#NET "BUSY_N_I<0>" LOC = "D5"; ## "FMC_LA06_N" , C11 on FMC
#NET "BUSY_P_I<1>" LOC = "AA16"; ## "FMC_LA28_P" , H31 on FMC
#NET "BUSY_N_I<1>" LOC = "AB16"; ## "FMC_LA28_N" , H32 on FMC
#NET "BUSY_P_I<2>" LOC = "B2"; ## "FMC_LA07_P" , H13 on FMC
#NET "BUSY_N_I<2>" LOC = "A2"; ## "FMC_LA07_N" , H14 on FMC
#NET "TRIGGERS_P_O<0>" LOC = "H10"; ## "FMC_LA10_P" , C14 on FMC
#NET "TRIGGERS_N_O<0>" LOC = "H11"; ## "FMC_LA10_N" , C15 on FMC
#NET "TRIGGERS_P_O<1>" LOC = "W17"; ## "FMC_LA32_P" , H37 on FMC
#NET "TRIGGERS_N_O<1>" LOC = "Y18"; ## "FMC_LA32_N" , H38 on FMC
#NET "TRIGGERS_P_O<2>" LOC = "F7"; ## "FMC_LA09_P" , D14 on FMC
#NET "TRIGGERS_N_O<2>" LOC = "F8"; ## "FMC_LA09_N" , D15 on FMC
#NET "SHUTTERS_P_O<0>" LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
#NET "SHUTTERS_N_O<0>" LOC = "R8"; ## "FMC_LA20_N" , G22 on FMC
#NET "SHUTTERS_P_O<1>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
#NET "SHUTTERS_N_O<1>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
#NET "SHUTTERS_N_O<2>" LOC = "T11"; ## "FMC_LA19_N" , H23 on FMC
#NET "DUT_CLK_P_I<0>" LOC = "U16"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
#NET "DUT_CLK_N_I<0>" LOC = "V15"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
#NET "DUT_CLK_P_I<1>" LOC = "AA14"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
#NET "DUT_CLK_N_I<1>" LOC = "AB14"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
#NET "DUT_CLK_P_I<2>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
#NET "DUT_CLK_N_I<2>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
#NET "RESET_OR_CLK_P_O<0>" LOC = "Y17"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
##NET "RESET_OR_CLK_N_O<0>" LOC = "AB17"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
#NET "RESET_OR_CLK_P_O<1>" LOC = "V11"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
##NET "RESET_OR_CLK_N_O<1>" LOC = "W11"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
#NET "RESET_OR_CLK_P_O<2>" LOC = "C19"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
##NET "RESET_OR_CLK_N_O<2>" LOC = "A19"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
# Trigger inputs
# first constant-fraction-discrimiator comparator outputs
NET "CFD_DISCR_P_I<0>" LOC = "G9"; ## "FMC_LA00_CC_P" , G6 on FMC
NET "CFD_DISCR_N_I<0>" LOC = "F10"; ## "FMC_LA00_CC_N" , G7 on FMC
NET "CFD_DISCR_P_I<1>" LOC = "C17"; ## "FMC_LA14_P" , C18 on FMC
NET "CFD_DISCR_N_I<1>" LOC = "A17"; ## "FMC_LA14_N" , C19 on FMC
NET "CFD_DISCR_P_I<2>" LOC = "H13"; ## "FMC_LA12_P" , C22 on FMC
NET "CFD_DISCR_N_I<2>" LOC = "G13"; ## "FMC_LA12_N" , C23 on FMC
NET "CFD_DISCR_P_I<3>" LOC = "C5"; ## "FMC_LA16_P" , C26 on FMC
NET "CFD_DISCR_N_I<3>" LOC = "A5"; ## "FMC_LA16_N" , C27 on FMC
#NET "CFD_DISCR_P_I<2>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
#NET "CFD_DISCR_N_I<2>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "CFD_DISCR_P_I<3>" LOC = "AA10"; ## "FMC_LA27_P" , C26 on FMC
#NET "CFD_DISCR_N_I<3>" LOC = "AB10"; ## "FMC_LA27_N" , C27 on FMC
# then threshold comparator outputs
# N.B. These differ from v1 of schematics, since the original choice couldn't be routed.
NET "THRESHOLD_DISCR_P_I<0>" LOC = "F14"; ## "FMC_LA01_CC_P" , D8 on FMC
#NET "THRESHOLD_DISCR_N_I<0>" LOC = "F15"; ## "FMC_LA01_CC_N" , D9 on FMC
NET "THRESHOLD_DISCR_P_I<1>" LOC = "G16"; ## "FMC_LA13_P" , D17 on FMC
#NET "THRESHOLD_DISCR_N_I<1>" LOC = "F17"; ## "FMC_LA13_N" , D18 on FMC
NET "THRESHOLD_DISCR_P_I<2>" LOC = "D18"; ## "FMC_LA15_P" , H19 on FMC
#NET "THRESHOLD_DISCR_N_I<2>" LOC = "D19"; ## "FMC_LA15_N" , H20 on FMC
NET "THRESHOLD_DISCR_P_I<3>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
#NET "THRESHOLD_DISCR_N_I<3>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
#NET "SPARE_P<2>" LOC = "Y11"; ## "FMC_LA17_CC_P" , D20 on FMC
#NET "SPARE_N<2>" LOC = "AB11"; ## "FMC_LA17_CC_N" , D21 on FMC
#NET "SPARE_P<1>" LOC = "Y15"; ## "FMC_LA30_P" , H34 on FMC
#NET "SPARE_N<1>" LOC = "AB15"; ## "FMC_LA30_N" , H35 on FMC
NET "EXTCLK_P_B" LOC = "H12"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "EXTCLK_N_B" LOC = "G11"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
#NET "HDMI_POWER_ENABLE1" LOC = "G8"; ## "FMC_LA02_P" , H7 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA02_N" , H8 on FMC
NET "output_0_p[0]" LOC = H10;
NET "output_0_p[1]" LOC = W17;
NET "output_0_p[2]" LOC = F7;
NET "output_0_n[0]" LOC = H11;
NET "output_0_n[1]" LOC = Y18;
NET "output_0_n[2]" LOC = F8;
NET "output_1_p[0]" LOC = U16;
NET "output_1_p[1]" LOC = V11;
NET "output_1_p[2]" LOC = C19;
NET "output_1_n[0]" LOC = V15;
NET "output_1_n[1]" LOC = W11;
NET "output_1_n[2]" LOC = A19;
NET "output_2_p[0]" LOC = Y17;
NET "output_2_p[1]" LOC = AA14;
NET "output_2_p[2]" LOC = B20;
NET "output_2_n[0]" LOC = AB17;
NET "output_2_n[1]" LOC = AB14;
NET "output_2_n[2]" LOC = A20;
NET "output_3_p[0]" LOC = D4;
NET "output_3_p[1]" LOC = AA16;
NET "output_3_p[2]" LOC = B2;
NET "output_3_n[0]" LOC = D5;
NET "output_3_n[1]" LOC = AB16;
NET "output_3_n[2]" LOC = A2;
\ No newline at end of file
firmware/hdl/test/sp605_FMC_mTLU_v1a.ucf 0 → 100644
View file @ c0e9d64f
NET sysclk_p_i LOC = K21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
NET sysclk_n_i LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
#NET Reset_i LOC=F3; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET leds_o<0> LOC=D17 | IOSTANDARD=LVCMOS25;
NET leds_o<1> LOC=AB4 | IOSTANDARD=LVCMOS25;
NET leds_o<2> LOC=D21 | IOSTANDARD=LVCMOS25;
NET leds_o<3> LOC=W15 | IOSTANDARD=LVCMOS25;
NET dip_switch_i<0> LOC=C18;
NET dip_switch_i<1> LOC=Y6;
NET dip_switch_i<2> LOC=W6;
NET dip_switch_i<3> LOC=E4;
# Ethernet PHY
TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<5> LOC=Y9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
# Main I2C bus
#NET i2c_scl_io LOC=P11 | IOSTANDARD=LVCMOS25;
#NET i2c_sda_io LOC=N10 | IOSTANDARD=LVCMOS25;
NET "I2C_SDA_B" LOC = "R22"; ## C30 on FMC
NET "I2C_SCL_B" LOC = "T21"; ## C31 on FMC
#
# I/O to devices under test
#NET "BUSY_P_I<0>" LOC = "D4"; ## "FMC_LA06_P" , C10 on FMC
#NET "BUSY_N_I<0>" LOC = "D5"; ## "FMC_LA06_N" , C11 on FMC
#NET "BUSY_P_I<1>" LOC = "AA16"; ## "FMC_LA28_P" , H31 on FMC
#NET "BUSY_N_I<1>" LOC = "AB16"; ## "FMC_LA28_N" , H32 on FMC
#NET "BUSY_P_I<2>" LOC = "B2"; ## "FMC_LA07_P" , H13 on FMC
#NET "BUSY_N_I<2>" LOC = "A2"; ## "FMC_LA07_N" , H14 on FMC
#NET "TRIGGERS_P_O<0>" LOC = "H10"; ## "FMC_LA10_P" , C14 on FMC
#NET "TRIGGERS_N_O<0>" LOC = "H11"; ## "FMC_LA10_N" , C15 on FMC
#NET "TRIGGERS_P_O<1>" LOC = "W17"; ## "FMC_LA32_P" , H37 on FMC
#NET "TRIGGERS_N_O<1>" LOC = "Y18"; ## "FMC_LA32_N" , H38 on FMC
#NET "TRIGGERS_P_O<2>" LOC = "F7"; ## "FMC_LA09_P" , D14 on FMC
#NET "TRIGGERS_N_O<2>" LOC = "F8"; ## "FMC_LA09_N" , D15 on FMC
#NET "SHUTTERS_P_O<0>" LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
#NET "SHUTTERS_N_O<0>" LOC = "R8"; ## "FMC_LA20_N" , G22 on FMC
#NET "SHUTTERS_P_O<1>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
#NET "SHUTTERS_N_O<1>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
#NET "SHUTTERS_N_O<2>" LOC = "T11"; ## "FMC_LA19_N" , H23 on FMC
#NET "DUT_CLK_P_I<0>" LOC = "U16"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
#NET "DUT_CLK_N_I<0>" LOC = "V15"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
#NET "DUT_CLK_P_I<1>" LOC = "AA14"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
#NET "DUT_CLK_N_I<1>" LOC = "AB14"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
#NET "DUT_CLK_P_I<2>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
#NET "DUT_CLK_N_I<2>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
#NET "RESET_OR_CLK_P_O<0>" LOC = "Y17"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
##NET "RESET_OR_CLK_N_O<0>" LOC = "AB17"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
#NET "RESET_OR_CLK_P_O<1>" LOC = "V11"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
##NET "RESET_OR_CLK_N_O<1>" LOC = "W11"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
#NET "RESET_OR_CLK_P_O<2>" LOC = "C19"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
##NET "RESET_OR_CLK_N_O<2>" LOC = "A19"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
# Trigger inputs
# first constant-fraction-discrimiator comparator outputs
#NET "CFD_DISCR_P_I<0>" LOC = "W17"; ## "FMC_LA00_CC_P" , G6 on FMC
#NET "CFD_DISCR_N_I<0>" LOC = "Y18"; ## "FMC_LA00_CC_N" , G7 on FMC
#NET "CFD_DISCR_P_I<1>" LOC = "Y15"; ## "FMC_LA14_P" , C18 on FMC
#NET "CFD_DISCR_N_I<1>" LOC = "AB15"; ## "FMC_LA14_N" , C19 on FMC
#NET "CFD_DISCR_P_I<2>" LOC = "AA16"; ## "FMC_LA12_P" , C22 on FMC
#NET "CFD_DISCR_N_I<2>" LOC = "AB16"; ## "FMC_LA12_N" , C23 on FMC
#NET "CFD_DISCR_P_I<3>" LOC = "AA14"; ## "FMC_LA16_P" , C26 on FMC
#NET "CFD_DISCR_N_I<3>" LOC = "AB14"; ## "FMC_LA16_N" , C27 on FMC
##NET "CFD_DISCR_P_I<2>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
##NET "CFD_DISCR_N_I<2>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
##NET "CFD_DISCR_P_I<3>" LOC = "AA10"; ## "FMC_LA27_P" , C26 on FMC
##NET "CFD_DISCR_N_I<3>" LOC = "AB10"; ## "FMC_LA27_N" , C27 on FMC
# then threshold comparator outputs
# N.B. These differ from v1 of schematics, since the original choice couldn't be routed.
NET "THRESHOLD_DISCR_P_I<0>" LOC = "F14"; ## "FMC_LA01_CC_P" , D8 on FMC
#NET "THRESHOLD_DISCR_N_I<0>" LOC = "F15"; ## "FMC_LA01_CC_N" , D9 on FMC
NET "THRESHOLD_DISCR_P_I<1>" LOC = "G16"; ## "FMC_LA13_P" , D17 on FMC
#NET "THRESHOLD_DISCR_N_I<1>" LOC = "F17"; ## "FMC_LA13_N" , D18 on FMC
NET "THRESHOLD_DISCR_P_I<2>" LOC = "D18"; ## "FMC_LA15_P" , H19 on FMC
#NET "THRESHOLD_DISCR_N_I<2>" LOC = "D19"; ## "FMC_LA15_N" , H20 on FMC
NET "THRESHOLD_DISCR_P_I<3>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
#NET "THRESHOLD_DISCR_N_I<3>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
#NET "SPARE_P<2>" LOC = "Y11"; ## "FMC_LA17_CC_P" , D20 on FMC
#NET "SPARE_N<2>" LOC = "AB11"; ## "FMC_LA17_CC_N" , D21 on FMC
#NET "SPARE_P<1>" LOC = "Y15"; ## "FMC_LA30_P" , H34 on FMC
#NET "SPARE_N<1>" LOC = "AB15"; ## "FMC_LA30_N" , H35 on FMC
NET "EXTCLK_P_B" LOC = "H12"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "EXTCLK_N_B" LOC = "G11"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
#NET "HDMI_POWER_ENABLE1" LOC = "G8"; ## "FMC_LA02_P" , H7 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA02_N" , H8 on FMC
NET "output_0_p[0]" LOC = R9;
NET "output_0_p[1]" LOC = B18;
NET "output_0_p[2]" LOC = C5;
NET "output_0_n[0]" LOC = R8;
NET "output_0_n[1]" LOC = A18;
NET "output_0_n[2]" LOC = A5;
NET "output_1_p[0]" LOC = AA10;
NET "output_1_p[1]" LOC = G8;
NET "output_1_p[2]" LOC = V11;
NET "output_1_n[0]" LOC = AB10;
NET "output_1_n[1]" LOC = F9;
NET "output_1_n[2]" LOC = W11;
NET "output_2_p[0]" LOC = V7;
NET "output_2_p[1]" LOC = T12;
NET "output_2_p[2]" LOC = B2;
NET "output_2_n[0]" LOC = W8;
NET "output_2_n[1]" LOC = U12;
NET "output_2_n[2]" LOC = A2;
NET "output_3_p[0]" LOC = R11;
NET "output_3_p[1]" LOC = C17;
NET "output_3_p[2]" LOC = H13;
NET "output_3_n[0]" LOC = T11;
NET "output_3_n[1]" LOC = A17;
NET "output_3_n[2]" LOC = G13;
\ No newline at end of file
firmware/hdl/test/top_extphy_struct.vhd 0 → 100644
View file @ c0e9d64f
This diff is collapsed.
firmware/scripts/aida_mini_tlu_addr_map.txt
View file @ c0e9d64f
......@@ -2,28 +2,34 @@
*-------------------------------------------------------------
FirmwareId 0x00000000 0xffffffff 1 0
* DUT interfaces base = 0x020
DUTMaskW 0x00000020 0xffffffff 0 1
DUTMaskR 0x00000021 0xffffffff 1 0
*
* trigger inputs = 0x040
SerdesRst 0x00000040 0xffffffff 1 1
ThrCount0 0x00000041 0xffffffff 1 0
ThrCount1 0x00000042 0xffffffff 1 0
ThrCount2 0x00000043 0xffffffff 1 0
ThrCount3 0x00000044 0xffffffff 1 0
SerdesRstW 0x00000040 0xffffffff 0 1
SerdesRstR 0x00000048 0xffffffff 1 0
ThrCount0R 0x00000049 0xffffffff 1 0
ThrCount1R 0x0000004a 0xffffffff 1 0
ThrCount2R 0x0000004b 0xffffffff 1 0
ThrCount3R 0x0000004c 0xffffffff 1 0
*
* trigger logic = 0x060
PostVetoTriggers 0x00000060 0xffffffff 1 0
PreVetoTriggers 0x00000061 0xffffffff 1 0
InternalTriggerInterval 0x00000062 0xffffffff 1 1
TriggerMask 0x00000063 0xffffffff 1 1
TriggerVeto 0x00000064 0xffffffff 1 1
ExternalTriggerVeto 0x00000065 0xffffffff 1 0
ResetCounters 0x00000066 0xffffffff 0 1
* trigger logic = 0x060 **Note the different read and write directions
InternalTriggerIntervalW 0x00000062 0xffffffff 1 1
TriggerMaskW 0x00000063 0xffffffff 1 1
TriggerVetoW 0x00000064 0xffffffff 1 1
ResetCountersW 0x00000066 0xffffffff 0 1
PostVetoTriggersR 0x00000068 0xffffffff 1 0
PreVetoTriggersR 0x00000069 0xffffffff 1 0
InternalTriggerIntervalR 0x0000006a 0xffffffff 1 1
TriggerMaskR 0x0000006b 0xffffffff 1 1
TriggerVetoR 0x0000006c 0xffffffff 1 1
ExternalTriggerVetoR 0x0000006d 0xffffffff 1 0
*
* event buffer = 0x080
EventFifoData 0x00000080 0xffffffff 1 0
EventFifoFillLevel 0x00000081 0xffffffff 1 0
EventFifoCSR 0x00000082 0xffffffff 1 1
EventFifoFillLevelFlags 0x00000083 0xffffffff 1 0
EventFifoFillLevelFlags 0x00000082 0xffffffff 1 0
*
* logic clocks = 0x0A0
LogicClocksCSR 0x000000A0 0xffffffff 1 1
......@@ -70,3 +76,13 @@ SpillRearmDeadTime 0x00000127 0xffffffff 1 1
*
* Event formatter = 0x140
Enable_Record_Data 0x00000140 0xffffffff 1 1
*
* Handshakes = 0x160
HandshakeTypeW 0x00000160 0xffffffff 0 1
HandshakeConfW 0x00000161 0xffffffff 0 1
TPx3_T0SyncLenW 0x00000162 0xffffffff 0 1
HandshakeTypeR 0x00000168 0xffffffff 1 0
HandshakeConfR 0x00000169 0xffffffff 1 0
TPx3_T0SyncLenR 0x0000016a 0xffffffff 1 0
TPx3_ShDTimeLenR 0x0000016b 0xffffffff 1 0
firmware/scripts/aida_mini_tlu_addr_map.txt~
View file @ c0e9d64f
......@@ -2,29 +2,47 @@
*-------------------------------------------------------------
FirmwareId 0x00000000 0xffffffff 1 0
* DUT interfaces base = 0x020
DUTMaskW 0x00000020 0xffffffff 0 1
DUTMaskR 0x00000020 0xffffffff 1 0
*
* trigger inputs = 0x040
SerdesRst 0x00000040 0xffffffff 0 1
SerdesRstW 0x00000040 0xffffffff 0 1
SerdesRstR 0x00000048 0xffffffff 1 0
ThrCount0R 0x00000049 0xffffffff 1 0
ThrCount1R 0x0000004a 0xffffffff 1 0
ThrCount2R 0x0000004b 0xffffffff 1 0
ThrCount3R 0x0000004c 0xffffffff 1 0
*
* trigger logic = 0x060
PostVetoTriggers 0x00000060 0xffffffff 1 0
PreVetoTriggers 0x00000061 0xffffffff 1 0
InternalTriggerInterval 0x00000062 0xffffffff 1 1
TriggerMask 0x00000063 0xffffffff 1 1
TriggerVeto 0x00000064 0xffffffff 1 1
ExternalTriggerVeto 0x00000065 0xffffffff 1 0
ResetCounters 0x00000066 0xffffffff 0 1
* trigger logic = 0x060 **Note the different read and write directions
InternalTriggerIntervalW 0x00000062 0xffffffff 1 1
TriggerMaskW 0x00000063 0xffffffff 1 1
TriggerVetoW 0x00000064 0xffffffff 1 1
ResetCountersW 0x00000066 0xffffffff 0 1
PostVetoTriggersR 0x00000068 0xffffffff 1 0
PreVetoTriggersR 0x00000069 0xffffffff 1 0
InternalTriggerIntervalR 0x0000006a 0xffffffff 1 1
TriggerMaskR 0x0000006b 0xffffffff 1 1
TriggerVetoR 0x0000006c 0xffffffff 1 1
ExternalTriggerVetoR 0x0000006d 0xffffffff 1 0
*
* event buffer = 0x080
EventFifoData 0x00000080 0xffffffff 1 0
EventFifoFillLevel 0x00000081 0xffffffff 1 0
EventFifoCSR 0x00000082 0xffffffff 1 1
EventFifoFillLevelFlags 0x00000083 0xffffffff 1 0
EventFifoFillLevelFlags 0x00000082 0xffffffff 1 0
*
* logic clocks = 0x0A0
LogicClocksCSR 0x000000A0 0xffffffff 1 1
LogicRst 0x000000A1 0xffffffff 0 1
*
* I2C = 0x0C0
i2c_pre_lo 0x000000C0 0x000000ff 1 1
i2c_pre_hi 0x000000C1 0x000000ff 1 1
i2c_ctrl 0x000000C2 0x000000ff 1 1
i2c_tx 0x000000C3 0x000000ff 0 1
i2c_rx 0x000000C3 0x000000ff 1 0
i2c_cmd 0x000000C4 0x000000ff 0 1
i2c_status 0x000000C4 0x000000ff 1 0
*
* trigger generator = 0x0E0
TriggerLength 0x000000E0 0xffffffff 1 1
......@@ -58,3 +76,13 @@ SpillRearmDeadTime 0x00000127 0xffffffff 1 1
*
* Event formatter = 0x140
Enable_Record_Data 0x00000140 0xffffffff 1 1
*
* Handshakes = 0x160
HandshakeTypeW 0x00000160 0xffffffff 0 1
HandshakeConfW 0x00000161 0xffffffff 0 1
TPx3_T0SyncLenW 0x00000162 0xffffffff 0 1
HandshakeTypeR 0x00000168 0xffffffff 1 0
HandshakeConfR 0x00000169 0xffffffff 1 0
TPx3_T0SyncLenR 0x0000016a 0xffffffff 1 0
TPx3_ShDTimeLenR 0x0000016b 0xffffffff 1 0
firmware/scripts/fmc_tlu_addr_table
View file @ c0e9d64f
......@@ -11,5 +11,5 @@
7 Shutter_Generator 0x100 5
8 Spill_Generator 0x120 5
9 Event_Formatter 0x140 5
9 version 0x000 0
10 emac_hostbus 0x002 1
10 Handshakes 0x160 5
11 version 0x000 0
firmware/scripts/test_aida_tlu.py
View file @ c0e9d64f
......@@ -4,52 +4,239 @@
# David Cussans, December 2012
#
# Modified by Alvaro Dosil, January 2013
from PyChipsUser import *
from FmcTluI2c import *
from ROOT import *
import sys
import time
def mean(TS):
val=0
for i in range(1,len(TS)):
val+=TS[i]-TS[i-1]
return val/(len(TS)-1)
bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 1
board = ChipsBusUdp(bAddrTab,"192.168.200.16",50001)
# Check the bus for I2C devices
boardi2c = FmcTluI2c(board)
firmwareID=board.read("FirmwareId")
firmwareID=board.read("FirmwareId")
print "Firmware = " , hex(firmwareID)
board.write("TriggerMask", 0)
trigpatt = board.read("TriggerMask")
print "Trigger pattern set to ", trigpatt
print "Scanning I2C bus:"
scanResults = boardi2c.i2c_scan()
print scanResults
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
resetClocks = 0
resetSerdes = 1
# set DACs to -200mV
print "Setting all threshold DAC to -200mV "
boardi2c.set_threshold_voltage(7, 1.0)
clockStatus = board.read("LogicClocksCSR")
print "Clock status = " , hex(clockStatus)
if resetClocks:
print "Resetting clocks"
board.write("LogicRst", 1 )
clockStatus = board.read("LogicClocksCSR")
print "Clock status after reset = " , hex(clockStatus)
inputStatus = board.read("SerdesRstR")
print "Input status = " , hex(inputStatus)
if resetSerdes:
board.write("SerdesRstW", 0x00000003 )
inputStatus = board.read("SerdesRstR")
print "Input status during reset = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000000 )
inputStatus = board.read("SerdesRstR")
print "Input status after reset = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000004 )
inputStatus = board.read("SerdesRstR")
print "Input status during calibration = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000000 )
inputStatus = board.read("SerdesRstR")
print "Input status after calibration = " , hex(inputStatus)
# Look at status of input IODELAYs
numLoops = 5
for iLoop in range(0,numLoops):
inputStatus = board.read("SerdesRstR")
print "Input status = " , hex(inputStatus)
count0 = board.read("ThrCount0R")
print " Count 0 = " , count0
count1 = board.read("ThrCount1R")
print " Count 1 = " , count1
count2 = board.read("ThrCount2R")
print " Count 2 = " , count2
count3 = board.read("ThrCount3R")
print " Count 3 = " , count3
time.sleep(1.0)
board.write("InternalTriggerIntervalW",0)
print "Enabling DUT 1"
board.write("DUTMaskW",0)
board.write("TriggerMaskW",0x0)
board.write("TriggerVetoW",0)
print "Trigger inputs enabled: ", board.read("TriggerMaskR")
print "Reseting FIFO"
board.write("EventFifoCSR",0x2)
print "Enabling to record data"
board.write("Enable_Record_Data",1)
print "Enabling handshake: No-handshake"
board.write("HandshakeTypeW",1)
TriggerInterval = 160
board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
pretrig = board.read("PreVetoTriggers")
print "Pre veto triggers = ", pretrig
#sys.exit(0)
fifofill = board.read("EventFifoFillLevel")
print "fifo fill level = ", fifofill
f=open("data/data.dat",'w')
board.write("InternalTriggerInterval", 0x10000000)
trigint = board.read("InternalTriggerInterval")
print "Trigger interval set to " , trigint
n=600000 #number of measurements
data={"EvtType":[],"InputTrig":[],"CoarseTS":[],"FineTS0":[],"FineTS1":[],"FineTS2":[],"FineTS3":[],"EvtNumber":[], "TS":[]}
read=range(4)
trigger_old=0
i=0
while i<n:
PostVetoTrig = board.read("PostVetoTriggersR")
if PostVetoTrig!=trigger_old:
f.write("word "+str(hex(i))+"\n")
for j in range(4):
read[j] = board.read("EventFifoData")
f.write(str(hex(read[j]))+"\n")
trigger_old = PostVetoTrig
else: continue
data["EvtType"].append(read[0] >> 28)
data["InputTrig"].append((read[0]&0xfff0000)>>16)
data["CoarseTS"].append(((read[0]&0xffff)<<32) | read[1])
data["FineTS0"].append(read[2]>>24)
data["FineTS1"].append(read[2]>>16 & 0xff)
data["FineTS2"].append(read[2]>>8 & 0xff)
data["FineTS3"].append(read[2] & 0xff)
data["EvtNumber"].append(read[3])
#if read[3]&0x84000000!=0: sys.exit(0)
if data["InputTrig"][i]==0x800:
data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS0"][i]>>3)*6.25+(data["FineTS0"][i]&0x7)*0.781)
elif data["InputTrig"][i]==0x400:
data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS1"][i]>>3)*6.25+(data["FineTS1"][i]&0x7)*0.781)
elif data["InputTrig"][i]==0x200:
data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS2"][i]>>3)*6.25+(data["FineTS2"][i]&0x7)*0.781)
elif data["InputTrig"][i]==0x100:
data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS3"][i]>>3)*6.25+(data["FineTS3"][i]&0x7)*0.781)
else:
data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS0"][i]>>3)*6.25+(data["FineTS0"][i]&0x7)*0.781)
#print data["CoarseTS"][i], (data["FineTS0"][i]&0x18)>>3
#hFineTS.Fill(data["FineTS0"][i]&0x7)
#if i!=0:
# print i, data["TS"][i]-data["TS"][i-1], data["EvtNumber"][i]
#hTS.Fill(data["TS"][i]-data["TS"][i-1])
if TriggerInterval==0 and data["EvtType"][i]==0:
print "Error!!! internal trigger detected!"
if TriggerInterval!=0 and data["EvtType"][i]!=0:
print "Error!!! external trigger detected!",
print hex(data["InputTrig"][i]), "EvtNumber:",data["EvtNumber"][i]
#time.sleep(.05)
#if i%100000==0: board.write("EventFifoCSR",0x2)
i+=1
f.close()
time.sleep(1.0)
pretrig = board.read("PreVetoTriggers")
print "Pre veto triggers = ", pretrig
meanVal=0
if len(data["TS"])<500:
meanVal=mean(data["TS"])
else:
meanVal=mean(data["TS"][0:500])
print meanVal
plotWidth=100
board.write("LogicRst",1)
print "reset counters"
pretrig = board.read("PreVetoTriggers")
print "Pre veto triggers = ", pretrig
hTS = TH1D("hTS", "hTS", int(plotWidth/0.78), meanVal-plotWidth/2., meanVal+plotWidth/2.)
hFineTS0 = TH1D("hFineTS0", "hFineTS0", 8, 0, 8)
hFineTS1 = TH1D("hFineTS1", "hFineTS1", 8, 0, 8)
hFineTS2 = TH1D("hFineTS2", "hFineTS2", 8, 0, 8)
hFineTS3 = TH1D("hFineTS3", "hFineTS3", 8, 0, 8)
h6TS0 = TH1D("h6TS3","h6TS0",4,0,4)
h6TS1 = TH1D("h6TS3","h6TS1",4,0,4)
h6TS2 = TH1D("h6TS3","h6TS2",4,0,4)
h6TS3 = TH1D("h6TS3","h6TS3",4,0,4)
hEvtNumber = TH1D("hEvtNumber", "hEvtNumber", 11, -1, 10)
print "Buffer Status = ", hex(board.read("EventFifoFillLevelFlags"))
board.write("EventFifoCSR",1)
print "reset FIFO"
print "Buffer Status = ", hex(board.read("EventFifoFillLevelFlags"))
hTS.GetXaxis().SetTitle("#Delta Time stamp [ns]")
hTS.GetYaxis().SetTitle("#events")
hEvtNumber.GetYaxis().SetTitle("#events")
posttrig = board.read("PostVetoTriggers")
print "Post veto triggers = ", posttrig
for i in range(len(data["TS"])):
if i!=0:
interval=data["TS"][i]-data["TS"][i-1]
hTS.Fill(interval)
hEvtNumber.Fill(data["EvtNumber"][i]-data["EvtNumber"][i-1])
hFineTS0.Fill(data["FineTS0"][i]&0x7)
hFineTS1.Fill(data["FineTS1"][i]&0x7)
hFineTS2.Fill(data["FineTS2"][i]&0x7)
hFineTS3.Fill(data["FineTS3"][i]&0x7)
h6TS0.Fill(data["FineTS0"][i]>>3)
h6TS1.Fill(data["FineTS1"][i]>>3)
h6TS2.Fill(data["FineTS2"][i]>>3)
h6TS3.Fill(data["FineTS3"][i]>>3)
fifofill = board.read("EventFifoFillLevel")
print "fifo fill level = ", fifofill
cPlots = TCanvas("cPlots","cPlots",900,600)
cPlots.Divide(2)
cPlots.cd(1)
hTS.Draw()
cPlots.cd(2)
hEvtNumber.Draw()
c6TS = TCanvas("c6TS", "c6TS", 1000,900)
c6TS.Divide(2,2)
c6TS.cd(1)
h6TS0.Draw()
c6TS.cd(2)
h6TS1.Draw()
c6TS.cd(3)
h6TS2.Draw()
c6TS.cd(4)
h6TS3.Draw()
cFineTS = TCanvas("cFineTS","cFineTS",1000,900)
cFineTS.Divide(2,2)
cFineTS.cd(1)
hFineTS0.Draw()
cFineTS.cd(2)
hFineTS1.Draw()
cFineTS.cd(3)
hFineTS2.Draw()
cFineTS.cd(4)
hFineTS3.Draw()
firmware/scripts/test_aida_tlu_trig_counter.py
View file @ c0e9d64f
......@@ -76,16 +76,16 @@ for iLoop in range(0,numLoops):
inputStatus = board.read("SerdesRst")
print "Input status = " , hex(inputStatus)
count0 = board.read("ThrCount0")
count0 = board.read("ThrCount0R")
print " Count 0 = " , count0
count1 = board.read("ThrCount1")
count1 = board.read("ThrCount1R")
print " Count 1 = " , count1
count2 = board.read("ThrCount2")
count2 = board.read("ThrCount2R")
print " Count 2 = " , count2
count3 = board.read("ThrCount3")
count3 = board.read("ThrCount3R")
print " Count 3 = " , count3
time.sleep(1.0)
......
firmware/ucf/sp601_FMC_mTLU.ucf
View file @ c0e9d64f
......@@ -87,19 +87,20 @@ NET "TRIGGERS_P_O<2>" LOC = "G11"; ## "FMC_LA09_P" , D14 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "N6"; ## "FMC_LA19_P" , H22 on FMC
##NET "SHUTTERS_N_O<2>" LOC = "P6"; ## "FMC_LA19_N" , H23 on FMC
NET "DUT_CLK_P_I<0>" LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
NET "DUT_CLK_N_I<0>" LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
NET "DUT_CLK_P_I<1>" LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
NET "DUT_CLK_N_I<1>" LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
NET "DUT_CLK_P_I<2>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
NET "DUT_CLK_N_I<2>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
NET "DUT_CLK_P_I<0>" LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC , DUT_CLK_P_I<0>
NET "DUT_CLK_N_I<0>" LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N_I<0>
NET "DUT_CLK_P_I<1>" LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC , DUT_CLK_P_I<0>
#NET "DUT_CLK_P_I<1>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC , DUT_CLK_N_I<0>
NET "DUT_CLK_P_I<2>" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC , DUT_CLK_P_I<0>
#NET "DUT_CLK_P_I<2>" LOC = "A16"; ## "FMC_LA04_N" , H11 on FMC , DUT_CLK_N_I<0>
NET "RESET_OR_CLK_P_O<0>" LOC = "M10"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
#NET "RESET_OR_CLK_N_O<0>" LOC = "N9"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
NET "RESET_OR_CLK_P_O<1>" LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
#NET "RESET_OR_CLK_N_O<1>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
NET "RESET_OR_CLK_P_O<2>" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
#NET "RESET_OR_CLK_N_O<2>" LOC = "A16"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
NET "RESET_OR_CLK_P_O<1>" LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
NET "RESET_OR_CLK_N_O<1>" LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
NET "RESET_OR_CLK_P_O<2>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
NET "RESET_OR_CLK_N_O<2>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
# Trigger Inputs
......
firmware/ucf/sp601_FMC_mTLU_v1a.ucf
View file @ c0e9d64f
This diff is collapsed.
firmware/ucf/sp605_FMC_mTLU.ucf
View file @ c0e9d64f
......@@ -3,7 +3,7 @@ NET sysclk_n_i LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
NET Reset_i LOC=F3; ## Global Reset
#NET Reset_i LOC=F3; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
......@@ -80,11 +80,11 @@ NET "TRIGGERS_P_O<1>" LOC = "W17"; ## "FMC_LA32_P" , H37 on FMC
NET "TRIGGERS_P_O<2>" LOC = "F7"; ## "FMC_LA09_P" , D14 on FMC
#NET "TRIGGERS_N_O<2>" LOC = "F8"; ## "FMC_LA09_N" , D15 on FMC
NET "SHUTTERS_P_O<0>" LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
#NET "SHUTTERS_P_O<0>" LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
#NET "SHUTTERS_N_O<0>" LOC = "R8"; ## "FMC_LA20_N" , G22 on FMC
NET "SHUTTERS_P_O<1>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
#NET "SHUTTERS_P_O<1>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
#NET "SHUTTERS_N_O<1>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
NET "SHUTTERS_P_O<2>" LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
#NET "SHUTTERS_N_O<2>" LOC = "T11"; ## "FMC_LA19_N" , H23 on FMC
NET "DUT_CLK_P_I<0>" LOC = "U16"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
......
firmware/ucf/sp605_FMC_mTLU_v1a.ucf 0 → 100644
View file @ c0e9d64f
This diff is collapsed.
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