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AIDA-2020 TLU
Commit c981c4f7 authored by Alvaro Dosil's avatar Alvaro Dosil
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- TPx3 handshake created. \n - Bidirectional clock port created configurable by… 

- TPx3 handshake created. \n - Bidirectional clock port created configurable by IPBus. But the external clock input properties still not working properly
parent 606a0b76
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firmware/hdl/common/DUTInterfaces_rtl.vhd
View file @ c981c4f7
......@@ -62,22 +62,21 @@ ENTITY DUTInterfaces IS
busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
clk_4x_logic_i : IN std_logic;
clk_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
ipbus_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic; -- ! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_i : IN std_logic; -- goes high when trigger logic issues a trigger
--shutter_i : IN std_logic; -- goes high when trigger logic issues a shutter
ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
clk_to_dut_i : IN std_logic ; -- ! clock to DUT
reset_or_clk_to_dut_i : IN std_logic;
ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
--shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
--shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
veto_o : OUT std_logic -- goes high when one or more DUT are busy
);
......@@ -91,22 +90,16 @@ ARCHITECTURE rtl OF DUTInterfaces IS
signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0); -- OR tree
signal s_veto : std_logic;
signal s_strobe_4x_logic_d1 : std_logic;
signal s_busy_from_dut , s_clk_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal s_clk_to_DUT , s_busy_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0);
signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs not used
constant c_N_CTRL : positive := 1;
constant c_N_STAT : positive := 1;
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
BEGIN
-- -----------------------------------------------------------------------------
-- -- IPBus. Dummy for now.
-- -----------------------------------------------------------------------------
-- ipbus_o.ipb_err <= '0';
-- ipbus_o.ipb_ack <= ipbus_i.ipb_strobe;
-- ipbus_o.ipb_rdata <= ( others => '1');
-- Dummy code.
s_intermediate_busy_or(0) <= '0';
--s_busy_from_dut(g_NUM_DUTS-1 downto 0) <= (others=>'0');
......@@ -168,6 +161,16 @@ BEGIN
I => busy_from_dut_p_i(dut-1), -- Diff_p buffer input (connect directly to top-level port)
IB => busy_from_dut_n_i(dut-1) -- Diff_n buffer input (connect directly to top-level port)
);
clk_to_DUT_OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => clk_to_dut_p_o(dut-1), -- Diff_p output (connect directly to top-level port)
OB => clk_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
I => s_clk_to_dut(dut-1) -- Buffer output
);
trig_OBUFDS_inst : OBUFDS
generic map (
......@@ -184,13 +187,30 @@ BEGIN
port map (
O => reset_or_clk_to_dut_p_o(dut-1), -- Diff_p output (connect directly to top-level port)
OB => reset_or_clk_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
I => s_reset_or_clk_to_dut(dut-1) and s_DUT_mask(dut-1) -- Buffer input
I => reset_or_clk_to_dut_i --s_reset_or_clk_to_dut(dut-1) and s_DUT_mask(dut-1) -- Buffer input
);
s_intermediate_busy_or(dut) <= s_intermediate_busy_or(dut-1) or
(s_busy_from_dut(dut-1) and
s_DUT_mask(dut-1));
ddr_for_clk_output : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => s_clk_to_dut(dut-1), -- 1-bit output data
C0 => clk_to_dut_i, -- 1-bit clock input
C1 => not clk_to_dut_i, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate duts;
s_veto <= s_intermediate_busy_or(g_NUM_DUTS);
......@@ -204,12 +224,11 @@ BEGIN
if rising_edge(clk_4x_logic_i) then
veto_o <= s_veto;
s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
s_reset_or_clk_to_dut <= ( others => (s_strobe_4x_logic_d1 or strobe_4x_logic_i));
--s_reset_or_clk_to_dut <= ( others => (s_strobe_4x_logic_d1 or strobe_4x_logic_i));
s_trigger_to_dut <= ( others => trigger_i );
--shutter_to_dut <= ( others => shutter_i );
end if;
end process register_signals;
END ARCHITECTURE rtl;
firmware/hdl/common/TPx3Logic_rtl.vhd 0 → 100644
View file @ c981c4f7
--=============================================================================
--! @file TPx3Logic_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Santiago de Compostela, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.TPx3Logic.rtl
--
--! @brief Produces shutters \n
--! IPBus address map:\n
--! 0x00000000 RO - Number of shutters issued since last reset.\n
--! 0x00000001 RO - Number of possible shutters since last reset (i.e. pre-veto triggers)\n
--! 0x00000010 RW - Interval between internal triggers in ticks of logic_strobe_i\n
--! 0x00000011 RW - shutter mask ( 1 bit per input )\n
--! 0x00000100 RW - bit-0 - internal shutter veto. Set to halt vetos.\n
--! 0x00000101 RO - state of external veto
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 16:06:19 11/09/12
--
--! @version v0.1
--
--! @details
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! Move all IPBus stuff into ipbus_syncreg_v , which also handles clock domain
--! crossing. 20/Feb/2014 , David Cussans
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
ENTITY TPx3Logic IS
GENERIC(
g_IPBUS_WIDTH : positive := 32
);
PORT(
clk_i : IN std_logic; -- ! Rising edge active
T0syncAut_i : IN std_logic;
T0syncFlag_i : IN std_logic;
T0syncLen_i : IN std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
ShDTLen_i : IN std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
logic_reset_i : IN std_logic; -- active high. Synchronous with clk_4x_logic
Busy_i : IN std_logic;
Shutter_o : OUT std_logic;
T0sync_o : OUT std_logic
);
-- Declarations
END ENTITY TPx3Logic ;
--
ARCHITECTURE rtl OF TPx3Logic IS
type state_values is (st0, st1, st2, st3, st4, st5);
signal pres_state, next_state: state_values;
signal s_Enable : std_logic := '0';
signal s_Shutter, s_T0sync : std_logic := '0';
--signal T0syncTime, ShDTime : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0); -- Result from counters
signal T0syncFlag, T0syncAut : std_logic := '1'; --T0 sync flag and T0sync authomatic/manual mode
signal Rst_T0sync, T0syncT : std_logic; --Load signal and flag for the T0sync
signal Rst_ShDT, ShDT : std_logic; --Load signal and flag for the interval between T0sync and Shutter
BEGIN
-----------------------------------------------------------------------------
-- Counters
-----------------------------------------------------------------------------
--T0sync counter
c_T0sync: entity work.CounterDown
generic map(
MAX_WIDTH => g_IPBUS_WIDTH
)
port map(
Clk => clk_i,
Reset => '0',
Load => Rst_T0sync,
InitVal => std_logic_vector(unsigned(T0syncLen_i)-1),
Count => open,
Q => T0syncT
);
--Start up dead time counter
c_STDT: entity work.CounterDown
generic map(
MAX_WIDTH => g_IPBUS_WIDTH
)
port map(
Clk => clk_i,
Reset => '0',
Load => Rst_ShDT,
InitVal => std_logic_vector(unsigned(ShDTLen_i)-1),
Count => open,
Q => ShDT
);
-- --T0sync counter
-- c_T0sync: entity work.counterWithReset
-- GENERIC MAP(
-- g_OUTPUT_REGISTERS => 1 --! Number of output registers. Minumum =1. Aids timing closure.
-- )
-- PORT MAP(
-- clock_i => clk_i, --! rising edge active clock
-- reset_i => Rst_T0sync, --! Active high. syncronous with rising clk
-- enable_i => '1', --! counts when enable=1
-- result_o => T0syncTime --! Unsigned integer output
-- );
-- T0syncT <= '1' when T0syncTime>=std_logic_vector(unsigned(T0syncLen_i)-1) else
-- '0';
-- --Start up dead time counter
-- c_STDT: entity work.counterWithReset
-- GENERIC MAP(
-- g_OUTPUT_REGISTERS => 1 --! Number of output registers. Minumum =1. Aids timing closure.
-- )
-- PORT MAP(
-- clock_i => clk_i, --! rising edge active clock
-- reset_i => Rst_ShDT, --! Active high. syncronous with rising clk
-- enable_i => '1', --! counts when enable=1
-- result_o => ShDTime --! Unsigned integer output
-- );
-- ShDT <= '1' when ShDTime=std_logic_vector(unsigned(ShDTLen_i)-1) else
-- '0';
-----------------------------------------------------------------------------
-- FSM register
-----------------------------------------------------------------------------
statereg: process(clk_i, s_Enable)
begin
if s_Enable = '0' then
pres_state <= st0; --Move to the "initial" state
elsif rising_edge(clk_i) then
pres_state <= next_state; --Move to the next state
end if;
end process statereg;
-----------------------------------------------------------------------------
-- FSM combinational block
-----------------------------------------------------------------------------
fsm: process(pres_state, s_Enable, T0syncT, shDT)
begin
next_state<=pres_state;
--To avoid latches we write the default values
s_Shutter<='0';
s_T0sync <='0';
Rst_T0sync <= '1';
Rst_ShDT <='1';
case pres_state is
when st0=>
if s_Enable = '1' then
next_state<=st1; --Next state is "Whait for T0sync flag"
end if;
when st1=>
if (T0syncAut_i = '1') or (T0syncFlag_i = '1' and T0syncAut_i = '0') then
next_state <= st2; --Next state is "Whait for end of T0sync signal"
end if;
when st2 =>
Rst_T0sync <='0';
s_T0sync <='1';
if (T0syncT = '1') and ShDTLen_i=X"00000000" then
next_state<=st4; --Next state is "Whait for end of start up Dead Time"
elsif (T0syncT = '1') and ShDTLen_i/=X"00000000" then
next_state<=st3; --Next state is "Shutter open"
end if;
when st3 =>
Rst_ShDT <='0';
if ShDT = '1' then
next_state<=st4; --Next state is "Shutter open"
end if;
when st4 =>
s_Shutter <= '1';
when others=>
next_state<=st0; --Next state is "Idle"
end case;
end process fsm;
s_Enable <= not Busy_i;
Shutter_o <= s_Shutter;
T0sync_o <= s_T0sync;
END ARCHITECTURE rtl;
firmware/hdl/common/counterDown.vhd 0 → 100644
View file @ c981c4f7
--Counter down
--Outputs: Q<='1' while counting
-- Q<='0' if not counting
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY CounterDown IS
GENERIC(
MAX_WIDTH: positive := 32
);
PORT(
Clk : in std_logic;
Reset : in std_logic;
Load : in std_logic;
InitVal : in std_logic_vector(MAX_WIDTH-1 downto 0);
Count : out Std_logic_vector(MAX_WIDTH-1 downto 0);
Q : out std_logic
);
END ENTITY CounterDown;
architecture rtl of CounterDown is
signal cnt : std_logic_vector(MAX_WIDTH-1 downto 0);
signal Qtmp : std_logic;
begin
Counter: process (Clk, Reset)
begin
if (Reset='1') then
cnt <= (others =>'0');
elsif rising_edge(Clk) then
if (Load='1') then
cnt <= InitVal;
else
if Qtmp='0' then
cnt <= std_logic_vector(unsigned(cnt) - 1);
end if;
end if;
end if;
end process;
Qtmp <= '1' when cnt=(cnt'range=>'0') else
'0';
Count <= cnt;
Q <= Qtmp;
end rtl;
firmware/hdl/common/handshakes_rtl.vhd 0 → 100644
View file @ c981c4f7
--=============================================================================
--! @file handshakes_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Santiago de Compostela, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.handshakes.rtl
--
--! @brief Handshakes between TLU and DUTs. \n
--
--
--! @author Alvaro Dosil , alvaro.dosil@usc.es
--
--! @date 12:08:30 25/06/14
--
--! @version v0.1
--
--! @details
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by: </b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
ENTITY handshakes IS
GENERIC(
g_IPBUS_WIDTH : positive := 32
);
PORT(
clk_4x_logic_i : IN std_logic;
DUT_clk_i : IN std_logic;
Trigger_i : IN std_logic;
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
ipbus_reset_i : IN std_logic;
ipbus_o : OUT ipb_rbus;
logic_reset_i : IN std_logic; -- reset buffers when high. Synch withclk_4x_logic
Busy_i : IN std_logic;
Trigger_o : OUT std_logic;
rst_or_clk_o : OUT std_logic -- CONT in schematics
);
-- Declarations
END ENTITY handshakes ;
--
ARCHITECTURE rtl OF handshakes IS
signal s_handshakeEnabled : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);
signal s_Trigger_o, s_Trigger, s_Shutter, s_T0sync, s_T0sync_o : std_logic;
signal TPx3_T0syncAut, TPx3_T0syncFlag : std_logic;
signal TPx3_T0syncTime, TPx3_ShDTime : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0); -- Result from counters
signal TPx3_T0syncLen : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000004"; --Load signal and flag for the start up dead time
signal TPx3_ShDTLen : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000010"; --Load signal and flag for the start up dead time
constant c_N_CTRL : positive := 5;
constant c_N_STAT : positive := 6;
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
BEGIN
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
ipbus_registers: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => c_N_CTRL,
N_STAT => c_N_STAT
)
port map(
clk => ipbus_clk_i,
reset=> '0',--ipbus_reset_i ,
ipbus_in=> ipbus_i,
ipbus_out=> ipbus_o,
d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb=> open
);
-- Synchronize registers from logic clock to ipbus.
sync_status: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_4x_logic_i,
data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
-- Synchronize registers from logic clock to ipbus.
sync_ctrl: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_CTRL )
port map (
clk_input_i => ipbus_clk_i,
data_i => s_control_from_ipbus,
data_o => s_sync_control_from_ipbus,
clk_output_i => clk_4x_logic_i);
--Map the control registers
s_handshakeEnabled <= s_sync_control_from_ipbus(0);
TPx3_T0syncAut <= s_sync_control_from_ipbus(1)(0);
TPx3_T0syncFlag <= s_sync_control_from_ipbus(1)(1);
TPx3_T0syncLen <= x"00000001" when s_sync_control_from_ipbus(2)<x"000000002" else
s_sync_control_from_ipbus(2);
TPx3_ShDTLen <= s_sync_control_from_ipbus(3);
-- Map the status registers
s_status_to_ipbus(0) <= s_handshakeEnabled;
s_status_to_ipbus(1) <= x"0000000" & "00" & TPx3_T0syncFlag & TPx3_T0syncAut;
s_status_to_ipbus(2) <= TPx3_T0syncLen;
s_status_to_ipbus(3) <= TPx3_ShDTLen;
-----------------------------------------------------------------------------
-- I/O
-----------------------------------------------------------------------------
Trigger_o <= s_Trigger_o;
s_Trigger <= Trigger_i when s_handshakeEnabled = x"00000000" else
Trigger_i when s_handshakeEnabled = x"00000001" and Busy_i='0' else
s_Shutter when s_handshakeEnabled = x"00000002" else
'0';
rst_or_clk_o <= s_T0sync_o when s_handshakeEnabled = x"00000002" else
'0';
-- Single Handshake (GPP)
-- TPx3 Handshake
TPx3_logic: entity work.TPx3Logic
PORT MAP(
clk_i => clk_4x_logic_i,
T0syncAut_i => TPx3_T0syncAut,
T0syncFlag_i => TPx3_T0syncFlag,
T0syncLen_i => TPx3_T0syncLen,
ShDTLen_i => TPx3_ShDTLen,
logic_reset_i => logic_reset_i,
Busy_i => Busy_i,
Shutter_o => s_Shutter,
T0sync_o => s_T0sync
);
-----------------------------------------------------------------------------
-- Synchronizing signals
-----------------------------------------------------------------------------
SyncDUTTrig : entity work.pulseClockDomainCrossing
port map(
clk_input_i => clk_4x_logic_i, --! clock for input
pulse_i => s_Trigger, --! input pulse. Active high
clk_output_i => DUT_clk_i, --! clock for output
pulse_o => s_Trigger_o); --! Single cycle pulse synchronized to clock_output_i
SyncDUTT0sync : entity work.pulseClockDomainCrossing
port map(
clk_input_i => clk_4x_logic_i, --! clock for input
pulse_i => s_T0sync, --! input pulse. Active high
clk_output_i => DUT_clk_i, --! clock for output
pulse_o => s_T0sync_o); --! Single cycle pulse synchronized to clock_output_i
END ARCHITECTURE rtl;
firmware/hdl/common/ipbus_addr_decode.vhd
View file @ c981c4f7
......@@ -43,8 +43,10 @@ package body ipbus_addr_decode is
sel := 8; -- Spill_Generator / base 00000120 / mask 0000001f
elsif std_match(addr, "-----------------------1010-----") then
sel := 9; -- Event_Formatter / base 00000140 / mask 0000001f
elsif std_match(addr, "-----------------------0000---0-") then
sel := 10; -- version / base 00000000 / mask 00000000
elsif std_match(addr, "-----------------------1011-----") then
sel := 10; -- Handshakes / base 00000160 / mask 0000001f
elsif std_match(addr, "-----------------------0000-----") then
sel := 11; -- version / base 00000000 / mask 00000000
else
sel := 99;
end if;
......
firmware/hdl/common/logic_clocks_rtl.vhd
View file @ c981c4f7
......@@ -80,9 +80,9 @@ ENTITY logic_clocks IS
ipbus_o : OUT ipb_rbus;
strobe_16x_logic_o : OUT std_logic; -- strobes once every 4 cycles of clk_16x
strobe_4x_logic_o : OUT std_logic; -- one pulse every 4 cycles of clk_4x
extclk_p_b : OUT std_logic; -- either external clock in, or a clock being driven out
extclk_n_b : OUT std_logic;
clk_logic_o : OUT std_logic;
extclk_p_b : INOUT std_logic; -- either external clock in, or a clock being driven out
extclk_n_b : INOUT std_logic;
DUT_clk_o : OUT std_logic;
logic_clocks_locked_o : OUT std_logic;
logic_reset_o : OUT std_logic -- Goes high to reset counters etc. Sync with clk_4x_logic
);
......@@ -101,14 +101,15 @@ ARCHITECTURE rtl OF logic_clocks IS
-- signal s_clk40_copy : std_logic; -- Clock generated by DDR register to feed out of chip.
-- Eventually connect up clock control & status lines to IPBus
signal s_extclk_is_input : std_logic := '1';
--signal s_extclk_is_input : std_logic := '0';
-- signal s_extclk_is_input_buf : std_logic := '1';
signal s_clk_is_xtal : std_logic := '1';
signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '1';
-- signal s_logic_clk_rst : std_logic := '0';
signal s_locked_pll, s_locked_bufpll : std_logic;
signal s_clk : std_logic;
--signal s_extclk : std_logic;
signal s_DUT_Clk, s_DUT_Clk_o, s_DUT_ClkG : std_logic;
signal s_extclk, s_extclkG : std_logic;
-- signal s_clk_d1 , s_strobe_4x_p1 , s_strobe_4x_logic : std_logic;
signal s_clkfbout_buf , s_clkfbout : std_logic;
......@@ -148,7 +149,7 @@ BEGIN
case ipbus_i.ipb_addr(1 downto 0) is
when "00" =>
s_clk_is_xtal <= ipbus_i.ipb_wdata(2) ; -- select clock source
s_extclk_is_input <= ipbus_i.ipb_wdata(3); -- select direction
--s_extclk_is_input <= ipbus_i.ipb_wdata(3); -- select direction. Note that clk_is_xtal and extclk_is_input are correlated
when "01" =>
s_logic_reset_ipb <= ipbus_i.ipb_wdata(0) ; -- write to reset
......@@ -163,7 +164,8 @@ BEGIN
s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
-- register the clock status signals onto IPBus domain.
s_clock_status_ipb <= x"0000000" & s_extclk_is_input & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
--s_clock_status_ipb <= x"0000000" & s_extclk_is_input & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
s_clock_status_ipb <= x"0000000" & '0' & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
end if;
end process ipbus_write;
......@@ -196,45 +198,71 @@ BEGIN
logic_reset_o <= s_logic_reset;
logic_clocks_locked_o <= s_locked_bufpll and s_locked_pll;
ext_clk_obuf : OBUFDS
ext_clk_obuf : IOBUFDS
generic map (
IOSTANDARD => "LVDS_25")
IOSTANDARD => "BLVDS_25")
port map (
O => extclk_p_b , -- Diff_p output (connect directly to top-level port)
OB => extclk_n_b , -- Diff_n output (connect directly to top-level port)
I => s_extclk_internal -- Buffer input
O => s_extclk, -- Buffer output
IO => extclk_p_b, -- Diff_p inout (connect directly to top-level port)
IOB => extclk_n_b, -- Diff_n inout (connect directly to top-level port)
I => s_DUT_Clk_o, -- Buffer input
T => s_clk_is_ext_buf -- 3-state enable input, high=input, low=output
);
ddr_for_extclk_output : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => s_extclk_internal, -- 1-bit output data
C0 => s_clk160_internal, -- 1-bit clock input
C1 => not s_clk160_internal, -- 1-bit clock input
Q => s_DUT_Clk_o, -- 1-bit output data
C0 => clk_logic_xtal_i, -- 1-bit clock input
C1 => not clk_logic_xtal_i, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
--When an ODDR2 primitive is used in conjunction with a 3-state output, the T control pin must
--also use an ODDR2 primitive configured in the same mode as the ODDR2 primitive used for data
--output.
ddr_for_40MHz_tristate : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => s_clk_is_ext_buf, -- 1-bit output data
C0 => clk_logic_xtal_i, -- 1-bit clock input
C1 => not clk_logic_xtal_i, --not s_clk160_internal, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
D0 => not s_clk_is_xtal, -- 1-bit data input (associated with C0)
D1 => '0', --not s_clk_is_xtal, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
s_clk <= clk_logic_xtal_i;
-- --! For now just connect input of PLL to clock from Xtal...
-- clock_mux : BUFGMUX
-- generic map (
-- CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
-- )
-- port map (
-- O => s_clk, -- 1-bit output: Clock buffer output
-- I0 => s_extclk, -- 1-bit input: Clock buffer input (S=0)
-- I1 => clk_logic_xtal_i, -- 1-bit input: Clock buffer input (S=1)
-- S => s_clk_is_xtal -- 1-bit input: Clock buffer select
-- );
--! Clock selection
clock_mux : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => s_DUT_Clk, -- 1-bit output: Clock buffer output
I0 => s_extclkG, -- 1-bit input: Clock buffer input (S=0)
I1 => clk_logic_xtal_i, -- 1-bit input: Clock buffer input (S=1)
S => s_clk_is_xtal -- 1-bit input: Clock buffer select
);
extclk_buf : BUFG
port map(
O => s_extclkG,
I => s_extclk);
-- IBUFG_inst : IBUFG
-- generic map (
......@@ -245,7 +273,6 @@ BEGIN
-- I => Reset_i -- Clock buffer input (connect directly to top-level port)
-- );
-- s_clk <= clk_logic_xtal_i;
--! Clocking primitive
-------------------------------------
......@@ -286,7 +313,7 @@ BEGIN
-- Input clock control
-- CLKFBIN => s_clkfbout_buf,
CLKFBIN => s_clkfbout,
CLKIN => s_clk);
CLKIN => clk_logic_xtal_i);
s_reset_pll <= Reset_i or s_logic_reset;
......@@ -303,8 +330,8 @@ BEGIN
PLLIN => s_clk640 -- 1-bit input: Clock input from PLL
);
clk_16x_logic_o <= s_clk640_internal;
clk_16x_logic_o <= s_clk640_internal;
DUT_clk_o <= s_DUT_clk;
......@@ -357,14 +384,14 @@ BEGIN
clk_4x_logic_o <= s_clk160_internal;
-- buffer 40MHz (1x) clock
--------------------------------------
clk40_o_buf : BUFG
port map(
O => s_clk40_internal,
I => s_clk40);
clk_logic_o <= s_clk40_out;
-- -- buffer 40MHz (1x) clock
-- --------------------------------------
-- clk40_o_buf : BUFG
-- port map(
-- O => s_clk40_internal,
-- I => s_clk40);
-- clk_logic_o <= s_clk40_out;
END ARCHITECTURE rtl;
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
View file @ c981c4f7
......@@ -14,7 +14,7 @@ ENTITY top_extphy IS
GENERIC(
g_NUM_DUTS : positive := 3;
g_NUM_TRIG_INPUTS : positive := 4;
g_NUM_EXT_SLAVES : positive := 10; --! Number of slaves outside IPBus interface
g_NUM_EXT_SLAVES : positive := 11; --! Number of slaves outside IPBus interface
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_NUM_EDGE_INPUTS : positive := 4;
......@@ -26,8 +26,6 @@ ENTITY top_extphy IS
cfd_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
cfd_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
dut_clk_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
dut_clk_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
gmii_rx_clk_i : IN std_logic;
gmii_rx_dv_i : IN std_logic;
gmii_rx_er_i : IN std_logic;
......@@ -43,12 +41,14 @@ ENTITY top_extphy IS
gpio_hdr : OUT std_logic_vector (7 DOWNTO 0);
leds_o : OUT std_logic_vector (3 DOWNTO 0);
phy_rstb_o : OUT std_logic;
dut_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
dut_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
reset_or_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger lines to DUT
extclk_n_b : OUT std_logic;
extclk_p_b : OUT std_logic; --! either external clock in, or a clock being driven out
extclk_n_b : INOUT std_logic;
extclk_p_b : INOUT std_logic; --! either external clock in, or a clock being driven out
i2c_scl_b : INOUT std_logic;
i2c_sda_b : INOUT std_logic
);
......@@ -119,6 +119,7 @@ ARCHITECTURE struct OF top_extphy IS
SIGNAL clk_16x_logic : std_logic; -- 640MHz clock
SIGNAL clk_4x_logic : std_logic; --! normally 160MHz
SIGNAL clk_logic_xtal : std_logic; -- ! 40MHz clock from onboard xtal
SIGNAL s_DUT_clk : std_logic; -- ! Clock to DUT
SIGNAL data_strobe : std_logic; -- goes high when data ready to load into event buffer
SIGNAL edge_fall_i : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
SIGNAL edge_fall_time_i : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
......@@ -148,7 +149,8 @@ ARCHITECTURE struct OF top_extphy IS
SIGNAL trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
SIGNAL triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);
SIGNAL veto_o : std_logic; --! goes high when one or more DUT are busy
SIGNAL s_Trig_TO_DUT : std_logic;
SIGNAL s_rst_or_clk_to_dut: std_logic;
-- Component Declarations
COMPONENT DUTInterfaces
......@@ -160,22 +162,21 @@ ARCHITECTURE struct OF top_extphy IS
busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
clk_4x_logic_i : IN std_logic ;
clk_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
ipbus_clk_i : IN std_logic ;
ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
ipbus_reset_i : IN std_logic ;
strobe_4x_logic_i : IN std_logic ; -- ! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_i : IN std_logic ; -- goes high when trigger logic issues a trigger
--shutter_i : IN std_logic; -- goes high when trigger logic issues a shutter
clk_to_dut_i : IN std_logic ; -- ! clock to DUT
reset_or_clk_to_dut_i : IN std_logic ; -- ! Either reset line or trigger
ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
--shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
--shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
veto_o : OUT std_logic -- goes high when one or more DUT are busy
);
END COMPONENT DUTInterfaces;
......@@ -288,7 +289,7 @@ ARCHITECTURE struct OF top_extphy IS
strobe_4x_logic_o : OUT std_logic ; -- one pulse every 4 cycles of clk_4x
extclk_p_b : OUT std_logic ; -- either external clock in, or a clock being driven out
extclk_n_b : OUT std_logic ;
clk_logic_o : OUT std_logic ;
DUT_clk_o : OUT std_logic ;
logic_clocks_locked_o : OUT std_logic ;
logic_reset_o : OUT std_logic -- Goes high TO reset counters etc. Sync with clk_4x_logic
);
......@@ -340,6 +341,24 @@ ARCHITECTURE struct OF top_extphy IS
trigger_active_o : OUT std_logic --! Goes high when triggers are active ( ie. not veoted)
);
END COMPONENT triggerLogic;
COMPONENT handshakes
GENERIC(
g_IPBUS_WIDTH : positive := 32
);
PORT(
clk_4x_logic_i : IN std_logic;
DUT_clk_i : IN std_logic;
Trigger_i : IN std_logic;
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
ipbus_reset_i : IN std_logic;
ipbus_o : OUT ipb_rbus;
logic_reset_i : IN std_logic; -- reset buffers when high. Synch withclk_4x_logic
Busy_i : IN std_logic;
Trigger_o : OUT std_logic;
rst_or_clk_o : OUT std_logic
);
END COMPONENT handshakes;
-- Optional embedded configurations
-- pragma synthesis_off
......@@ -351,6 +370,7 @@ ARCHITECTURE struct OF top_extphy IS
FOR ALL : logic_clocks USE ENTITY work.logic_clocks;
FOR ALL : triggerInputs USE ENTITY work.triggerInputs;
FOR ALL : triggerLogic USE ENTITY work.triggerLogic;
FOR ALL : handshakes USE ENTITY work.handshakes;
-- pragma synthesis_on
......@@ -396,15 +416,17 @@ BEGIN
busy_from_dut_n_i => busy_n_i,
busy_from_dut_p_i => busy_p_i,
clk_4x_logic_i => clk_4x_logic,
clk_from_dut_n_i => dut_clk_n_i,
clk_from_dut_p_i => dut_clk_p_i,
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(0),
ipbus_reset_i => ipbus_reset,
strobe_4x_logic_i => strobe_4x_logic,
trigger_counter_i => trigger_count,
trigger_i => overall_trigger,
clk_to_dut_i => s_DUT_clk,
trigger_i => s_Trig_TO_DUT, --overall_trigger,
reset_or_clk_to_dut_i => s_rst_or_clk_to_dut,
ipbus_o => ipbr(0),
clk_to_dut_n_o => dut_clk_n_o,
clk_to_dut_p_o => dut_clk_p_o,
reset_or_clk_to_dut_n_o => reset_or_clk_n_o,
reset_or_clk_to_dut_p_o => reset_or_clk_p_o,
trigger_to_dut_n_o => triggers_n_o,
......@@ -516,7 +538,7 @@ BEGIN
strobe_4x_logic_o => strobe_4x_logic,
extclk_p_b => extclk_p_b,
extclk_n_b => extclk_n_b,
clk_logic_o => OPEN,
DUT_clk_o => s_DUT_clk,
logic_clocks_locked_o => leds_o(1),
logic_reset_o => logic_reset
);
......@@ -565,5 +587,23 @@ BEGIN
pre_veto_trigger_o => OPEN,
trigger_active_o => leds_o(0)
);
I8 : handshakes
GENERIC MAP(
g_IPBUS_WIDTH => g_IPBUS_WIDTH
)
PORT MAP(
clk_4x_logic_i => clk_4x_logic,
DUT_clk_i => s_DUT_clk,
Trigger_i => overall_trigger,
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(10),
ipbus_reset_i => ipbus_reset,
ipbus_o => ipbr(10),
logic_reset_i => logic_reset,
Busy_i => veto_o,
Trigger_o => s_Trig_TO_DUT,
rst_or_clk_o => s_rst_or_clk_to_dut
);
END ARCHITECTURE struct;
firmware/scripts/aida_mini_tlu_addr_map.txt
View file @ c981c4f7
......@@ -2,13 +2,14 @@
*-------------------------------------------------------------
FirmwareId 0x00000000 0xffffffff 1 0
* DUT interfaces base = 0x020
DUTMask 0x00000020 0xffffffff 1 1
*
* trigger inputs = 0x040
SerdesRst 0x00000040 0xffffffff 1 1
ThrCount0 0x00000041 0xffffffff 1 0
ThrCount1 0x00000042 0xffffffff 1 0
ThrCount2 0x00000043 0xffffffff 1 0
ThrCount3 0x00000044 0xffffffff 1 0
ThrCount0 0x00000041 0xffffffff 0 1
ThrCount1 0x00000042 0xffffffff 0 1
ThrCount2 0x00000043 0xffffffff 0 1
ThrCount3 0x00000044 0xffffffff 0 1
SerdesRstR 0x00000048 0xffffffff 1 1
ThrCount0R 0x00000049 0xffffffff 1 0
ThrCount1R 0x0000004a 0xffffffff 1 0
......@@ -30,8 +31,8 @@ ExternalTriggerVetoR 0x0000006d 0xffffffff 1 0
* event buffer = 0x080
EventFifoData 0x00000080 0xffffffff 1 0
EventFifoFillLevel 0x00000081 0xffffffff 1 0
EventFifoCSR 0x00000082 0xffffffff 1 1
EventFifoFillLevelFlags 0x00000083 0xffffffff 1 0
EventFifoCSR 0x00000082 0xffffffff 0 1
EventFifoFillLevelFlags 0x00000082 0xffffffff 1 0
*
* logic clocks = 0x0A0
LogicClocksCSR 0x000000A0 0xffffffff 1 1
......@@ -78,3 +79,14 @@ SpillRearmDeadTime 0x00000127 0xffffffff 1 1
*
* Event formatter = 0x140
Enable_Record_Data 0x00000140 0xffffffff 1 1
*
* Handshakes = 0x160
HandshakeTypeW 0x00000160 0xffffffff 0 1
HandshakeConfW 0x00000161 0xffffffff 0 1
TPx3_T0SyncLenW 0x00000162 0xffffffff 0 1
TPx3_ShDTimeLenW 0x00000163 0xffffffff 0 1
HandshakeTypeR 0x00000168 0xffffffff 1 0
HandshakeConfR 0x00000169 0xffffffff 1 0
TPx3_T0SyncLenR 0x0000016a 0xffffffff 1 0
TPx3_ShDTimeLenR 0x0000016b 0xffffffff 1 0
firmware/scripts/aida_mini_tlu_addr_map.txt~
View file @ c981c4f7
......@@ -2,14 +2,18 @@
*-------------------------------------------------------------
FirmwareId 0x00000000 0xffffffff 1 0
* DUT interfaces base = 0x020
DUTMask 0x00000020 0xffffffff 1 1
*
* trigger inputs = 0x040
SerdesRst 0x00000040 0xffffffff 1 1
ThrCount0 0x00000041 0xffffffff 1 0
ThrCount1 0x00000042 0xffffffff 1 0
ThrCount2 0x00000043 0xffffffff 1 0
ThrCount3 0x00000044 0xffffffff 1 0
ThrCount0 0x00000041 0xffffffff 0 1
ThrCount1 0x00000042 0xffffffff 0 1
ThrCount2 0x00000043 0xffffffff 0 1
ThrCount3 0x00000044 0xffffffff 0 1
SerdesRstR 0x00000048 0xffffffff 1 1
ThrCount0R 0x00000049 0xffffffff 1 0
ThrCount1R 0x0000004a 0xffffffff 1 0
ThrCount2R 0x0000004b 0xffffffff 1 0
ThrCount3R 0x0000004c 0xffffffff 1 0
*
* trigger logic = 0x060 **Note the different read and write directions
InternalTriggerIntervalW 0x00000062 0xffffffff 1 1
......@@ -26,8 +30,8 @@ ExternalTriggerVetoR 0x0000006d 0xffffffff 1 0
* event buffer = 0x080
EventFifoData 0x00000080 0xffffffff 1 0
EventFifoFillLevel 0x00000081 0xffffffff 1 0
EventFifoCSR 0x00000082 0xffffffff 1 1
EventFifoFillLevelFlags 0x00000083 0xffffffff 1 0
EventFifoCSR 0x00000082 0xffffffff 0 1
EventFifoFillLevelFlags 0x00000082 0xffffffff 1 0
*
* logic clocks = 0x0A0
LogicClocksCSR 0x000000A0 0xffffffff 1 1
......@@ -74,3 +78,14 @@ SpillRearmDeadTime 0x00000127 0xffffffff 1 1
*
* Event formatter = 0x140
Enable_Record_Data 0x00000140 0xffffffff 1 1
*
* Handshakes = 0x160
HandshakeTypeW 0x00000160 0xffffffff 0 1
HandshakeConfW 0x00000161 0xffffffff 0 1
TPx3_T0SyncLenW 0x00000162 0xffffffff 0 1
TPx3_ShDTimeLenW 0x00000163 0xffffffff 0 1
HandshakeTypeR 0x00000168 0xffffffff 1 0
HandshakeConfR 0x00000169 0xffffffff 1 0
TPx3_T0SyncLenR 0x0000016a 0xffffffff 1 0
TPx3_ShDTimeLenR 0x0000016b 0xffffffff 1 0
firmware/scripts/fmc_tlu_addr_table
View file @ c981c4f7
......@@ -11,5 +11,5 @@
7 Shutter_Generator 0x100 5
8 Spill_Generator 0x120 5
9 Event_Formatter 0x140 5
9 version 0x000 0
10 emac_hostbus 0x002 1
10 Handshakes 0x160 5
11 version 0x000 0
firmware/scripts/test_aida_tlu_trig_counter.py
View file @ c981c4f7
......@@ -76,16 +76,16 @@ for iLoop in range(0,numLoops):
inputStatus = board.read("SerdesRst")
print "Input status = " , hex(inputStatus)
count0 = board.read("ThrCount0")
count0 = board.read("ThrCount0R")
print " Count 0 = " , count0
count1 = board.read("ThrCount1")
count1 = board.read("ThrCount1R")
print " Count 1 = " , count1
count2 = board.read("ThrCount2")
count2 = board.read("ThrCount2R")
print " Count 2 = " , count2
count3 = board.read("ThrCount3")
count3 = board.read("ThrCount3R")
print " Count 3 = " , count3
time.sleep(1.0)
......
firmware/ucf/sp601_FMC_mTLU.ucf
View file @ c981c4f7
......@@ -87,19 +87,20 @@ NET "TRIGGERS_P_O<2>" LOC = "G11"; ## "FMC_LA09_P" , D14 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "N6"; ## "FMC_LA19_P" , H22 on FMC
##NET "SHUTTERS_N_O<2>" LOC = "P6"; ## "FMC_LA19_N" , H23 on FMC
NET "DUT_CLK_P_I<0>" LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
NET "DUT_CLK_N_I<0>" LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
NET "DUT_CLK_P_I<1>" LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
NET "DUT_CLK_N_I<1>" LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
NET "DUT_CLK_P_I<2>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
NET "DUT_CLK_N_I<2>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
NET "DUT_CLK_P_I<0>" LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC , DUT_CLK_P_I<0>
NET "DUT_CLK_N_I<0>" LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N_I<0>
NET "DUT_CLK_P_I<1>" LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC , DUT_CLK_P_I<0>
#NET "DUT_CLK_P_I<1>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC , DUT_CLK_N_I<0>
NET "DUT_CLK_P_I<2>" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC , DUT_CLK_P_I<0>
#NET "DUT_CLK_P_I<2>" LOC = "A16"; ## "FMC_LA04_N" , H11 on FMC , DUT_CLK_N_I<0>
NET "RESET_OR_CLK_P_O<0>" LOC = "M10"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
#NET "RESET_OR_CLK_N_O<0>" LOC = "N9"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
NET "RESET_OR_CLK_P_O<1>" LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
#NET "RESET_OR_CLK_N_O<1>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
NET "RESET_OR_CLK_P_O<2>" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
#NET "RESET_OR_CLK_N_O<2>" LOC = "A16"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
NET "RESET_OR_CLK_P_O<1>" LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
NET "RESET_OR_CLK_N_O<1>" LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
NET "RESET_OR_CLK_P_O<2>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
NET "RESET_OR_CLK_N_O<2>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
# Trigger Inputs
......
firmware/ucf/sp601_FMC_mTLU_v1a.ucf
View file @ c981c4f7
......@@ -134,12 +134,12 @@ NET "triggers_p_o[2]" LOC = C7;
#NET "DUT_CLK_N_I<0>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC
#NET "DUT_CLK_N_I<1>" LOC = "T11"; ## "FMC_LA27_N" , C27 on FMC
#NET "DUT_CLK_N_I<2>" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
## "FMC_LA21_P" , H25 on FMC
NET "dut_clk_p_o[0]" LOC = T4;
## "FMC_LA27_P" , C26 on FMC
NET "dut_clk_p_i[1]" LOC = R11;
NET "dut_clk_p_o[1]" LOC = R11;
## "FMC_LA02_P" , H7 on FMC
NET "dut_clk_p_i[2]" LOC = C15;
## "FMC_LA21_P" , H25 on FMC
NET "dut_clk_p_i[0]" LOC = T4;
NET "dut_clk_p_o[2]" LOC = C15;
# Labelled CONT on schematic.
#NET "RESET_OR_CLK_N_O<0>" LOC = "T7"; ## "FMC_LA22_N" , G25 on FMC
......
firmware/ucf/sp605_FMC_mTLU_v1a.ucf
View file @ c981c4f7
......@@ -81,17 +81,17 @@ NET "i2c_sda_b" LOC = R22;
## "FMC_LA19_P" , H22 on FMC
NET "busy_p_i[0]" LOC = R11;
## "FMC_LA14_P" , C18 on FMC
NET "busy_p_i[1]" LOC = C17;
## "FMC_LA12_P" , G15 on FMC
NET "busy_p_i[2]" LOC = H13;
NET "busy_p_i[1]" LOC = H13;
## "FMC_LA14_P" , C18 on FMC
NET "busy_p_i[2]" LOC = C17;
## "FMC_LA20_P" , G21 on FMC
NET "triggers_p_o[0]" LOC = R9;
## "FMC_LA03_P" , G9 on FMC
NET "triggers_p_o[1]" LOC = B18;
## "FMC_LA16_P" , G18 on FMC
NET "triggers_p_o[2]" LOC = C5;
NET "triggers_p_o[1]" LOC = C5;
## "FMC_LA03_P" , G9 on FMC
NET "triggers_p_o[2]" LOC = B18;
# Remove shutters ( also known as SPARE ) for now
#NET "SPARE_N_O<1>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC
......@@ -100,21 +100,21 @@ NET "triggers_p_o[2]" LOC = C5;
#NET "SPARE_P_O<2>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
## "FMC_LA21_P" , H25 on FMC
NET "dut_clk_p_i[0]" LOC = V11;
## "FMC_LA27_P" , C26 on FMC
NET "dut_clk_p_i[1]" LOC = AA10;
NET "dut_clk_p_o[0]" LOC = AA10;
## "FMC_LA21_P" , H25 on FMC
NET "dut_clk_p_o[1]" LOC = V11;
## "FMC_LA02_P" , H7 on FMC
NET "dut_clk_p_i[2]" LOC = G8;
NET "dut_clk_p_o[2]" LOC = G8;
# Labelled CONT on schematic.
## "FMC_LA22_P" , G24 on FMC
NET "reset_or_clk_p_o[0]" LOC = V7;
## "FMC_LA18_CC_P" , C22 on FMC
NET "reset_or_clk_p_o[1]" LOC = T12;
## "FMC_LA07_P" , H13 on FMC
NET "reset_or_clk_p_o[2]" LOC = B2;
## "FMC_LA07_CC_P" , H13 on FMC
NET "reset_or_clk_p_o[1]" LOC = B2;
## "FMC_LA18_P" , C22 on FMC
NET "reset_or_clk_p_o[2]" LOC = T12;
# Trigger Inputs
......
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