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AIDA-2020 TLU
Commit ccc18cf9 authored by David Cussans's avatar David Cussans
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Merge remote-tracking branch 'firmware_AIDA/master' 

Used instructions at https://bneijt.nl/blog/post/merge-a-subdirectory-of-another-repository-with-git/ to merge in Paolo's firmware with FMC-TLU Git repository

git clone git@github.com:DavidCussans/firmware_AIDA.git
git clone ssh://git@ohwr.org/fmc-projects/fmc-mtlu.git
cd fmc-mtlu/
git remote add firmware_AIDA ../firmware_AIDA
git fetch firmware_AIDA
git merge -s ours --no-commit --allow-unrelated-histories firmware_AIDA/master
( N.B. Had to add allow-unrelated-histories flag ... )
git read-tree --prefix=AIDA_tlu -u firmware_AIDA/master
git commit
parents adcab1e8 ac97acd0
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/TLU_v1e/work/TLU_v1e.runs/*
/EUDETdummy/work/*
/TLU_v1e/work/*
/TLU_v1c/work/*
/Enclustra_Example/*
/Enclustra_tests/
/TLU_v1e/scripts/datafiles
/Data/*
/TLU_v1e/.Xil/
*.pyc
.svn/*
*.jou
*.str
*.BKP
## Backup files
*.py~
*.md~
*.sh~
*.*~
## Core latex/pdflatex auxiliary files:
*.aux
*.lof
*.log
*.lot
*.fls
*.out
*.toc
*.fmt
*.fot
*.cb
*.cb2
## Bibliography auxiliary files (bibtex/biblatex/biber):
*.bbl
*.bcf
*.blg
*-blx.aux
*-blx.bib
*.run.xml
## WinEdt project
*.prj.bak
## Intermediate documents:
*.dvi
*.xdv
*-converted-to.*
## Build tool auxiliary files:
*.fdb_latexmk
*.synctex
*.synctex(busy)
*.synctex.gz
*.synctex.gz(busy)
*.pdfsync
# makeidx
*.idx
*.ilg
*.ind
*.ist
# glossaries
*.acn
*.acr
*.glg
*.glo
*.gls
*.glsdefs
# xindy
*.xdy
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*O:/LatexFiles/Glossary/myGlossary.tex
*ch_TLU_Preparation
*ch_TLU_Hardware
*ch_TLU_clock
*DUT_signals
*ch_TLU_triggerInputs
*ch_EventBuffer
*ch_TLU_Functions
*ch_TLU_IPBusRegs
*ch_EUDAQParameters
*ch_EUDAQProducer
*ch_TLU_Appendix
<
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\chapter{DUT signals}\label{ch:DUTsignals}
In the old versions of the \gls{tlu} the direction of the signals on the \verb|HDMI*| connectors were pre-defined. The new hardware has separate lines for signals going into the \gls{tlu} and signals out of the \gls{tlu}. See section~\ref{ch:hwDUT} for further details.\\
\ No newline at end of file
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\documentclass[10pt,twoside, fleqn]{memoir}
%\usepackage{createspace}
%\usepackage[size=pocket,noicc]{createspace}
%\usepackage[paperwidth=4.25in, paperght=6.875in,bindingoffset=.75in]{geometry}
\usepackage[T1]{fontenc}
\usepackage{mathpazo} % USE PALATINO FONT
%\usepackage{newpxtext,newpxmath}
\usepackage[latin1]{inputenc}
%\usepackage[xindy]{imakeidx}
%\usepackage{imakeidx}
\usepackage[nomain,acronym,xindy,toc]{glossaries}
%\usepackage{glossaries} %For acronyms
\usepackage[british]{babel}
%\usepackage{tgtermes}
%\usepackage[framed, numbered, autolinebreaks]{mcode} %MATLAB Snippet code
\usepackage{listings}
\usepackage{graphicx}
\usepackage{glossaries}
\usepackage{hyperref} % HYPERLINKS
\usepackage[font=footnotesize]{caption}
%\usepackage[hidelinks]{hyperref}
%\usepackage{xcolor}
\usepackage{subcaption}
\usepackage{pdflscape} %Landscape pages
\usepackage{pdfpages} %Insert pdf in document
\usepackage{amsmath}
\usepackage{amssymb}
\usepackage{gensymb} %Degree sign
\usepackage{footnote} %Footnotes in tabulars
\usepackage{xcolor,framed,marginnote,blindtext}
\hypersetup{
colorlinks,
linkcolor={blue!50!black},
citecolor={blue!50!black},
urlcolor={blue!80!black}
}% Get rid of that MySpace feeling in hypelinks...
\usepackage{listings} %Include code
\usepackage{multirow}
\usepackage{datetime}
%\usepackage{svg}
\definecolor{infobackground}{RGB}{217,237,247}
\definecolor{infoforeground}{RGB}{58,135,173}
\definecolor{infoborder}{RGB}{188,232,241}
\usepackage{environ}
\usepackage{tikz} %TO CREATE BLOCK DIAGRAMS
\usetikzlibrary{fit,backgrounds,calc}
%\usepackage{vrsion}
\colorlet{shadecolor}{blue!10}
%\usepackage[fleqn]{amsmath}
\usetikzlibrary{shapes,arrows}
\usetikzlibrary{positioning}
\setcounter{tocdepth}{2} % DEPTH OF TABLE OF CONTENTS; 2= SUBSECTIONS INCLUDED
\setcounter{secnumdepth}{2} % SUBSECTIONS ARE NUMBERED
\usepackage[clockwise, figuresright]{rotating}
\usepackage{longtable}
\usepackage{tabu}
\NewEnviron{alertinfo}[1]
{
\begin{tikzpicture}
\node[inner sep=0pt,
draw=infoborder,
line width=1.2pt,
fill=infobackground] (box) {\parbox[t]{.99\textwidth}
{%
\begin{minipage}{.15\textwidth}
\centering\tikz[scale=3]
\node[scale=1]
{
\includegraphics[scale=0.04]{./Images/Warning.png}
};
\end{minipage}%
\begin{minipage}{.80\textwidth}
\vskip 10pt
\textbf{\textcolor{infoforeground}{#1}}\par\smallskip
\textcolor{infoforeground}{\BODY}
\par\smallskip
\end{minipage}\hfill
}%
};
\end{tikzpicture}
}
%\usepackage{mathpazo}
%\usepackage[protrusion=true,expansion=true]{microtype}
%\usepackage{type1cm}
%\usepackage{lettrine}
%\checkandfixthelayout
% See the ``Memoir customise'' template for some common customisations
% Don't forget to read the Memoir manual: memman.pdf
%\title{TITLE OF BOOK}
%\author{NAME OF AUTHOR}
%\date{} % Delete this line to display the current date
%% BEGIN TITLE
\makeatletter
\def\maketitle{%
\null
\thispagestyle{empty}%
\vfill
\begin{center}\leavevmode
\normalfont
{\LARGE\raggedleft \@author\par}%
\hrulefill\par
{\huge\raggedright \@title\par}%
\vskip 1cm
{\Large \@date\par}%
\end{center}%
\vfill
\null
\cleardoublepage
}
\makeatother
\author{Paolo Baesso}
\title{AIDA Trigger logic unit (TLU)}
\date{\today}
\loadglsentries{O:/LatexFiles/Glossary/myGlossary.tex}
%\input{O:/LatexFiles/Glossary/myGlossary.tex}
%\makeglossaries
%%% BEGIN DOCUMENT
\makeindex
\begin{document}
\def\brd{FMC\_TLU\_v1E }
\def\oldbrd{FMC\_TLU\_v1C }
\let\cleardoublepage\clearpage
\maketitle
\frontmatter
\null\vfill
\begin{flushleft}
\textit{Board \brd.}\newline
\newline
Paolo Baesso - \monthname, \the\year\newline paolo.baesso@bristol.ac.uk
\bigskip
\end{flushleft}
\let\cleardoublepage\clearpage
\newpage
\tableofcontents
\mainmatter
\sloppy
\newenvironment{SpecialPar}
{\begin{shaded}\noindent}
{\end{shaded}}
%%% INCLUDE CHAPTERS
%\def\conn{\verb|HDMI1|}
%\def\conn{\verb|HDMI2|}
%\def\conn{\verb|HDMI3|}
%\def\conn{\verb|HDMI4|}
%\include{ch_Introduction}
\include{ch_TLU_Preparation}
\include{ch_TLU_Hardware}
\include{ch_TLU_clock}
\include{DUT_signals}
\include{ch_TLU_triggerInputs}
\include{ch_EventBuffer}
\include{ch_TLU_Functions}
\include{ch_TLU_IPBusRegs}
\include{ch_EUDAQParameters}
\include{ch_EUDAQProducer}
\include{ch_TLU_Appendix}
%\begin{figure}[h]
% \centering
% \includegraphics[width=1.62\textwidth, angle=90]{./Images/protoDUNE_fmc_sfp_to_slave_v0-7.pdf}
% \caption{Sketch of the connections and signal names between the elements of the board.}\label{fig:Connections}
%\end{figure}
%\section{Schematic}
%\includepdf[pages={1-},scale=0.99, landscape=true]{./Images/PC053A.pdf}
%%\includepdf[pages={1-},scale=0.99, landscape=true]{./Images/PC053A_TOPLEVEL.pdf}
%%% GLOSSARY
\printglossaries
%\printglossary[type=\acronymtype]
\printglossary[type=\acronymtype,title=Abbreviations]
%%% BIBLIOGRAPHY
%\bibliographystyle{unsrt}
%\bibliography{./../../Bibliography/myBibliography}
\end{document}
\ No newline at end of file
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\chapter{EUDAQ Producer}\label{ch:eudaqprod}
Current structure of a fmctlu producer event:
\lstset{language=XML}
\scriptsize
\begin{lstlisting}
<Event>
<Type>2149999981</Type>
<Extendword>171577627</Extendword>
<Description>Ex0Tg</Description>
<Flag>0x00000018</Flag>
<RunN>0</RunN>
<StreamN>0</StreamN>
<EventN>0</EventN>
<TriggerN>88</TriggerN>
<Timestamp>0x0000000000000000 -> 0x0000000000000000</Timestamp>
<Timestamp>0 -> 0</Timestamp>
<Block_Size>0</Block_Size>
<SubEvents>
<Size>1</Size>
<Event>
<Type>2149999981</Type>
<Extendword>3634980144</Extendword>
<Description>TluRawDataEvent</Description>
<Flag>0x00000010</Flag>
<RunN>96</RunN>
<StreamN>4008428646</StreamN>
<EventN>88</EventN>
<TriggerN>88</TriggerN>
<Timestamp>0x0000000105b44f91 -> 0x0000000105b44faa</Timestamp>
<Timestamp>4390670225 -> 4390670250</Timestamp>
<Tags>
<Tag>PARTICLES=89</Tag>
<Tag>SCALER0=93</Tag>
<Tag>SCALER1=93</Tag>
<Tag>SCALER2=0</Tag>
<Tag>SCALER3=0</Tag>
<Tag>SCALER4=0</Tag>
<Tag>SCALER5=0</Tag>
<Tag>TEST=110011</Tag>
<Tag>trigger=</Tag>
</Tags>
<Block_Size>0</Block_Size>
</Event>
</SubEvents>
</Event>
\end{lstlisting}
\normalsize
\begin{description}
\item[Type] ??
\item[ExtendWord] ??
\item[Description]
\item[Flag] Independent from producer. See the \href{https://github.com/eudaq/eudaq/blob/master/main/lib/core/include/eudaq/Event.hh#L87}{EUDAQ documentation} for details.
\item[RunN]
\item[StreamN]
\item[EventN]
\item[TriggerN] Both in the event and subevent this is written byt the producer with \verb|ev->SetTriggerN(trigger_n);|
\item[Timestamp] The event timestamp is currently always 0. The subevent timestamps is written by the producer \verb|ev->SetTimestamp(ts_ns, ts_ns+25, false);|. The top line (0x0000000105b44f91, in the example) is coarse time stamp multiplied by 25, so it represents the time in nanoseconds. The bottom one (4390670225) is the same number but written in decimal format instead of hexadecimal.
\item[PARTICLES] Number of pre-veto triggers recorded by the \gls{tlu}: the trigger logic can detect a valid trigger condition even when the unit is vetoed. In this case no trigger is issued to the \gls{dut}s but the number of such triggers is stored as number of particles. \verb|ev->SetTag("PARTICLES", std::to_string(pt));|
\item[SCALER\#] Number of triggers edges seen by the specific discriminator. \verb|ev->SetTag("SCALER", std::to_string(sl));|
\item[???] Event type from \gls{tlu} is missing?
\item[???] Input trig, i.e. the actual firing inputs should be in TRIGGER but there seems to be nothing there
\end{description}
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\section{Event buffer}\label{ch:eventBuffer}
The event buffer IPBus slave has four registers.
Writing to \verb|EventFifoCSR| will reset the \gls{fifo}. Reading from either of the register will put their data on the IPBus data line.\\
Reading from \verb|EventFifoCSR| returns the following:
\begin{itemize}
\item bit 0: \gls{fifo} empty flag
\item bit 1: \gls{fifo} almost empty flag
\item bit 2: \gls{fifo} almost full flag
\item bit 3: \gls{fifo} full flag
\item bit 4: \gls{fifo} programmable full flag
\item other bits: 0
\end{itemize}
The status register (SerdesRst) is as follows:
\begin{itemize}
\item bit 0: reset the ISERDES
\item bit 1: reset the trigger counters
\item bit 2: calibrate IDELAY: This seems to be disconnected at the moment.
\item bit 3: fixed to 0
\item bit 4, 5: status of \verb|thresholdDeserializer(Input0)|. When the IDELAY modules (prompt, delayed) have reached the correct delay, these two bits should read 00.
\item bit 6, 7: status of \verb|thresholdDeserializer(Input1)|
\item bit 8, 9: status of \verb|thresholdDeserializer(Input2)|
\item bit 10, 11: status of \verb|thresholdDeserializer(Input3)|
\item bit 12, 13: status of \verb|thresholdDeserializer(Input4)|
\item bit 14, 15: status of \verb|thresholdDeserializer(Input5)|
\item bit 16, 19: fixed to 0
\item bit 20: \verb|s_deserialized_threshold_data(Input0)(7)|
\item bit 21: \verb|s_deserialized_threshold_data(Input1)(7)|
\item bit 22: \verb|s_deserialized_threshold_data(Input2)(7)|
\item bit 23: \verb|s_deserialized_threshold_data(Input3)(7)|
\item bit 24: \verb|s_deserialized_threshold_data(Input4)(7)|
\item bit 25: \verb|s_deserialized_threshold_data(Input5)(7)|
\end{itemize}
9 bits are used to determine trigger edges. 8 are from the deserializers, 1 is added as the LSB and is the MSB from the previous word.
\begin{figure}
\centering
\includegraphics[width=.95\textwidth]{./Images/fifo_words.pdf}
\caption{Event structure}
\label{fig:fifo_event}
\end{figure}
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\chapter{Appendix}\label{ch:appendix}
\includepdf[link,pages={1}]{./Docs/PM3TopView.pdf}
\includepdf[link,pages=-, angle=90]{./Docs/Connections.pdf}
\includepdf[link,pages=-, angle=90]{./Docs/schematics.pdf}
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\chapter{Functions}\label{ch:functions}
The following is a list of files containing the code for the \gls{tlu}:
\begin{itemize}
\item \verb|./eudaq2/user/eudet/misc/fmctlu_runcontrol.ini|:\newline initialization file for the hardware. The location of the file can be passed to the EUDAQ code in the \gls{gui}.
\item \verb|./eudaq2/user/eudet/misc/fmctlu_runcontrol.conf|:\newline configuration file. It contains all the parameters to be loaded in the \gls{tlu} at the beginning of the run. If this file is not found, EUDAQ will use a list of default settings. The location of the file (and its name) can be passed to the EUDAQ code in the \gls{gui}.
\item \verb|./eudaq2/user/eudet/misc/fmctlu_connection.xml|:\newline define the IP address and address map of the \gls{tlu}. The one listed is the default location for the file. A different location can be specified with the \verb|ConnectionFile| option in the \emph{conf} file for the \gls{tlu}.
\item \verb|./eudaq2/user/eudet/misc/fmctlu_address.xml|:\newline address map for the \gls{tlu}. The location of the file is specified in the \verb|fmctlu_connection.xml| file.
\item \verb|./eudaq2/user/eudet/misc/fmctlu_clock_config.txt|:\newline configuration for the Si5345 clock chip. In order for the hardware to work a configuration file must be present. Those listed are the default name and location for the file; a different file can be specified with the \verb|CLOCK_CFG_FILE| option in the \emph{conf} file for the \gls{tlu}.
\item \verb|./eudaq2/user/eudet/module/src/FMCTLU_Producer.cc|:\newline eudaq producer for the \gls{tlu}. Contains the methods to initialize, configure, start, stop the \gls{tlu} producer.
\item \verb|./eudaq2/user/eudet/hardware/src/FmctluController.cc|:\newline Contains the definition of the hardware class for the \gls{tlu} and the methods to set and read from its hardware, such as clock chip, DAC, etc. This lever is abstract with respect to the actual hardware, so that if a future version of the board uses different components it should be possible to re-use this code.
\item \verb|./eudaq2/user/eudet/hardware/include/FmctluController.hh|:\newline Headers for the controller.
\item \verb|./eudaq2/user/eudet/hardware/src/FmctluController.cxx|:\newline Executable for the controller.
\item \verb|./eudaq2/user/eudet/hardware/src/FmctluHardware.cc|:\newline This is the code that deals with the actual hardware on the \gls{tlu}, and contains specific instructions for the chips mounted in the current version. It contains several classes for the ADC, the clock chip, the I/O expanders etc.
\item \verb|./eudaq2/user/eudet/hardware/include/FmctluHardware.hh|:\newline Header for the hardware.
\item \verb|./eudaq2/user/eudet/hardware/src/FmctluI2c.cc|:\newline core functions used to read and write from \gls{i2c} compatible slaves.
\item \verb|./eudaq2/user/eudet/hardware/include/FmctluI2c.hh|:\newline Headers for the \gls{i2c} core.
\end{itemize}
\section{Functions}
\begin{description}
\item[enableClkLEMO] Enable or disable the output clock to the differential LEMO connector.
\item[enableHDMI] Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.\\ In the configuration file use \verb|HDMIx_on = 0| to disable a channel and \verb|HDMI1_on = 1| to enable it (x can be 1, 2, 3, 4).\\
NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.\\
NOTE: Clock source must be defined separately using SetDutClkSrc (DUTClkSrc in python script).\\
NOTE: this is called \verb|DUTOutputs| on the python scripts.
\item[GetFW] dsds
\item[getSN] dsd
\item[I2C\_enable] dsd
\item[InitializeClkChip]
\item[InitializeDAC]
\item[InitializeIOexp]
\item[InitializeI2C]
\item[PopFrontEvent]
\item[ReadRRegister]
\item[ReceiveEvents]
\item[ResetEventsBuffer]
\item[SetDutClkSrc] Set the clock source for a specific \gls{hdmi} connector. The source can be set to 0 (no clock), 1 (Si5345) or 2 (FPGA). In the configuration file use \verb|HDMIx_on = N| to select the source (x can be 1, 2, 3, 4, N is the clock source).\\
NOTE: this is called \verb|DUTClkSrc| on python scripts.
\item[SetPulseStretchPk] Takes a vector of six numbers, packs them (5-bits each) and sends them to the PulseStretch register.
\item[SetThresholdValue]
\item[setTrgPattern] Writes two 32-bit words to define the trigger pattern for the inputs. See section~\ref{ch:triggerinputs} for details.
\item[SetWRegister]
\item[SetUhalLogLevel]
\end{description}
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\chapter{Introduction}\label{ch:introduction}
This manual describes the AIDA \gls{tlu} designed for the \href{http://aida2020.web.cern.ch/}{AIDA-2020 project} by David Cussans\footnote{University of Bristol, Particle Physics group} and Paolo Baesso\footnote{University of Bristol, Particle Physics group}.\\
The unit is designed to be used in High Energy Physics beam-tests and provides a simple and flexible interface for fast timing and triggering signals at the AIDA pixel sensor beam-telescope.\\
The current version of the hardware is an evolution of the \href{https://twiki.cern.ch/twiki/bin/view/MimosaTelescope/TLU}{EUDET-TLU} and the \href{https://www.ohwr.org/projects/fmc-mtlu/wiki}{miniTLU} and is shipped in a metallic case that includes an \gls{fpga} board and the \gls{tlu} \gls{pcb}: the \gls{fpga} is responsible for all the logic functions of the unit, while the \gls{pcb} contains the clock chip, discriminator and interface blocks needed to communicate with other devices.\\
The current version of the \gls{pcb} is \brd and is designed to plug onto a carrier \gls{fpga} board like any other \gls{fmc} mezzanine board, although its form factor does not comply with the ANSI-VITA-57-1 standard.\\
\section{Overview}
The AIDA \gls{tlu} provides timing and synchronization signals to test-beam readout hardware.\\
The hardware can provide an internally generated low-jitter 40~MHz clock or can accept and external clock reference.\\
It accepts the asynchronous trigger signals from up to six external sources, such as beam-scintillators, and generate synchronous signals (including global trigger or control signals) to send to up to four devices under tests. The logic function used to generate the trigger can be defined by the user among all the possible logic combinations of the inputs.\\
Depending on the chosen mode of operation, the \gls{tlu} can accept busy signals or other veto signals from \gls{dut}s and react accordingly, for instance avoinding any further trigger until all the busy signals have been de-asserted.\\
Whenever a global trigger is generated by the unit, a 48-bit time-stamp is attached to it. This time stamp is based on the 40~MHz clock. Additionally ???\\
The configuration parameters and data are sent and received via the \href{https://www.ohwr.org/projects/ipbus}{IPbus}. IPbus is a simple way to control and communicate TCA-based hardware via the UDP/IP protocol.
\section{FPGA}
The \gls{tlu} is shipped with an \gls{fpga} board already programmed with the latest version of the firmware needed to operate the unit.\\
The firmware developed at University of Bristol is targeted to work with the Enclustra AX3 board, which must be plugged onto a PM3 base, also produced by \href{http://www.enclustra.com/en/home/}{Enclustra}. The firmware is written on the \gls{fpga} using a \gls{jtag} interface. Typically a breakout board will be required to connect the Xilinx programming cable to the Enclustra PM3. All these components are included in the \gls{tlu} enclosure so the user can upload a new version of the firmware by simply connecting a \gls{usb}-B cable in the back panel of the unit.\\
At the time of writing this work\footnote{Oct 2017} the AX3 is the only \gls{fpga} for which a firmware has been developed. However, we plan to ship future versions of the \gls{tlu} with a custom made \gls{fpga} designed by Samer Kilani.
\begin{alertinfo}{Note}
If the \gls{fpga} detects a programming cable connected it will not load the firmware from its memory after a power cycle.\\
It is recommended to leave the \gls{usb} cable disconnected from the back panel unless there is the intention to re-program the firmware.
\end{alertinfo}
\section{Power}
The \gls{tlu} requires 12~V to operate. Power can be provided using the circular jack on the back panel of the unit.\\
During normal operation the current drawn by the unit is about 0.5~A.
%\section{Preparation}
%Before powering the \gls{tlu} it is necessary to follow a few steps to ensure the board and the \gls{fpga} work correctly.\\
%
%Currently, it is recommended to use the following:
%\begin{itemize}
% \item MA-PM3-W-R5: Mars PM3 base board
% \item MA-AX3-35-1I-D8-R3: Marx AX3 module (hosts a Xilinx XC7A35T-1CSG324I )
% \item MA-PM3-ACC-BASE: Accessory kit, including a \gls{jtag} breakout board to connect Xilinx programming cables. Also includes a 12~V power supply to power the PM3.
%\end{itemize}
%
%\section{I/O voltage setting}
%The I/O pins of the PM3 can be configured to operate at 2.5~V or 3.3~V; the factory default is 2.5~V but the \brd requires 3.3~V logic. The user should make sure to select the appropriate voltage by operating on DIP-switch CFG-A/S1200 (pin 1 set to ON).\\For reference, a top view of the board is provided in the appendix at page~\pageref{ch:appendix}.\\
%\begin{alertinfo}{Warning}
% Please double check the PM3 board manual for the correct way to change the I/O voltage setting. Enclustra has been changing their hardware recently.
%\end{alertinfo}
%
%\section{Xilinx programming cable}
%The \gls{jtag} pins on the PM3 are located on the header J800 (20-way, 2.54~mm pitch). The breakout board provided by Enclustra sits on top of the header and connects the pins to a 14-way Molex milli-grid header so that it is possible to plug the Xiling programming cable directly onto it. However, when the \brd is mounted on a base plate as shown in figure~\ref{fig:TLUplate}, the breakout board has to be detached from the PM3 because it interferes with the mounting screws.\\
%The connection between J800 and the breakout can be achieved by using two standard 20-way \gls{idc} cables as shown in figure~\ref{fig:XilinxCable}.
%\begin{figure}[h]
% \centering
% \includegraphics[width=.50\textwidth]{./Images/TLU_plate.jpg}
% \caption{\brd and PM3 mounted on a base plate: in this configuration it is not possible to install the breakout board on the PM3 because the mountings screws are in the way.}\label{fig:TLUplate}
%\end{figure}
%\begin{figure}
% \centering
% \includegraphics[width=.80\textwidth]{./Images/XilinxCable.jpg}
% \caption{Connecting the Xilinx programming cable to the PM3 in an ugly (but effective) way.}\label{fig:XilinxCable}
%\end{figure}
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\chapter{Preparation}\label{ch:preparation}
Before powering the \gls{tlu} it is necessary to follow a few steps to ensure the board and the \gls{fpga} work correctly.\\
The \brd is designed to plug onto a carrier \gls{fpga} board like any other \gls{fmc} mezzanine board, although its form factor does not comply with the ANSI-VITA-57-1 standard.\\
The firmware developed at University of Bristol is targeted to work with the Enclustra AX3 board, which must be plugged onto a PM3 base, also produced by \href{http://www.enclustra.com/en/home/}{Enclustra}. The firmware is written on the \gls{fpga} using a \gls{jtag} interface. Typically a breakout board will be required to connect the Xilinx programming cable to the Enclustra PM3.\\
Currently, it is recommended to use the following:
\begin{itemize}
\item MA-PM3-W-R5: Mars PM3 base board
\item MA-AX3-35-1I-D8-R3: Marx AX3 module (hosts a Xilinx XC7A35T-1CSG324I )
\item MA-PM3-ACC-BASE: Accessory kit, including a \gls{jtag} breakout board to connect Xilinx programming cables. Also includes a 12~V power supply to power the PM3.
\end{itemize}
\section{I/O voltage setting}
The I/O pins of the PM3 can be configured to operate at 2.5~V or 3.3~V; the factory default is 2.5~V but the \brd requires 3.3~V logic. The user should make sure to select the appropriate voltage by operating on DIP-switch CFG-A/S1200 (pin 1 set to ON).\\For reference, a top view of the board is provided in the appendix at page~\pageref{ch:appendix}.\\
\begin{alertinfo}{Warning}
Please double check the PM3 board manual for the correct way to change the I/O voltage setting. Enclustra has been changing their hardware recently.
\end{alertinfo}
\section{Xilinx programming cable}
The \gls{jtag} pins on the PM3 are located on the header J800 (20-way, 2.54~mm pitch). The breakout board provided by Enclustra sits on top of the header and connects the pins to a 14-way Molex milli-grid header so that it is possible to plug the Xiling programming cable directly onto it. However, when the \brd is mounted on a base plate as shown in figure~\ref{fig:TLUplate}, the breakout board has to be detached from the PM3 because it interferes with the mounting screws.\\
The connection between J800 and the breakout can be achieved by using two standard 20-way \gls{idc} cables as shown in figure~\ref{fig:XilinxCable}.
\begin{figure}[h]
\centering
\includegraphics[width=.50\textwidth]{./Images/TLU_plate.jpg}
\caption{\brd and PM3 mounted on a base plate: in this configuration it is not possible to install the breakout board on the PM3 because the mountings screws are in the way.}\label{fig:TLUplate}
\end{figure}
\begin{figure}
\centering
\includegraphics[width=.80\textwidth]{./Images/XilinxCable.jpg}
\caption{Connecting the Xilinx programming cable to the PM3 in an ugly (but effective) way.}\label{fig:XilinxCable}
\end{figure}
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\chapter{Clock}\label{ch:clock}
The \gls{tlu} can use various sources to produce a stable 40~MHz clock\footnote{For some applications a 50~MHz clock will be required instead}. A \gls{lvpecl} crystal provides the reference 50~MHz clock for a Si5345A jitter attenuator. The Si5345A can accept up to four clock sources and use them to generate the required output clocks.\\
In \brd the possible sources are: differential LEMO connector LM1\_9, one of the four \gls{hdmi} connectors (\verb|HDMI4|), a \gls{cdr} chip connected to the \gls{sfp} cage. The fourht input is used to provide a zero-delay feedback loop.\\
The low-jitter clock generated by the Si5345A can be distributed to up to ten recipients. In the \gls{tlu} these are: the four \gls{dut}s via \gls{hdmi} connectors, the differential LEMO cable, the \gls{fpga}, connector J1 as a differential pair (pins 4 and 6) and as a single ended signal (pin 8). The final output is connected to the zero-delay feedback loop.\\
The \gls{dut}s can receive the clock either from the Si5435A or directly from the \gls{fpga}: when provided by the clock generator, the signal name is \verb|CLK\_TO\_DUT| and is enabled by signal \verb|ENABLE_CLK_TO_DUT|; when the signal is provided directly from the \gls{fpga} the line used is \verb|DUT_CLK_FROM_FPGA| and is enabled by \verb|ENABLE_DUT_CLK_FROM_FPGA|.\\
The firmware uses the clock generated by the Si5345A except for the block \verb|enclustra_ax3_pm3_infra| which relies on a crystal mounted on the Enclustra board to provide the IPBus functionalities (in this way, at power up the board can communicate via IPBus even if the Si5345A is not configured).
\section{Input selection}
The Si5345 has four inputs that can be selected to provide the clock alignment; the selection can be automatic or user-defined. For further details on this aspect the user should consult the chip documentation.
\begin{table}[]
\small
\centering
\caption{Si5345 Input Selection Configuration.}
\label{tab:si5345inputs}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Register Name} & \textbf{Hex Address {[}Bit Field{]}} & \textbf{Function} \\ \hline
CLK\_SWITCH\_MODE & 0x0536{[}1:0{]} & \begin{tabular}[c]{@{}l@{}}Selects manual or automatic switching modes.\\ Automatic mode can be revertive or non-revertive.\\ Selections are the following:\\00 Manual\\01 Automatic non-revertive\\02 Automatic revertive\\03 Reserved\end{tabular} \\ \hline
IN\_SEL\_REGCTRL & 0x052A {[}0{]} & \begin{tabular}[c]{@{}l@{}}0 for pin controlled clock selection\\ 1 for register controlled clock selection\end{tabular} \\ \hline
IN\_SEL & 0x052A {[}2:1{]} & \begin{tabular}[c]{@{}l@{}}0 for IN0\\ 1 for IN1\\ 2 for IN2\\ 3 for IN3 (or FB\_IN)\end{tabular} \\ \hline
\end{tabular}
\end{table}
\section{Logic clocks registers}\label{ch:logicClock}
LogicClocksCSR: in the new TLU the selection of the clock source is done by programming the Si5345. As a consequence, there is no reason to write to this register. Reading it back returns the status of the PLL on bit 0, so this should read 0x1.
\ No newline at end of file
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# firmware_AIDA
Firmware for the AIDA TLU Hardware
This repository contains the VHL used to generate the firmware for the AIDA TLU, both versions V1C (T-shaped pcb) and V1E (rectangular PCB; the one most likely to be used outside the UoB lab).
# Scripts
The repository also contains Python scripts used to test the hardware. These scripts rely on a few libraries not linked here, so they are unlikely to work "out of the box".
# EUDAQ2
The best way to operate on the TLU is by using the EUDAQ2 tools (provide link!).
# Building Firmware
The master firmware uses the [ipbb](https://github.com/ipbus/ipbb) build tool, and requires the ipbus system firmware.
Set up the environment for Xilinx Vivado, then:
mkdir work
cd work
git clone git@github.com:ipbus/ipbb.git
( ... or curl -L https://github.com/ipbus/ipbb/archive/v0.2.5.tar.gz | tar xvz )
source ipbb/env.sh
ipbb init build
cd build
ipbb add git https://github.com/ipbus/ipbus-firmware.git -b enhancement/28
ipbb add git git@github.com:DavidCussans/firmware_AIDA.git
ipbb proj create vivado TLU_1e firmware_AIDA:projects/TLU_v1e -t top_tlu_1e_a35.dep
cd proj/TLU_1e
ipbb vivado project
# Set correct file as design "top"
vivado -mode tcl -nojournal -nolog -notrace -source ../../src/firmware_AIDA/projects/TLU_v1e/firmware/cfg/set_top.tcl top/top.xpr
# Edit the files in the IPBus repostitory to expose the 200MHz clock
sed -i 's/onehz);/onehz); clk_200_o<=clk200;/' ../../src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd
sed -i 's/clk125_o: out std_logic/clk125_o, clk_200_o: out std_logic/' ../../src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd
# Comment out the cfg signals in the IPBus constraints file enclustra_ax3_pm3.tcl
pushd ../../src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf
patch < ../../../../../../../firmware_AIDA/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.patch
# In order to generate the VHDL to decode the addresses follow the instructions at https://ipbus.web.cern.ch/ipbus/doc/user/html/firmware/hwDevInstructions.html
pushd firmware_AIDA/projects/TLU_v1e/addr_table
/opt/cactus/bin/uhal/tools/gen_ipbus_addr_decode -v TLUaddrmap.xml
#copy resulting file ( ipbus_decode_TLUaddrmap.vhd ) to work/build/src/firmware_AIDA/projects/TLU_v1e/firmware/hdl/
cp ipbus_decode_TLUaddrmap.vhd ../firmware/hdl/
ipbb vivado impl
ipbb vivado bitfile
ipbb vivado package
deactivate
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[Dolphin]
Timestamp=2017,2,17,15,3,7
ViewMode=1
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# Si538x/4x Registers Export
#
# Part: Si5345
# Project File: P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel_c\physical\ClockGen\TLU_Si5345-RevB-NEWTLU00-Project.slabtimeproj
# Design ID: NEWTLU01
# Includes Pre/Post Download Control Register Writes: Yes
# Die Revision: A2
# Creator: ClockBuilder Pro v2.12.1 [2016-12-15]
# Created On: 2017-02-17 15:16:26 GMT+00:00
Address,Data
0x0B24,0xD8
0x0B25,0x00
0x000B,0x68
0x0016,0x02
0x0017,0x1C
0x0018,0x00
0x0019,0xDD
0x001A,0xDF
0x002B,0x02
0x002C,0x0F
0x002D,0x55
0x002E,0x37
0x002F,0x00
0x0030,0x37
0x0031,0x00
0x0032,0x37
0x0033,0x00
0x0034,0x37
0x0035,0x00
0x0036,0x37
0x0037,0x00
0x0038,0x37
0x0039,0x00
0x003A,0x37
0x003B,0x00
0x003C,0x37
0x003D,0x00
0x003F,0xFF
0x0040,0x04
0x0041,0x0C
0x0042,0x0C
0x0043,0x0C
0x0044,0x0C
0x0045,0x0C
0x0046,0x32
0x0047,0x32
0x0048,0x32
0x0049,0x32
0x004A,0x32
0x004B,0x32
0x004C,0x32
0x004D,0x32
0x004E,0x55
0x004F,0x55
0x0051,0x03
0x0052,0x03
0x0053,0x03
0x0054,0x03
0x0055,0x03
0x0056,0x03
0x0057,0x03
0x0058,0x03
0x0059,0xFF
0x005A,0x00
0x005B,0x00
0x005C,0x00
0x005D,0x01
0x005E,0x00
0x005F,0x00
0x0060,0x00
0x0061,0x01
0x0062,0x00
0x0063,0x00
0x0064,0x00
0x0065,0x01
0x0066,0x00
0x0067,0x00
0x0068,0x00
0x0069,0x01
0x0092,0x00
0x0093,0x00
0x0095,0x00
0x0096,0x00
0x0098,0x00
0x009A,0x02
0x009B,0x30
0x009D,0x00
0x009E,0x20
0x00A0,0x00
0x00A2,0x02
0x00A8,0x89
0x00A9,0x70
0x00AA,0x07
0x00AB,0x00
0x00AC,0x00
0x0102,0x01
0x0108,0x06
0x0109,0x09
0x010A,0x33
0x010B,0x00
0x010D,0x06
0x010E,0x09
0x010F,0x33
0x0110,0x00
0x0112,0x06
0x0113,0x09
0x0114,0x33
0x0115,0x00
0x0117,0x06
0x0118,0x09
0x0119,0x33
0x011A,0x00
0x011C,0x06
0x011D,0x09
0x011E,0x33
0x011F,0x00
0x0121,0x06
0x0122,0x09
0x0123,0x33
0x0124,0x00
0x0126,0x06
0x0127,0x09
0x0128,0x33
0x0129,0x00
0x012B,0x06
0x012C,0x09
0x012D,0x33
0x012E,0x00
0x0130,0x06
0x0131,0x09
0x0132,0x33
0x0133,0x00
0x013A,0x06
0x013B,0xCC
0x013C,0x00
0x013D,0x00
0x013F,0x00
0x0140,0x00
0x0141,0x40
0x0142,0xFF
0x0202,0x00
0x0203,0x00
0x0204,0x00
0x0205,0x00
0x0206,0x00
0x0208,0x19
0x0209,0x00
0x020A,0x00
0x020B,0x00
0x020C,0x00
0x020D,0x00
0x020E,0x01
0x020F,0x00
0x0210,0x00
0x0211,0x00
0x0212,0x19
0x0213,0x00
0x0214,0x00
0x0215,0x00
0x0216,0x00
0x0217,0x00
0x0218,0x01
0x0219,0x00
0x021A,0x00
0x021B,0x00
0x021C,0x19
0x021D,0x00
0x021E,0x00
0x021F,0x00
0x0220,0x00
0x0221,0x00
0x0222,0x01
0x0223,0x00
0x0224,0x00
0x0225,0x00
0x0226,0x19
0x0227,0x00
0x0228,0x00
0x0229,0x00
0x022A,0x00
0x022B,0x00
0x022C,0x01
0x022D,0x00
0x022E,0x00
0x022F,0x00
0x0231,0x01
0x0232,0x01
0x0233,0x01
0x0234,0x01
0x0235,0x00
0x0236,0x00
0x0237,0x00
0x0238,0x00
0x0239,0xA9
0x023A,0x00
0x023B,0x00
0x023C,0x00
0x023D,0x00
0x023E,0xA0
0x024A,0x00
0x024B,0x00
0x024C,0x00
0x024D,0x00
0x024E,0x00
0x024F,0x00
0x0250,0x00
0x0251,0x00
0x0252,0x00
0x0253,0x00
0x0254,0x00
0x0255,0x00
0x0256,0x00
0x0257,0x00
0x0258,0x00
0x0259,0x00
0x025A,0x00
0x025B,0x00
0x025C,0x00
0x025D,0x00
0x025E,0x00
0x025F,0x00
0x0260,0x00
0x0261,0x00
0x0262,0x00
0x0263,0x00
0x0264,0x00
0x0268,0x00
0x0269,0x00
0x026A,0x00
0x026B,0x4E
0x026C,0x45
0x026D,0x57
0x026E,0x54
0x026F,0x4C
0x0270,0x55
0x0271,0x30
0x0272,0x31
0x0302,0x00
0x0303,0x00
0x0304,0x00
0x0305,0x80
0x0306,0x54
0x0307,0x00
0x0308,0x00
0x0309,0x00
0x030A,0x00
0x030B,0x80
0x030C,0x00
0x030D,0x00
0x030E,0x00
0x030F,0x00
0x0310,0x00
0x0311,0x00
0x0312,0x00
0x0313,0x00
0x0314,0x00
0x0315,0x00
0x0316,0x00
0x0317,0x00
0x0318,0x00
0x0319,0x00
0x031A,0x00
0x031B,0x00
0x031C,0x00
0x031D,0x00
0x031E,0x00
0x031F,0x00
0x0320,0x00
0x0321,0x00
0x0322,0x00
0x0323,0x00
0x0324,0x00
0x0325,0x00
0x0326,0x00
0x0327,0x00
0x0328,0x00
0x0329,0x00
0x032A,0x00
0x032B,0x00
0x032C,0x00
0x032D,0x00
0x032E,0x00
0x032F,0x00
0x0330,0x00
0x0331,0x00
0x0332,0x00
0x0333,0x00
0x0334,0x00
0x0335,0x00
0x0336,0x00
0x0337,0x00
0x0338,0x00
0x0339,0x1F
0x033B,0x00
0x033C,0x00
0x033D,0x00
0x033E,0x00
0x033F,0x00
0x0340,0x00
0x0341,0x00
0x0342,0x00
0x0343,0x00
0x0344,0x00
0x0345,0x00
0x0346,0x00
0x0347,0x00
0x0348,0x00
0x0349,0x00
0x034A,0x00
0x034B,0x00
0x034C,0x00
0x034D,0x00
0x034E,0x00
0x034F,0x00
0x0350,0x00
0x0351,0x00
0x0352,0x00
0x0353,0x00
0x0354,0x00
0x0355,0x00
0x0356,0x00
0x0357,0x00
0x0358,0x00
0x0359,0x00
0x035A,0x00
0x035B,0x00
0x035C,0x00
0x035D,0x00
0x035E,0x00
0x035F,0x00
0x0360,0x00
0x0361,0x00
0x0362,0x00
0x0487,0x00
0x0502,0x01
0x0508,0x14
0x0509,0x23
0x050A,0x0C
0x050B,0x0B
0x050C,0x03
0x050D,0x3F
0x050E,0x17
0x050F,0x2B
0x0510,0x09
0x0511,0x08
0x0512,0x03
0x0513,0x3F
0x0515,0x00
0x0516,0x00
0x0517,0x00
0x0518,0x00
0x0519,0xA4
0x051A,0x02
0x051B,0x00
0x051C,0x00
0x051D,0x00
0x051E,0x00
0x051F,0x80
0x0521,0x21
0x052A,0x05
0x052B,0x01
0x052C,0x0F
0x052D,0x03
0x052E,0x19
0x052F,0x19
0x0531,0x00
0x0532,0x42
0x0533,0x03
0x0534,0x00
0x0535,0x00
0x0536,0x0C
0x0537,0x00
0x0538,0x00
0x0539,0x00
0x0802,0x35
0x0803,0x05
0x0804,0x00
0x090E,0x02
0x0943,0x00
0x0949,0x0F
0x094A,0x0F
0x0A02,0x00
0x0A03,0x01
0x0A04,0x01
0x0A05,0x01
0x0B44,0x2F
0x0B46,0x00
0x0B47,0x00
0x0B48,0x00
0x0B4A,0x1E
0x0514,0x01
0x001C,0x01
0x0B24,0xDB
0x0B25,0x02
AIDA_tlu/bitFiles/TLU_CLK_Config_BKP.txt 0 → 100644
View file @ ccc18cf9
# Si538x/4x Registers Export
#
# Part: Si5345
# Project File: P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel_c\physical\ClockGen\TLU_Si5345-RevB-NEWTLU00-Project.slabtimeproj
# Design ID: NEWTLU00
# Includes Pre/Post Download Control Register Writes: Yes
# Die Revision: A2
# Creator: ClockBuilder Pro v2.12.1 [2016-12-15]
# Created On: 2017-02-07 18:25:57 GMT+00:00
Address,Data
0x0B24,0xD8
0x0B25,0x00
0x000B,0x68
0x0016,0x02
0x0017,0x1C
0x0018,0xFF
0x0019,0xFF
0x001A,0xFF
0x002B,0x02
0x002C,0x00
0x002D,0x00
0x002E,0x00
0x002F,0x00
0x0030,0x00
0x0031,0x00
0x0032,0x00
0x0033,0x00
0x0034,0x00
0x0035,0x00
0x0036,0x00
0x0037,0x00
0x0038,0x00
0x0039,0x00
0x003A,0x00
0x003B,0x00
0x003C,0x00
0x003D,0x00
0x003F,0x00
0x0040,0x04
0x0041,0x00
0x0042,0x00
0x0043,0x00
0x0044,0x00
0x0045,0x0C
0x0046,0x00
0x0047,0x00
0x0048,0x00
0x0049,0x00
0x004A,0x00
0x004B,0x00
0x004C,0x00
0x004D,0x00
0x004E,0x00
0x004F,0x00
0x0051,0x00
0x0052,0x00
0x0053,0x00
0x0054,0x00
0x0055,0x00
0x0056,0x00
0x0057,0x00
0x0058,0x00
0x0059,0x00
0x005A,0x00
0x005B,0x00
0x005C,0x00
0x005D,0x00
0x005E,0x00
0x005F,0x00
0x0060,0x00
0x0061,0x00
0x0062,0x00
0x0063,0x00
0x0064,0x00
0x0065,0x00
0x0066,0x00
0x0067,0x00
0x0068,0x00
0x0069,0x00
0x0092,0x00
0x0093,0x00
0x0095,0x00
0x0096,0x00
0x0098,0x00
0x009A,0x00
0x009B,0x00
0x009D,0x00
0x009E,0x00
0x00A0,0x00
0x00A2,0x00
0x00A8,0x00
0x00A9,0x00
0x00AA,0x00
0x00AB,0x00
0x00AC,0x00
0x0102,0x01
0x0108,0x06
0x0109,0x09
0x010A,0x33
0x010B,0x00
0x010D,0x06
0x010E,0x09
0x010F,0x33
0x0110,0x00
0x0112,0x06
0x0113,0x09
0x0114,0x33
0x0115,0x00
0x0117,0x06
0x0118,0x09
0x0119,0x33
0x011A,0x00
0x011C,0x06
0x011D,0x09
0x011E,0x33
0x011F,0x00
0x0121,0x06
0x0122,0x09
0x0123,0x33
0x0124,0x00
0x0126,0x06
0x0127,0x09
0x0128,0x33
0x0129,0x00
0x012B,0x06
0x012C,0x09
0x012D,0x33
0x012E,0x00
0x0130,0x06
0x0131,0x09
0x0132,0x33
0x0133,0x00
0x013A,0x06
0x013B,0xCC
0x013C,0x00
0x013D,0x00
0x013F,0x00
0x0140,0x00
0x0141,0x40
0x0142,0xFF
0x0202,0x00
0x0203,0x00
0x0204,0x00
0x0205,0x00
0x0206,0x00
0x0208,0x00
0x0209,0x00
0x020A,0x00
0x020B,0x00
0x020C,0x00
0x020D,0x00
0x020E,0x00
0x020F,0x00
0x0210,0x00
0x0211,0x00
0x0212,0x00
0x0213,0x00
0x0214,0x00
0x0215,0x00
0x0216,0x00
0x0217,0x00
0x0218,0x00
0x0219,0x00
0x021A,0x00
0x021B,0x00
0x021C,0x00
0x021D,0x00
0x021E,0x00
0x021F,0x00
0x0220,0x00
0x0221,0x00
0x0222,0x00
0x0223,0x00
0x0224,0x00
0x0225,0x00
0x0226,0x00
0x0227,0x00
0x0228,0x00
0x0229,0x00
0x022A,0x00
0x022B,0x00
0x022C,0x00
0x022D,0x00
0x022E,0x00
0x022F,0x00
0x0231,0x01
0x0232,0x01
0x0233,0x01
0x0234,0x01
0x0235,0x00
0x0236,0x00
0x0237,0x00
0x0238,0x00
0x0239,0xA9
0x023A,0x00
0x023B,0x00
0x023C,0x00
0x023D,0x00
0x023E,0xA0
0x024A,0x00
0x024B,0x00
0x024C,0x00
0x024D,0x00
0x024E,0x00
0x024F,0x00
0x0250,0x00
0x0251,0x00
0x0252,0x00
0x0253,0x00
0x0254,0x00
0x0255,0x00
0x0256,0x00
0x0257,0x00
0x0258,0x00
0x0259,0x00
0x025A,0x00
0x025B,0x00
0x025C,0x00
0x025D,0x00
0x025E,0x00
0x025F,0x00
0x0260,0x00
0x0261,0x00
0x0262,0x00
0x0263,0x00
0x0264,0x00
0x0268,0x00
0x0269,0x00
0x026A,0x00
0x026B,0x4E
0x026C,0x45
0x026D,0x57
0x026E,0x54
0x026F,0x4C
0x0270,0x55
0x0271,0x30
0x0272,0x30
0x0302,0x00
0x0303,0x00
0x0304,0x00
0x0305,0x80
0x0306,0x54
0x0307,0x00
0x0308,0x00
0x0309,0x00
0x030A,0x00
0x030B,0x80
0x030C,0x00
0x030D,0x00
0x030E,0x00
0x030F,0x00
0x0310,0x00
0x0311,0x00
0x0312,0x00
0x0313,0x00
0x0314,0x00
0x0315,0x00
0x0316,0x00
0x0317,0x00
0x0318,0x00
0x0319,0x00
0x031A,0x00
0x031B,0x00
0x031C,0x00
0x031D,0x00
0x031E,0x00
0x031F,0x00
0x0320,0x00
0x0321,0x00
0x0322,0x00
0x0323,0x00
0x0324,0x00
0x0325,0x00
0x0326,0x00
0x0327,0x00
0x0328,0x00
0x0329,0x00
0x032A,0x00
0x032B,0x00
0x032C,0x00
0x032D,0x00
0x032E,0x00
0x032F,0x00
0x0330,0x00
0x0331,0x00
0x0332,0x00
0x0333,0x00
0x0334,0x00
0x0335,0x00
0x0336,0x00
0x0337,0x00
0x0338,0x00
0x0339,0x1F
0x033B,0x00
0x033C,0x00
0x033D,0x00
0x033E,0x00
0x033F,0x00
0x0340,0x00
0x0341,0x00
0x0342,0x00
0x0343,0x00
0x0344,0x00
0x0345,0x00
0x0346,0x00
0x0347,0x00
0x0348,0x00
0x0349,0x00
0x034A,0x00
0x034B,0x00
0x034C,0x00
0x034D,0x00
0x034E,0x00
0x034F,0x00
0x0350,0x00
0x0351,0x00
0x0352,0x00
0x0353,0x00
0x0354,0x00
0x0355,0x00
0x0356,0x00
0x0357,0x00
0x0358,0x00
0x0359,0x00
0x035A,0x00
0x035B,0x00
0x035C,0x00
0x035D,0x00
0x035E,0x00
0x035F,0x00
0x0360,0x00
0x0361,0x00
0x0362,0x00
0x0487,0x00
0x0502,0x01
0x0508,0x00
0x0509,0x00
0x050A,0x00
0x050B,0x00
0x050C,0x00
0x050D,0x00
0x050E,0x00
0x050F,0x00
0x0510,0x00
0x0511,0x00
0x0512,0x00
0x0513,0x00
0x0515,0x00
0x0516,0x00
0x0517,0x00
0x0518,0x00
0x0519,0x00
0x051A,0x00
0x051B,0x00
0x051C,0x00
0x051D,0x00
0x051E,0x00
0x051F,0x00
0x0521,0x21
0x052A,0x00
0x052B,0x01
0x052C,0x0F
0x052D,0x03
0x052E,0x00
0x052F,0x00
0x0531,0x00
0x0532,0x00
0x0533,0x04
0x0534,0x00
0x0535,0x01
0x0536,0x0E
0x0537,0x00
0x0538,0x00
0x0539,0x00
0x0802,0x35
0x0803,0x05
0x0804,0x01
0x090E,0x02
0x0943,0x00
0x0949,0x00
0x094A,0x00
0x0A02,0x00
0x0A03,0x01
0x0A04,0x01
0x0A05,0x01
0x0B44,0x0F
0x0B46,0x00
0x0B47,0x00
0x0B48,0x0F
0x0B4A,0x1E
0x0514,0x01
0x001C,0x01
0x0B24,0xDB
0x0B25,0x02
AIDA_tlu/bitFiles/TLU_CLK_Config_v1e.txt 0 → 100644
View file @ ccc18cf9
# Si538x/4x Registers Export
#
# Part: Si5345
# Project File: P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel_c\physical\ClockGen\TLU_Si5345-RevB-NEWTLU00-Project.slabtimeproj
# Design ID: TLU1E_01
# Includes Pre/Post Download Control Register Writes: Yes
# Die Revision: A2
# Creator: ClockBuilder Pro v2.12.1 [2016-12-15]
# Created On: 2017-08-24 13:37:41 GMT+01:00
Address,Data
0x0B24,0xD8
0x0B25,0x00
0x000B,0x68
0x0016,0x02
0x0017,0x1C
0x0018,0x88
0x0019,0xDD
0x001A,0xDF
0x002B,0x02
0x002C,0x07
0x002D,0x15
0x002E,0x37
0x002F,0x00
0x0030,0x37
0x0031,0x00
0x0032,0x37
0x0033,0x00
0x0034,0x00
0x0035,0x00
0x0036,0x37
0x0037,0x00
0x0038,0x37
0x0039,0x00
0x003A,0x37
0x003B,0x00
0x003C,0x00
0x003D,0x00
0x003F,0x77
0x0040,0x04
0x0041,0x0C
0x0042,0x0C
0x0043,0x0C
0x0044,0x00
0x0045,0x0C
0x0046,0x32
0x0047,0x32
0x0048,0x32
0x0049,0x00
0x004A,0x32
0x004B,0x32
0x004C,0x32
0x004D,0x00
0x004E,0x55
0x004F,0x05
0x0051,0x03
0x0052,0x03
0x0053,0x03
0x0054,0x00
0x0055,0x03
0x0056,0x03
0x0057,0x03
0x0058,0x00
0x0059,0x3F
0x005A,0xCC
0x005B,0xCC
0x005C,0xCC
0x005D,0x00
0x005E,0xCC
0x005F,0xCC
0x0060,0xCC
0x0061,0x00
0x0062,0xCC
0x0063,0xCC
0x0064,0xCC
0x0065,0x00
0x0066,0x00
0x0067,0x00
0x0068,0x00
0x0069,0x00
0x0092,0x00
0x0093,0x00
0x0095,0x00
0x0096,0x00
0x0098,0x00
0x009A,0x02
0x009B,0x30
0x009D,0x00
0x009E,0x20
0x00A0,0x00
0x00A2,0x02
0x00A8,0x89
0x00A9,0x70
0x00AA,0x07
0x00AB,0x00
0x00AC,0x00
0x0102,0x01
0x0108,0x06
0x0109,0x09
0x010A,0x33
0x010B,0x00
0x010D,0x06
0x010E,0x09
0x010F,0x33
0x0110,0x00
0x0112,0x06
0x0113,0x09
0x0114,0x33
0x0115,0x00
0x0117,0x06
0x0118,0x09
0x0119,0x33
0x011A,0x00
0x011C,0x06
0x011D,0x09
0x011E,0x33
0x011F,0x00
0x0121,0x06
0x0122,0x09
0x0123,0x33
0x0124,0x00
0x0126,0x06
0x0127,0x09
0x0128,0x33
0x0129,0x00
0x012B,0x06
0x012C,0x09
0x012D,0x33
0x012E,0x00
0x0130,0x06
0x0131,0x09
0x0132,0x33
0x0133,0x00
0x013A,0x01
0x013B,0xCC
0x013C,0x00
0x013D,0x00
0x013F,0x00
0x0140,0x00
0x0141,0x40
0x0142,0xFF
0x0202,0x00
0x0203,0x00
0x0204,0x00
0x0205,0x00
0x0206,0x00
0x0208,0x14
0x0209,0x00
0x020A,0x00
0x020B,0x00
0x020C,0x00
0x020D,0x00
0x020E,0x01
0x020F,0x00
0x0210,0x00
0x0211,0x00
0x0212,0x14
0x0213,0x00
0x0214,0x00
0x0215,0x00
0x0216,0x00
0x0217,0x00
0x0218,0x01
0x0219,0x00
0x021A,0x00
0x021B,0x00
0x021C,0x14
0x021D,0x00
0x021E,0x00
0x021F,0x00
0x0220,0x00
0x0221,0x00
0x0222,0x01
0x0223,0x00
0x0224,0x00
0x0225,0x00
0x0226,0x00
0x0227,0x00
0x0228,0x00
0x0229,0x00
0x022A,0x00
0x022B,0x00
0x022C,0x00
0x022D,0x00
0x022E,0x00
0x022F,0x00
0x0231,0x01
0x0232,0x01
0x0233,0x01
0x0234,0x01
0x0235,0x00
0x0236,0x00
0x0237,0x00
0x0238,0x00
0x0239,0xA9
0x023A,0x00
0x023B,0x00
0x023C,0x00
0x023D,0x00
0x023E,0xA0
0x024A,0x00
0x024B,0x00
0x024C,0x00
0x024D,0x00
0x024E,0x00
0x024F,0x00
0x0250,0x00
0x0251,0x00
0x0252,0x00
0x0253,0x00
0x0254,0x00
0x0255,0x00
0x0256,0x00
0x0257,0x00
0x0258,0x00
0x0259,0x00
0x025A,0x00
0x025B,0x00
0x025C,0x00
0x025D,0x00
0x025E,0x00
0x025F,0x00
0x0260,0x00
0x0261,0x00
0x0262,0x00
0x0263,0x00
0x0264,0x00
0x0268,0x00
0x0269,0x00
0x026A,0x00
0x026B,0x54
0x026C,0x4C
0x026D,0x55
0x026E,0x31
0x026F,0x45
0x0270,0x5F
0x0271,0x30
0x0272,0x31
0x0302,0x00
0x0303,0x00
0x0304,0x00
0x0305,0x80
0x0306,0x54
0x0307,0x00
0x0308,0x00
0x0309,0x00
0x030A,0x00
0x030B,0x80
0x030C,0x00
0x030D,0x00
0x030E,0x00
0x030F,0x00
0x0310,0x00
0x0311,0x00
0x0312,0x00
0x0313,0x00
0x0314,0x00
0x0315,0x00
0x0316,0x00
0x0317,0x00
0x0318,0x00
0x0319,0x00
0x031A,0x00
0x031B,0x00
0x031C,0x00
0x031D,0x00
0x031E,0x00
0x031F,0x00
0x0320,0x00
0x0321,0x00
0x0322,0x00
0x0323,0x00
0x0324,0x00
0x0325,0x00
0x0326,0x00
0x0327,0x00
0x0328,0x00
0x0329,0x00
0x032A,0x00
0x032B,0x00
0x032C,0x00
0x032D,0x00
0x032E,0x00
0x032F,0x00
0x0330,0x00
0x0331,0x00
0x0332,0x00
0x0333,0x00
0x0334,0x00
0x0335,0x00
0x0336,0x00
0x0337,0x00
0x0338,0x00
0x0339,0x1F
0x033B,0x00
0x033C,0x00
0x033D,0x00
0x033E,0x00
0x033F,0x00
0x0340,0x00
0x0341,0x00
0x0342,0x00
0x0343,0x00
0x0344,0x00
0x0345,0x00
0x0346,0x00
0x0347,0x00
0x0348,0x00
0x0349,0x00
0x034A,0x00
0x034B,0x00
0x034C,0x00
0x034D,0x00
0x034E,0x00
0x034F,0x00
0x0350,0x00
0x0351,0x00
0x0352,0x00
0x0353,0x00
0x0354,0x00
0x0355,0x00
0x0356,0x00
0x0357,0x00
0x0358,0x00
0x0359,0x00
0x035A,0x00
0x035B,0x00
0x035C,0x00
0x035D,0x00
0x035E,0x00
0x035F,0x00
0x0360,0x00
0x0361,0x00
0x0362,0x00
0x0487,0x00
0x0502,0x01
0x0508,0x14
0x0509,0x23
0x050A,0x0C
0x050B,0x0B
0x050C,0x03
0x050D,0x3F
0x050E,0x17
0x050F,0x2B
0x0510,0x09
0x0511,0x08
0x0512,0x03
0x0513,0x3F
0x0515,0x00
0x0516,0x00
0x0517,0x00
0x0518,0x00
0x0519,0xA4
0x051A,0x02
0x051B,0x00
0x051C,0x00
0x051D,0x00
0x051E,0x00
0x051F,0x80
0x0521,0x21
0x052A,0x05
0x052B,0x01
0x052C,0x0F
0x052D,0x03
0x052E,0x19
0x052F,0x19
0x0531,0x00
0x0532,0x42
0x0533,0x03
0x0534,0x00
0x0535,0x00
0x0536,0x08
0x0537,0x00
0x0538,0x00
0x0539,0x00
0x0802,0x35
0x0803,0x05
0x0804,0x00
0x090E,0x02
0x0943,0x00
0x0949,0x07
0x094A,0x07
0x0A02,0x00
0x0A03,0x01
0x0A04,0x01
0x0A05,0x01
0x0B44,0x2F
0x0B46,0x00
0x0B47,0x00
0x0B48,0x08
0x0B4A,0x1E
0x0514,0x01
0x001C,0x01
0x0B24,0xDB
0x0B25,0x02
AIDA_tlu/bitFiles/TLU_CLK_Config_v1e_2.txt 0 → 100644
View file @ ccc18cf9
# Si538x/4x Registers Script
#
# Part: Si5345
# Project File: P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel_c\physical\ClockGen\Si5345-TLU1E_02.slabtimeproj
# Design ID: TLU1E_02
# Includes Pre/Post Download Control Register Writes: Yes
# Die Revision: A2
# Creator: ClockBuilder Pro v2.16.1 [2017-07-19]
# Created On: 2017-08-24 15:55:56 GMT+01:00
Address,Data
#
# Start configuration preamble
0x0B24,0xD8
0x0B25,0x00
0x0540,0x01
# End configuration preamble
#
# Delay 300 msec
# Delay is worst case time for device to complete any calibration
# that is running due to device state change previous to this script
# being processed.
#
# Start configuration registers
0x000B,0x68
0x0016,0x02
0x0017,0x1C
0x0018,0xFF
0x0019,0xFF
0x001A,0xFF
0x002B,0x02
0x002C,0x00
0x002D,0x00
0x002E,0x00
0x002F,0x00
0x0030,0x00
0x0031,0x00
0x0032,0x00
0x0033,0x00
0x0034,0x00
0x0035,0x00
0x0036,0x00
0x0037,0x00
0x0038,0x00
0x0039,0x00
0x003A,0x00
0x003B,0x00
0x003C,0x00
0x003D,0x00
0x003F,0x00
0x0040,0x04
0x0041,0x00
0x0042,0x00
0x0043,0x00
0x0044,0x00
0x0045,0x0C
0x0046,0x00
0x0047,0x00
0x0048,0x00
0x0049,0x00
0x004A,0x00
0x004B,0x00
0x004C,0x00
0x004D,0x00
0x004E,0x00
0x004F,0x00
0x0050,0x0F
0x0051,0x00
0x0052,0x00
0x0053,0x00
0x0054,0x00
0x0055,0x00
0x0056,0x00
0x0057,0x00
0x0058,0x00
0x0059,0x00
0x005A,0x00
0x005B,0x00
0x005C,0x00
0x005D,0x00
0x005E,0x00
0x005F,0x00
0x0060,0x00
0x0061,0x00
0x0062,0x00
0x0063,0x00
0x0064,0x00
0x0065,0x00
0x0066,0x00
0x0067,0x00
0x0068,0x00
0x0069,0x00
0x0092,0x00
0x0093,0x00
0x0095,0x00
0x0096,0x00
0x0098,0x00
0x009A,0x00
0x009B,0x00
0x009D,0x00
0x009E,0x00
0x00A0,0x00
0x00A2,0x00
0x00A8,0x00
0x00A9,0x00
0x00AA,0x00
0x00AB,0x00
0x00AC,0x00
0x0102,0x01
0x0108,0x06
0x0109,0x09
0x010A,0x33
0x010B,0x00
0x010D,0x06
0x010E,0x09
0x010F,0x33
0x0110,0x00
0x0112,0x06
0x0113,0x09
0x0114,0x33
0x0115,0x00
0x0117,0x06
0x0118,0x09
0x0119,0x33
0x011A,0x00
0x011C,0x06
0x011D,0x09
0x011E,0x33
0x011F,0x00
0x0121,0x06
0x0122,0x09
0x0123,0x33
0x0124,0x00
0x0126,0x06
0x0127,0x09
0x0128,0x33
0x0129,0x00
0x012B,0x06
0x012C,0x09
0x012D,0x33
0x012E,0x00
0x0130,0x06
0x0131,0x09
0x0132,0x33
0x0133,0x00
0x013A,0x06
0x013B,0x09
0x013C,0x33
0x013D,0x00
0x013F,0x00
0x0140,0x00
0x0141,0x40
0x0142,0xFF
0x0202,0x00
0x0203,0x00
0x0204,0x00
0x0205,0x00
0x0206,0x00
0x0208,0x00
0x0209,0x00
0x020A,0x00
0x020B,0x00
0x020C,0x00
0x020D,0x00
0x020E,0x00
0x020F,0x00
0x0210,0x00
0x0211,0x00
0x0212,0x00
0x0213,0x00
0x0214,0x00
0x0215,0x00
0x0216,0x00
0x0217,0x00
0x0218,0x00
0x0219,0x00
0x021A,0x00
0x021B,0x00
0x021C,0x00
0x021D,0x00
0x021E,0x00
0x021F,0x00
0x0220,0x00
0x0221,0x00
0x0222,0x00
0x0223,0x00
0x0224,0x00
0x0225,0x00
0x0226,0x00
0x0227,0x00
0x0228,0x00
0x0229,0x00
0x022A,0x00
0x022B,0x00
0x022C,0x00
0x022D,0x00
0x022E,0x00
0x022F,0x00
0x0231,0x01
0x0232,0x01
0x0233,0x01
0x0234,0x01
0x0235,0x00
0x0236,0x00
0x0237,0x00
0x0238,0x00
0x0239,0xA9
0x023A,0x00
0x023B,0x00
0x023C,0x00
0x023D,0x00
0x023E,0xA0
0x024A,0x00
0x024B,0x00
0x024C,0x00
0x024D,0x00
0x024E,0x00
0x024F,0x00
0x0250,0x00
0x0251,0x00
0x0252,0x00
0x0253,0x00
0x0254,0x00
0x0255,0x00
0x0256,0x00
0x0257,0x00
0x0258,0x00
0x0259,0x00
0x025A,0x00
0x025B,0x00
0x025C,0x00
0x025D,0x00
0x025E,0x00
0x025F,0x00
0x0260,0x00
0x0261,0x00
0x0262,0x00
0x0263,0x00
0x0264,0x00
0x0268,0x00
0x0269,0x00
0x026A,0x00
0x026B,0x54
0x026C,0x4C
0x026D,0x55
0x026E,0x31
0x026F,0x45
0x0270,0x5F
0x0271,0x30
0x0272,0x32
0x0302,0x00
0x0303,0x00
0x0304,0x00
0x0305,0x80
0x0306,0x54
0x0307,0x00
0x0308,0x00
0x0309,0x00
0x030A,0x00
0x030B,0x80
0x030C,0x00
0x030D,0x00
0x030E,0x00
0x030F,0x00
0x0310,0x00
0x0311,0x00
0x0312,0x00
0x0313,0x00
0x0314,0x00
0x0315,0x00
0x0316,0x00
0x0317,0x00
0x0318,0x00
0x0319,0x00
0x031A,0x00
0x031B,0x00
0x031C,0x00
0x031D,0x00
0x031E,0x00
0x031F,0x00
0x0320,0x00
0x0321,0x00
0x0322,0x00
0x0323,0x00
0x0324,0x00
0x0325,0x00
0x0326,0x00
0x0327,0x00
0x0328,0x00
0x0329,0x00
0x032A,0x00
0x032B,0x00
0x032C,0x00
0x032D,0x00
0x032E,0x00
0x032F,0x00
0x0330,0x00
0x0331,0x00
0x0332,0x00
0x0333,0x00
0x0334,0x00
0x0335,0x00
0x0336,0x00
0x0337,0x00
0x0338,0x00
0x0339,0x1F
0x033B,0x00
0x033C,0x00
0x033D,0x00
0x033E,0x00
0x033F,0x00
0x0340,0x00
0x0341,0x00
0x0342,0x00
0x0343,0x00
0x0344,0x00
0x0345,0x00
0x0346,0x00
0x0347,0x00
0x0348,0x00
0x0349,0x00
0x034A,0x00
0x034B,0x00
0x034C,0x00
0x034D,0x00
0x034E,0x00
0x034F,0x00
0x0350,0x00
0x0351,0x00
0x0352,0x00
0x0353,0x00
0x0354,0x00
0x0355,0x00
0x0356,0x00
0x0357,0x00
0x0358,0x00
0x0359,0x00
0x035A,0x00
0x035B,0x00
0x035C,0x00
0x035D,0x00
0x035E,0x00
0x035F,0x00
0x0360,0x00
0x0361,0x00
0x0362,0x00
0x0487,0x00
0x0502,0x01
0x0508,0x00
0x0509,0x00
0x050A,0x00
0x050B,0x00
0x050C,0x00
0x050D,0x00
0x050E,0x00
0x050F,0x00
0x0510,0x00
0x0511,0x00
0x0512,0x00
0x0513,0x00
0x0515,0x00
0x0516,0x00
0x0517,0x00
0x0518,0x00
0x0519,0x00
0x051A,0x00
0x051B,0x00
0x051C,0x00
0x051D,0x00
0x051E,0x00
0x051F,0x00
0x0521,0x21
0x052A,0x05
0x052B,0x01
0x052C,0x0F
0x052D,0x03
0x052E,0x00
0x052F,0x00
0x0531,0x00
0x0532,0x00
0x0533,0x04
0x0534,0x00
0x0535,0x01
0x0536,0x0C
0x0537,0x00
0x0538,0x00
0x0539,0x00
0x0802,0x35
0x0803,0x05
0x0804,0x01
0x090E,0x02
0x0943,0x00
0x0949,0x00
0x094A,0x00
0x0A02,0x00
0x0A03,0x01
0x0A04,0x01
0x0A05,0x01
0x0B44,0x0F
0x0B46,0x00
0x0B47,0x0F
0x0B48,0x0F
0x0B4A,0x1E
# End configuration registers
#
# Start configuration postamble
0x0514,0x01
0x001C,0x01
0x0540,0x00
0x0B24,0xDB
0x0B25,0x02
# End configuration postamble
AIDA_tlu/bitFiles/debug_nets.ltx 0 → 100644
View file @ ccc18cf9
<?xml version="1.0" encoding="UTF-8"?>
<probeData version="2" minor="0">
<probeset name="EDA_PROBESET" active="true">
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="0"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I5/trigger_input_loop[0].thresholdLUT/deserialized_data_i[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="1"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="8"/>
</probeOptions>
<nets>
<net name="I5/s_deserialized_threshold_data[0][7]"/>
<net name="I5/s_deserialized_threshold_data[0][6]"/>
<net name="I5/s_deserialized_threshold_data[0][5]"/>
<net name="I5/s_deserialized_threshold_data[0][4]"/>
<net name="I5/s_deserialized_threshold_data[0][3]"/>
<net name="I5/s_deserialized_threshold_data[0][2]"/>
<net name="I5/s_deserialized_threshold_data[0][1]"/>
<net name="I5/s_deserialized_threshold_data[0][0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="2"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="I10/cmp_coincidence_logic/triggers_i[5]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[4]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[3]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[2]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[1]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="3"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="I10/trigger_i[5]"/>
<net name="I10/trigger_i[4]"/>
<net name="I10/trigger_i[3]"/>
<net name="I10/trigger_i[2]"/>
<net name="I10/trigger_i[1]"/>
<net name="I10/trigger_i[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="4"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="triggers[5]"/>
<net name="triggers[4]"/>
<net name="triggers[3]"/>
<net name="triggers[2]"/>
<net name="triggers[1]"/>
<net name="triggers[0]"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="5"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="clk_ipb"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="6"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I5/trigger_input_loop[0].thresholdLUT/rising_edge_o"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="7"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I10/s_external_trigger_l"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="8"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="sysclk_40"/>
</nets>
</probe>
</probeset>
</probeData>
AIDA_tlu/bitFiles/debug_nets_abcd000a.ltx 0 → 100644
View file @ ccc18cf9
<?xml version="1.0" encoding="UTF-8"?>
<probeData version="2" minor="0">
<probeset name="EDA_PROBESET" active="true">
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="0"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="8"/>
</probeOptions>
<nets>
<net name="I5/s_deserialized_threshold_data[0][7]"/>
<net name="I5/s_deserialized_threshold_data[0][6]"/>
<net name="I5/s_deserialized_threshold_data[0][5]"/>
<net name="I5/s_deserialized_threshold_data[0][4]"/>
<net name="I5/s_deserialized_threshold_data[0][3]"/>
<net name="I5/s_deserialized_threshold_data[0][2]"/>
<net name="I5/s_deserialized_threshold_data[0][1]"/>
<net name="I5/s_deserialized_threshold_data[0][0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="1"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I5/s_threshold_previous_late_bit[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="2"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="I5/trigger_o[5]"/>
<net name="I5/trigger_o[4]"/>
<net name="I5/trigger_o[3]"/>
<net name="I5/trigger_o[2]"/>
<net name="I5/trigger_o[1]"/>
<net name="I5/trigger_o[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="3"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="5"/>
</probeOptions>
<nets>
<net name="I5/trigger_times_o[0][4]"/>
<net name="I5/trigger_times_o[0][3]"/>
<net name="I5/trigger_times_o[0][2]"/>
<net name="I5/trigger_times_o[0][1]"/>
<net name="I5/trigger_times_o[0][0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="4"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="I10/cmp_coincidence_logic/triggers_i[5]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[4]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[3]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[2]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[1]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="5"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="I10/trigger_i[5]"/>
<net name="I10/trigger_i[4]"/>
<net name="I10/trigger_i[3]"/>
<net name="I10/trigger_i[2]"/>
<net name="I10/trigger_i[1]"/>
<net name="I10/trigger_i[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="6"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="triggers[5]"/>
<net name="triggers[4]"/>
<net name="triggers[3]"/>
<net name="triggers[2]"/>
<net name="triggers[1]"/>
<net name="triggers[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="7"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I5/trigger_input_loop[0].thresholdLUT/deserialized_data_i[0]"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="8"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="clk_ipb"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="9"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I5/trigger_input_loop[0].thresholdLUT/rising_edge_o"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="10"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I10/s_external_trigger_l"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="11"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="sysclk_40"/>
</nets>
</probe>
</probeset>
</probeData>
AIDA_tlu/bitFiles/debug_nets_abcd000b.ltx 0 → 100644
View file @ ccc18cf9
<?xml version="1.0" encoding="UTF-8"?>
<probeData version="2" minor="0">
<probeset name="EDA_PROBESET" active="true">
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="0"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="8"/>
</probeOptions>
<nets>
<net name="I5/s_deserialized_threshold_data[0][7]"/>
<net name="I5/s_deserialized_threshold_data[0][6]"/>
<net name="I5/s_deserialized_threshold_data[0][5]"/>
<net name="I5/s_deserialized_threshold_data[0][4]"/>
<net name="I5/s_deserialized_threshold_data[0][3]"/>
<net name="I5/s_deserialized_threshold_data[0][2]"/>
<net name="I5/s_deserialized_threshold_data[0][1]"/>
<net name="I5/s_deserialized_threshold_data[0][0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="1"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I5/s_threshold_previous_late_bit[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="2"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="I5/trigger_o[5]"/>
<net name="I5/trigger_o[4]"/>
<net name="I5/trigger_o[3]"/>
<net name="I5/trigger_o[2]"/>
<net name="I5/trigger_o[1]"/>
<net name="I5/trigger_o[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="3"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="5"/>
</probeOptions>
<nets>
<net name="I5/trigger_times_o[0][4]"/>
<net name="I5/trigger_times_o[0][3]"/>
<net name="I5/trigger_times_o[0][2]"/>
<net name="I5/trigger_times_o[0][1]"/>
<net name="I5/trigger_times_o[0][0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="4"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="I10/cmp_coincidence_logic/triggers_i[5]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[4]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[3]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[2]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[1]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="5"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="I10/trigger_i[5]"/>
<net name="I10/trigger_i[4]"/>
<net name="I10/trigger_i[3]"/>
<net name="I10/trigger_i[2]"/>
<net name="I10/trigger_i[1]"/>
<net name="I10/trigger_i[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="6"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="triggers[5]"/>
<net name="triggers[4]"/>
<net name="triggers[3]"/>
<net name="triggers[2]"/>
<net name="triggers[1]"/>
<net name="triggers[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="7"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I5/trigger_input_loop[0].thresholdLUT/deserialized_data_i[0]"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="8"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="clk_ipb"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="9"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I5/trigger_input_loop[0].thresholdLUT/rising_edge_o"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="10"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I10/s_external_trigger_l"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="11"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="sysclk_40"/>
</nets>
</probe>
</probeset>
</probeData>
AIDA_tlu/bitFiles/debug_nets_abcd000d.ltx 0 → 100644
View file @ ccc18cf9
This diff is collapsed.
AIDA_tlu/bitFiles/debug_nets_abcd000e.ltx 0 → 100644
View file @ ccc18cf9
<?xml version="1.0" encoding="UTF-8"?>
<probeData version="2" minor="0">
<probeset name="EDA_PROBESET" active="true">
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="0"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I5/trigger_input_loop[0].thresholdLUT/deserialized_data_i[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="1"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="8"/>
</probeOptions>
<nets>
<net name="I5/s_deserialized_threshold_data[0][7]"/>
<net name="I5/s_deserialized_threshold_data[0][6]"/>
<net name="I5/s_deserialized_threshold_data[0][5]"/>
<net name="I5/s_deserialized_threshold_data[0][4]"/>
<net name="I5/s_deserialized_threshold_data[0][3]"/>
<net name="I5/s_deserialized_threshold_data[0][2]"/>
<net name="I5/s_deserialized_threshold_data[0][1]"/>
<net name="I5/s_deserialized_threshold_data[0][0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="2"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I5/s_threshold_previous_late_bit[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="3"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="I5/trigger_o[5]"/>
<net name="I5/trigger_o[4]"/>
<net name="I5/trigger_o[3]"/>
<net name="I5/trigger_o[2]"/>
<net name="I5/trigger_o[1]"/>
<net name="I5/trigger_o[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="4"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="5"/>
</probeOptions>
<nets>
<net name="I5/trigger_times_o[0][4]"/>
<net name="I5/trigger_times_o[0][3]"/>
<net name="I5/trigger_times_o[0][2]"/>
<net name="I5/trigger_times_o[0][1]"/>
<net name="I5/trigger_times_o[0][0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="5"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="I10/cmp_coincidence_logic/triggers_i[5]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[4]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[3]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[2]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[1]"/>
<net name="I10/cmp_coincidence_logic/triggers_i[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="6"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="I10/trigger_i[5]"/>
<net name="I10/trigger_i[4]"/>
<net name="I10/trigger_i[3]"/>
<net name="I10/trigger_i[2]"/>
<net name="I10/trigger_i[1]"/>
<net name="I10/trigger_i[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="7"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="postVetotrigger[5]"/>
<net name="postVetotrigger[4]"/>
<net name="postVetotrigger[3]"/>
<net name="postVetotrigger[2]"/>
<net name="postVetotrigger[1]"/>
<net name="postVetotrigger[0]"/>
</nets>
</probe>
<probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="8"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
</probeOptions>
<nets>
<net name="triggers[5]"/>
<net name="triggers[4]"/>
<net name="triggers[3]"/>
<net name="triggers[2]"/>
<net name="triggers[1]"/>
<net name="triggers[0]"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="9"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="clk_ipb"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="10"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I5/trigger_input_loop[0].thresholdLUT/rising_edge_o"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="11"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I10/s_external_trigger_l"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="12"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="I10/s_external_trigger_p"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="13"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="sysclk_40"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="BSCAN_SWITCH_INDEX" value="0"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="14"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="clk_8x_logic"/>
</nets>
</probe>
</probeset>
</probeData>
AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/cfg/lib_mappings.tcl 0 → 100644
View file @ ccc18cf9
set xlib $::env(XILINX_SIMLIBS)
vmap secureip $xlib/secureip
vmap unisim $xlib/unisim
vmap unimacro $xlib/unimacro
vmap unifast $xlib/unifast
vmap unisims_ver $xlib/unisims_ver
vmap unimacro_ver $xlib/unimacro_ver
vmap unifast_ver $xlib/unifast_ver
vmap simprims_ver $xlib/simprims_ver
AIDA_tlu/components/tlu/firmware/cgn/tlu_event_fifo.xci 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/GPL_doxygen_header.vhdl 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/Reg_2clks.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/SyncGenerator_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/TPx3Logic_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/TPx3_iface_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/coincidenceLogic_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/counterDownGated_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/counterWithReset_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/delayPulse4x_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterfaces_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/dut/DUTs_outputs.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/eventBuffer_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/eventFormatter_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/fmcTLU_pkg.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/fmcTLU_pkg_body.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/handshakes_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/ipbus_example.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/ipbus_fabric_sel.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/ipbus_slaves.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/led_stretcher.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/logic_clocks_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/registerCounter_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/serdes_1_to_n_SDR.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/single_pulse_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/stretchPulse4x_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/stretchPulse_rtl.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/sync_reg.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/test_inToOut.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/test_inputToOutput.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/test_toggleLines.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/testbench_clocks.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/testbench_myclocks.vhd 0 → 100644
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AIDA_tlu/components/tlu/firmware/hdl/top_enclustra_ax3_pm3.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/constraints/EUDET_dummy_constr.xdc 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/constraints/I2C_constr.xdc 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/constraints/enclustra_ax3_pm3.tcl 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/Dummy_DUT.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/Dummy_DUT_Toplevel.vhd 0 → 100755
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AIDA_tlu/legacy/EUDETdummy/hdl/Register_Controller.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/TLU_Address_Map.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/TLU_address_map_v0-2.vhdl 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/ZestSC1_Host.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/ZestSC1_Interfaces.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/clocks_7s_extphy_se.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/delay.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/delay_word.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/dtype.vhdl 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/enclustra_ax3_pm3_infra.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/eth_7s_rgmii.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/fmcTLU_pkg.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/fmcTLU_pkg_body.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_bit_ctrl.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_byte_ctrl.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_registers.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_top.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_addr_decode.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_decode_ipbus_example.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_decode_tlu.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_example.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_fabric_sel.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_slaves.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_ver.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/led_stretcher.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/logic_clocks_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/hdl/top_EUDET_dummy.vhd 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/scripts/EUDETdummy.py 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/scripts/EUDETdummyaddrmap.xml 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/scripts/EUDETdummyconnection.xml 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/scripts/EUDummy_testscript.py 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/scripts/initTLU.py 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/scripts/startDUMMY.sh 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/scripts/startEUDETdummy.py 0 → 100644
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AIDA_tlu/legacy/EUDETdummy/scripts/testTLU_script.py 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/DUTInterface_AIDA_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/DUTInterface_EUDET_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/DUTInterfaces_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/DUTInterfaces_rtl_BKP.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/DUTs_outputs.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/GPL_doxygen_header.vhdl 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/GPP_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/IODELAYCal_FSM_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/IPBusInterface_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/Reg_2clks.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/T0_Shutter_Iface_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/TPx3Logic_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/TPx3_iface_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/arrivalTimeLUT_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/ax3_pm3_mTLUvC.xdc 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/clock_sim.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/clocks_7s_extphy.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/clocks_7s_extphy_se.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/clocks_7s_extphy_se_MOD.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/clocks_s6_extphy.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/coincidenceLogic_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/coincidenceLogic_rtl_BKP.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/counterDown.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/counterWithReset_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/dualSERDES_1to4_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/enclustra_ax3_pm3_infra.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/eth_7s_gmii.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/eth_7s_rgmii.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/eventBuffer_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/eventFormatter_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/fmcTLU_pkg.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/fmcTLU_pkg_body.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/handshakes_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/i2c_master_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/ipbus_addr_decode.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/ipbus_decode_ipbus_example.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/ipbus_decode_tlu.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/ipbus_example.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/ipbus_fabric_sel.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/ipbus_slaves.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/ipbus_ver.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/led_stretcher.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/logic_clocks_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/registerCounter_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/serdes_1_to_n_SDR.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/single_pulse_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/stretchPulse_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/sync_reg.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/synchronizeRegisters_fifo.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/synchronizeRegisters_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/test_inToOut.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/test_inputToOutput.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/test_toggleLines.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/testbench_clocks.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/testbench_myclocks.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/top_enclustra_ax3_pm3.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/top_enclustra_tlu.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_newTLU_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/common/triggerLogic_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/scripts/500ns_23ns.txt 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/scripts/500ns_24ns.txt 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/scripts/AIDA_testScript.py 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/scripts/TLU.py 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/scripts/TLUaddrmap.xml 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/scripts/TLUconnection.xml 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/scripts/initTLU.py 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/scripts/output_check.csv 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/scripts/startTLU.sh 0 → 100755
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AIDA_tlu/legacy/TLU_v1c/scripts/startTLU_v6.py 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/scripts/startTLU_v8.py 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/scripts/test.py 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/scripts/testTLU_script.py 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/scripts/test_T0.py 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/test/clock_divider_s6.v 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/test/clocks_s6_extphy.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/test/comb_generator_rtl.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/test/dtype_fd.vhdl 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/test/dtype_fdpe.vhdl 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/test/dtype_fdr.vhdl 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/test/dtype_fds.vhdl 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/test/fmc-tlu_sp601_pulse_shaper.vhdl 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/test/fmc_tlu_pin_test.vhd 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/test/fmc_tlu_sp601_tb.vhdl 0 → 100644
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AIDA_tlu/legacy/TLU_v1c/test/fmc_tlu_top_sp601.vhd 0 → 100644
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