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AIDA-2020 TLU
Commits
d8c9b2f2
Commit
d8c9b2f2
authored
May 11, 2015
by
David Cussans
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Checking in files for setting up simulation
parent
395b773e
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2 changed files
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292 additions
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0 deletions
+292
-0
add_files.tcl
firmware/simulation/scripts/add_files.tcl
+94
-0
wave1.do
firmware/simulation/scripts/wave1.do
+198
-0
No files found.
firmware/simulation/scripts/add_files.tcl
0 → 100644
View file @
d8c9b2f2
set
xlib_vhdl
$::env
(
ISE_VHDL_MTI
)
set
xlib_vlog
$::env
(
ISE_VLOG_MTI
)
project new ./ fmc_tlu_sim
vmap unisim
$xlib
_vhdl/unisim
vmap unimacro
$xlib
_vhdl/unimacro
vmap secureip
$xlib
_vlog/secureip
vmap xilinxcorelib
$xlib
_vhdl/xilinxcorelib
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/example_designs/hdl/clock_div.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipcore_dir/tri_mode_eth_mac_v5_4.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipcore_dir/mac_fifo_axi4.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/transactor.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/stretcher.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/fmcTLU_pkg.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/fmcTLU_pkg_body.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/external/opencores_i2c/i2c_master_registers.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/external/opencores_i2c/i2c_master_byte_ctrl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/external/opencores_i2c/i2c_master_bit_ctrl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/slaves/hdl/syncreg_w.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/slaves/hdl/syncreg_r.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipcore_dir/tlu_event_fifo.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipcore_dir/internalTriggerGenerator.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipcore_dir/FIFO.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/IODELAYCal_FSM_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/external/opencores_i2c/i2c_master_top.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/coincidenceLogic_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/stretchPulse_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/ethernet/sim/eth_mac_sim.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/ipbus/firmware/sim/hdl/clock_sim.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/simulation_src/pmtPulseGenerator_rtl.vhd
# Special file for linking to TimePix telescope:
project addfile
$::env
(
FW_WORKSPACE
)
/workspace/fmc-mtlu/firmware/hdl/common/TPx3_iface.vhd
project calculateorder
project close
quit
firmware/simulation/scripts/wave1.do
0 → 100644
View file @
d8c9b2f2
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/auxTrigger_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/g_nInputs
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/g_patternWidth
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/s_auxTrigOut
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/s_configBit
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/s_configDataSR
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/s_configEnable
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/s_configEnableSR
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/s_trigOut
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/triggerPattern_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/trigger_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/triggers_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/CFGLUT5_inst/CLK
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/CFGLUT5_inst/INIT
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/CFGLUT5_inst/O5
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/CFGLUT5_inst/O6
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/CFGLUT5_inst/SHIFT_REG
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/CFGLUT5_inst/o5_addr
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/CFGLUT5_inst/o5_slv
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/CFGLUT5_inst/o6_addr
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/cmp_coincicence_logic/CFGLUT5_inst/o6_slv
add wave -noupdate -expand /fmctlu_v0_1_testbench/uut/I3/ipbus_i
add wave -noupdate -expand /fmctlu_v0_1_testbench/uut/I3/ipbus_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/post_veto_trigger_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/pre_veto_trigger_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/s_PulseStretchWord
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/s_TriggerPattern
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/s_loadTriggerPattern
add wave -noupdate -expand /fmctlu_v0_1_testbench/uut/I3/s_sync_status_to_ipbus
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/s_veto_word
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/s_post_veto_trigger_counter
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/s_pre_veto_trigger_counter
add wave -noupdate -divider triggerLogic
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/s_controlRegStrobes
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/s_loadTriggerPattern
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/ipbus_clk_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/ipbus_reset_i
add wave -noupdate -divider {Top level}
add wave -noupdate /fmctlu_v0_1_testbench/uut/T0_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/clk_4x_logic
add wave -noupdate /fmctlu_v0_1_testbench/uut/s_shutter
add wave -noupdate /fmctlu_v0_1_testbench/uut/strobe_4x_logic
add wave -noupdate /fmctlu_v0_1_testbench/uut/threshold_discr_n_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/threshold_discr_p_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/triggers
add wave -noupdate /fmctlu_v0_1_testbench/uut/buffer_full_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/veto_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/overall_veto
add wave -noupdate -divider {Test Bench}
add wave -noupdate /fmctlu_v0_1_testbench/T0_n_i
add wave -noupdate /fmctlu_v0_1_testbench/T0_p_i
add wave -noupdate /fmctlu_v0_1_testbench/TPix_Shutter_n_i
add wave -noupdate /fmctlu_v0_1_testbench/TPix_Shutter_p_i
add wave -noupdate -divider {Trigger Inputs}
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/ipbus_reset_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/reset_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_calibrate_idelay
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_cfd_trigger_times
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_control_from_ipbus
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_counter_reset
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_deserialized_cfd_data
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_deserialized_cfd_data_l
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_deserialized_threshold_data
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_deserialized_threshold_data_l
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_edge_falling
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_edge_falling_times
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_edge_rising
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_edge_rising_times
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_rst_iserdes
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_status_to_ipbus
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_sync_control_from_ipbus
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_sync_status_to_ipbus
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_threshold_discr_input
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/s_threshold_previous_late_bit
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/strobe_16x_logic_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/strobe_4x_logic_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/threshold_discr_n_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/threshold_discr_p_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/trigger_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/trigger_times_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/clk_16x_logic_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/clk_4x_logic
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/ipbus_clk_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/strobe_16x_logic_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/strobe_4x_logic_i
add wave -noupdate -expand /fmctlu_v0_1_testbench/uut/I1/ipbus_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/ipbus_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/ipbus_reset_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/reset_i
add wave -noupdate -expand /fmctlu_v0_1_testbench/uut/I1/s_status_to_ipbus
add wave -noupdate -expand /fmctlu_v0_1_testbench/uut/I1/s_sync_status_to_ipbus
add wave -noupdate -divider {Sync Trigger input}
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/sync_ipbus/data_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/sync_ipbus/data_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/sync_ipbus/g_NUM_REGISTERS
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/sync_ipbus/s_read_strobe
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/sync_ipbus/s_registered_data
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/sync_ipbus/s_ring_d0
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/sync_ipbus/s_ring_d1
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/sync_ipbus/s_ring_d2
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/sync_ipbus/s_ring_d3
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/sync_ipbus/s_ring_d4
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/sync_ipbus/s_ring_d5
add wave -noupdate /fmctlu_v0_1_testbench/uut/I1/sync_ipbus/s_write_strobe
add wave -noupdate -divider {Logic Clocks}
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/DUT_clk_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/Reset_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/clk_16x_logic_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/clk_4x_logic_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/clk_logic_xtal_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/extclk_n_b
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/extclk_p_b
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/ipbus_clk_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/ipbus_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/ipbus_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/ipbus_reset_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/logic_clocks_locked_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/logic_reset_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_DUT_Clk
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_clk160
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_clk160_internal
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_clk40
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_clk640
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_clk640_internal
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_clk_is_xtal
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_clkfbout
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_clock_status_ipb
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_extclk
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_extclkG
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_ipbus_ack
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_locked_bufpll
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_locked_pll
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_logic_clk_generator
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_logic_reset
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_logic_reset_d1
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_logic_reset_d2
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_logic_reset_d3
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_logic_reset_ipb
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_logic_reset_ipb_d1
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_reset_pll
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/s_strobe_generator
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/strobe_16x_logic_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I6/strobe_4x_logic_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/s_internal_veto
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/veto_i
add wave -noupdate -divider {Trigger Logic / IPBUs registers}
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/ipbus_registers/N_CTRL
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/ipbus_registers/N_STAT
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/ipbus_registers/cw_cyc
add wave -noupdate -expand /fmctlu_v0_1_testbench/uut/I3/ipbus_registers/d
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/ipbus_registers/q
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/ipbus_registers/reg
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/ipbus_registers/ri
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/ipbus_registers/sel
add wave -noupdate -expand /fmctlu_v0_1_testbench/uut/I3/ipbus_registers/si
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/ipbus_registers/stat_cyc
add wave -noupdate /fmctlu_v0_1_testbench/uut/I3/ipbus_registers/stb
add wave -noupdate -divider {Event Formatter}
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/logic_reset_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/logic_strobe_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/reset_timestamp_i
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/reset_timestamp_o
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_coarse_timestamp_h
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_coarse_timestamp_h_d1
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_coarse_timestamp_h_d2
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_coarse_timestamp_h_d3
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_coarse_timestamp_ipbus
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_coarse_timestamp_l
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_coarse_timestamp_l_d1
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_coarse_timestamp_l_d2
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_coarse_timestamp_l_d3
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_reset_timestamp_4x
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_reset_timestamp_4x_external
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_reset_timestamp_4x_external_p1
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_reset_timestamp_4x_external_p2
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_reset_timestamp_4x_ipbus
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_reset_timestamp_ipbus
add wave -noupdate /fmctlu_v0_1_testbench/uut/I2/s_timestamp_h_en
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2139160008 ps} 0} {{Cursor 2} {118123357 ps} 0}
quietly wave cursor active 2
configure wave -namecolwidth 537
configure wave -valuecolwidth 98
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits us
update
WaveRestoreZoom {208044964 ps} {208380792 ps}
Write
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