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AIDA-2020 TLU
Commit de7083b2 authored by David Cussans's avatar David Cussans
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Trigger input and event type fields not being filled correctly in TLU data, 

unable to understand Alvaro's code, so removed it ( will re-implement later ).
This involved editing
* eventFormatter to strip out Alvaro's code
* triggerLogic to connect stretched triggers not input triggers to trigger_o

Wrote script to set registers to that simulation works OK
( aida_tlu_enable_data_recording.py )
parent 4899a765
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Showing with 135 additions and 186 deletions
firmware/hdl/common/eventFormatter_rtl.vhd
View file @ de7083b2
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firmware/hdl/common/triggerLogic_rtl.vhd
View file @ de7083b2
......@@ -233,7 +233,7 @@ BEGIN
-- Change Me
-- Process triggers , but for now pass through.
trigger_o <= trigger_i;
trigger_o <= s_stretchedTriggers;
trigger_times_o <= trigger_times_i;
end if;
......
firmware/scripts/aida_tlu_enable_data_recording.py 0 → 100644
View file @ de7083b2
#
# Script to exercise AIDA mini-TLU
#
# David Cussans, December 2012
#
# Hacked to only test internal triggers
from PyChipsUser import *
from FmcTluI2c import *
import sys
import time
def mean(TS):
val=0
for i in range(1,len(TS)):
val+=TS[i]-TS[i-1]
return val/(len(TS)-1)
def pulseT0(board):
# set T0 bit to 1
PulseBits = board.read("ConfBits")
# print "ConfBits before pulseT0: ", hex(PulseBits)
PulseBits = PulseBits | 0x2
# board.write("ConfBits", PulseBits)
# print "ConfBits after pulseT0: ", hex(PulseBits)
# reset T0 bit
PulseBits = board.read("ConfBits")
PulseBits = PulseBits & 0xfffffffd
board.write("ConfBits", PulseBits)
PulseBits = board.read("ConfBits")
# print "ConfBits after reseting pulseT0: ", hex(PulseBits)
# POint to TLU
bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 2
board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
firmwareID=board.read("FirmwareId")
print "Firmware = " , hex(firmwareID)
print "Set all DUT into AIDA mode"
board.write("DUTInterfaceModeW", 0xFF)
DUTInterfaceModeR = board.read("DUTInterfaceModeR")
print "DUT mode read back as " , DUTInterfaceModeR
print "Disable all DUT"
board.write("DUTMaskW",0)
DUTMask = board.read("DUTMaskR")
print "DUTMaskR = " , DUTMask
print "Set IgnoreShutterVetoW to Ignore veto from shutter"
board.write("IgnoreShutterVetoW",1)
print "Ignore veto on all DUT"
board.write("IgnoreDUTBusyW",0xF)
IgnoreDUTBusy = board.read("IgnoreDUTBusyR")
print "IgnoreDUTBusyR = " , IgnoreDUTBusy
print "Turning off software trigger veto"
board.write("TriggerVetoW",0)
print "Reseting FIFO"
board.write("EventFifoCSR",0x2)
print "Enable data recording"
board.write("Enable_Record_Data",1)
firmware/simulation/questa/fmc_tlu.mpf
View file @ de7083b2
......@@ -1544,15 +1544,15 @@ Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 5
Project_File_0 = /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/fmc-tlu_sp601.vhdl
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298653495 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298653495 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_1 = /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/pulse_shaper.vhdl
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298654919 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298654919 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_2 = /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/dtype_fd.vhdl
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298563433 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298563433 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_3 = /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/fmc_tlu_sp601_tb.vhdl
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298652988 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298652988 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_4 = /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/dtype_fdpe.vhdl
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298458157 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298458157 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
......@@ -1586,7 +1586,19 @@ LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
TDB_DoubleClick = Edit
TDB_CustomDoubleClick =
UPF_DoubleClick = Edit
UPF_CustomDoubleClick =
PCF_DoubleClick = Edit
PCF_CustomDoubleClick =
PROJECT_DoubleClick = Edit
PROJECT_CustomDoubleClick =
Project_Major_Version = 6
Project_Minor_Version = 6
VRM_DoubleClick = Edit
VRM_CustomDoubleClick =
DEBUGDATABASE_DoubleClick = Edit
DEBUGDATABASE_CustomDoubleClick =
DEBUGARCHIVE_DoubleClick = Edit
DEBUGARCHIVE_CustomDoubleClick =
Project_Major_Version = 10
Project_Minor_Version = 4
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