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AIDA-2020 TLU
Commit de762276 authored by Alvaro Dosil's avatar Alvaro Dosil
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outputs tests files for sp601

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firmware/hdl/test/DUTInterfaces_rtl.vhd 0 → 100644
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--=============================================================================
--! @file DUTInterfaces_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:09:50 11/09/12
--
--! @version v0.1
--
--! @details
--! Address map:\n
--! 5-bit decoded
--! 0x00000000 - DUT interface mode, two bits per DUT. Up to 12 inputs XXXXXXXXBBAA99887766554433221100\n
--! - mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
--!
--
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> Indicate if the DUT works under AIDA/EUDET style\n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
library unisim;
use unisim.VComponents.all;
ENTITY DUTInterfaces IS
GENERIC(
g_NUM_DUTS : positive := 3;
g_IPBUS_WIDTH : positive := 32
);
PORT(
--busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
--busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
clk_4x_logic_i : IN std_logic;
clk_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
ipbus_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic; -- ! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_i : IN std_logic; -- goes high when trigger logic issues a trigger
--shutter_i : IN std_logic; -- goes high when trigger logic issues a shutter
ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
--reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
--reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
--trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
--trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
--shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
--shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
output_0_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_0_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_1_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_1_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_2_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_2_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_3_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_3_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
veto_o : OUT std_logic -- goes high when one or more DUT are busy
);
-- Declarations
END ENTITY DUTInterfaces ;
--
ARCHITECTURE rtl OF DUTInterfaces IS
signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0); -- OR tree
signal s_veto : std_logic;
signal s_strobe_4x_logic_d1, clk_2x_logic : std_logic;
signal s_busy_from_dut , s_clk_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs not used
signal s_EnableOutput : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
constant c_N_CTRL : positive := 2;
constant c_N_STAT : positive := 2;
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
BEGIN
-- Dummy code.
s_intermediate_busy_or(0) <= '0';
--s_busy_from_dut(g_NUM_DUTS-1 downto 0) <= (others=>'0');
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
ipbus_registers: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => c_N_CTRL,
N_STAT => c_N_STAT
)
port map(
clk => ipbus_clk_i,
reset=> '0',--ipbus_reset_i ,
ipbus_in=> ipbus_i,
ipbus_out=> ipbus_o,
d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb=> open
);
-- Synchronize registers from logic clock to ipbus.
sync_status: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_4x_logic_i,
data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
-- Synchronize registers from logic clock to ipbus.
sync_ctrl: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_CTRL )
port map (
clk_input_i => ipbus_clk_i,
data_i => s_control_from_ipbus,
data_o => s_sync_control_from_ipbus,
clk_output_i => clk_4x_logic_i);
-- Map the control registers
s_DUT_mask <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
s_EnableOutput <= s_sync_control_from_ipbus(1);
-- Map the status registers
s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
s_status_to_ipbus(1) <= s_EnableOutput;
-- purpose: Writes in the positive pin of the signals an 80MHz clock and the strobe_4x_logic_i in the negative one.
--The output signals (one signal is an lvds pair) can be enabled independently in the s_EnableOutput via IPBus.
-- type : combinational
-- inputs : clk_2x_logic , strobe_4x_logic_i, s_EnableOutput
-- outputs: output_0_p, output_0_n, output_1_p, output_1_n, output_2_p, output_2_n, output_3_p, output_3_n
duts: for dut in 1 to g_NUM_DUTS generate
output_0_p_inst : OBUF
port map (
O => output_0_p(dut-1),
I => s_EnableOutput(0) and clk_2x_logic -- Buffer input
);
output_0_n_inst : OBUF
port map (
O => output_0_n(dut-1),
I => s_EnableOutput(0) and strobe_4x_logic_i -- Buffer input
);
output_1_p_inst : OBUF
port map (
O => output_1_p(dut-1),
I => s_EnableOutput(1) and clk_2x_logic -- Buffer input
);
output_1_n_inst : OBUF
port map (
O => output_1_n(dut-1),
I => s_EnableOutput(1) and strobe_4x_logic_i -- Buffer input
);
output_2_p_inst : OBUF
port map (
O => output_2_p(dut-1),
I => s_EnableOutput(2) and clk_2x_logic -- Buffer input
);
output_2_n_inst : OBUF
port map (
O => output_2_n(dut-1),
I => s_EnableOutput(2) and strobe_4x_logic_i -- Buffer input
);
output_3_p_inst : OBUF
port map (
O => output_3_p(dut-1),
I => s_EnableOutput(3) and clk_2x_logic -- Buffer input
);
output_3_n_inst : OBUF
port map (
O => output_3_n(dut-1),
I => s_EnableOutput(3) and strobe_4x_logic_i -- Buffer input
);
s_intermediate_busy_or(dut) <= s_intermediate_busy_or(dut-1) or
(s_busy_from_dut(dut-1) and
s_DUT_mask(dut-1));
end generate duts;
s_veto <= s_intermediate_busy_or(g_NUM_DUTS);
clk_2x_logic <= s_strobe_4x_logic_d1 or strobe_4x_logic_i; --80 MHz clock
-- purpose: register for internal signals and output signals
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
-- outputs: veto_o
register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
begin -- process register_signals
if rising_edge(clk_4x_logic_i) then
veto_o <= s_veto;
s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
s_reset_or_clk_to_dut <= ( others => (s_strobe_4x_logic_d1 or strobe_4x_logic_i));
s_trigger_to_dut <= ( others => trigger_i );
--shutter_to_dut <= ( others => shutter_i );
end if;
end process register_signals;
END ARCHITECTURE rtl;
firmware/hdl/test/sp601_FMC_mTLU.ucf 0 → 100644
View file @ de762276
NET sysclk_p_i LOC = K15 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
NET sysclk_n_i LOC = K16 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
# remove for now
#NET Reset_i LOC=P4; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET I6/s_clk_is_xtal TIG;
NET leds_o<0> LOC=E13 | IOSTANDARD=LVCMOS25;
NET leds_o<1> LOC=C14 | IOSTANDARD=LVCMOS25;
NET leds_o<2> LOC=C4 | IOSTANDARD=LVCMOS25;
NET leds_o<3> LOC=A4 | IOSTANDARD=LVCMOS25;
NET dip_switch_i<0> LOC=D14;
NET dip_switch_i<1> LOC=E12;
NET dip_switch_i<2> LOC=F12;
NET dip_switch_i<3> LOC=V13;
# Ethernet PHY
TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET gmii_gtx_clk_o LOC=A9 | IOSTANDARD=LVCMOS25 | SLEW=FAST;
NET gmii_txd_o<0> LOC=F8 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<1> LOC=G8 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<2> LOC=A6 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<3> LOC=B6 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<4> LOC=E6 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<5> LOC=F7 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<6> LOC=A5 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<7> LOC=C5 | IOSTANDARD=LVCMOS25;
NET gmii_tx_en_o LOC=B8 | IOSTANDARD=LVCMOS25;
NET gmii_tx_er_o LOC=A8 | IOSTANDARD=LVCMOS25;
NET gmii_rx_clk_i LOC=L16 | IOSTANDARD=LVCMOS25 | TNM_NET= "gmii_rx_clk_i";
TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
NET gmii_rxd_i<0> LOC=M14 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<1> LOC=U18 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<2> LOC=U17 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<3> LOC=T18 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<4> LOC=T17 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<5> LOC=N16 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<6> LOC=N15 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<7> LOC=P18 | IOSTANDARD=LVCMOS25;
NET gmii_rx_dv_i LOC=N18 | IOSTANDARD=LVCMOS25;
NET gmii_rx_er_i LOC=P17 | IOSTANDARD=LVCMOS25;
NET phy_rstb_o LOC=L13 | IOSTANDARD=LVCMOS25;
# Main I2C bus
NET "I2C_SCL_B" LOC = "P11"; ## C30 on FMC
NET "I2C_SDA_B" LOC = "N10"; ## C31 on FMC
#
# I/O to devices under test
#NET "BUSY_P_I<0>" LOC = "D12"; ## "FMC_LA06_P" , C10 on FMC
#NET "BUSY_N_I<0>" LOC = "C12"; ## "FMC_LA06_N" , C11 on FMC
#NET "BUSY_P_I<1>" LOC = "U11"; ## "FMC_LA28_P" , H31 on FMC
#NET "BUSY_N_I<1>" LOC = "V11"; ## "FMC_LA28_N" , H32 on FMC
#NET "BUSY_P_I<2>" LOC = "E7"; ## "FMC_LA07_P" , H13 on FMC
#NET "BUSY_N_I<2>" LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
#NET "TRIGGERS_P_O<0>" LOC = "D8"; ## "FMC_LA10_P" , C14 on FMC
##NET "TRIGGERS_N_O<0>" LOC = "C8"; ## "FMC_LA10_N" , C15 on FMC
#NET "TRIGGERS_P_O<1>" LOC = "U15"; ## "FMC_LA32_P" , H37 on FMC
##NET "TRIGGERS_N_O<1>" LOC = "V15"; ## "FMC_LA32_N" , H38 on FMC
#NET "TRIGGERS_P_O<2>" LOC = "G11"; ## "FMC_LA09_P" , D14 on FMC
##NET "TRIGGERS_N_O<2>" LOC = "F10"; ## "FMC_LA09_N" , D15 on FMC
# Remove for now.
#NET "SHUTTERS_P_O<0>" LOC = "N7"; ## "FMC_LA20_P" , G21 on FMC
##NET "SHUTTERS_N_O<0>" LOC = "P8"; ## "FMC_LA20_N" , G22 on FMC
#NET "SHUTTERS_P_O<1>" LOC = "R10"; ## "FMC_LA18_CC_P" , C22 on FMC
##NET "SHUTTERS_N_O<1>" LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "N6"; ## "FMC_LA19_P" , H22 on FMC
##NET "SHUTTERS_N_O<2>" LOC = "P6"; ## "FMC_LA19_N" , H23 on FMC
#NET "DUT_CLK_P_I<0>" LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
#NET "DUT_CLK_N_I<0>" LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
#NET "DUT_CLK_P_I<1>" LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
#NET "DUT_CLK_N_I<1>" LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
#NET "DUT_CLK_P_I<2>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
#NET "DUT_CLK_N_I<2>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
#NET "RESET_OR_CLK_P_O<0>" LOC = "M10"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
##NET "RESET_OR_CLK_N_O<0>" LOC = "N9"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
#NET "RESET_OR_CLK_P_O<1>" LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
##NET "RESET_OR_CLK_N_O<1>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
#NET "RESET_OR_CLK_P_O<2>" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
##NET "RESET_OR_CLK_N_O<2>" LOC = "A16"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
# Trigger Inputs
# Constant-fraction-discrimiator comparator outputs
#NET "CFD_DISCR_P_I<0>" LOC = "D9"; ## "FMC_LA00_CC_P" , G6 on FMC
#NET "CFD_DISCR_N_I<0>" LOC = "C9"; ## "FMC_LA00_CC_N" , G7 on FMC
#
#NET "CFD_DISCR_P_I<1>" LOC = "B2"; ## "FMC_LA14_P" , C18 on FMC
#NET "CFD_DISCR_N_I<1>" LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
#
#NET "CFD_DISCR_P_I<2>" LOC = "B14"; ## "FMC_LA05_P" , D11 on FMC
#NET "CFD_DISCR_N_I<2>" LOC = "A14"; ## "FMC_LA05_N" , D12 on FMC
#
#NET "CFD_DISCR_P_I<3>" LOC = "B11"; ## "FMC_LA13_P" , D17 on FMC
#NET "CFD_DISCR_N_I<3>" LOC = "A11"; ## "FMC_LA13_N" , D18 on FMC
# Threshold comparator outputs
NET "THRESHOLD_DISCR_P_I<0>" LOC = "D11"; ## "FMC_LA01_CC_P" , D8 on FMC
NET "THRESHOLD_DISCR_N_I<0>" LOC = "C11"; ## "FMC_LA01_CC_N" , D9 on FMC
NET "THRESHOLD_DISCR_P_I<1>" LOC = "C13"; ## "FMC_LA03_P" , G9 on FMC
NET "THRESHOLD_DISCR_N_I<1>" LOC = "A13"; ## "FMC_LA03_N" , G10 on FMC
NET "THRESHOLD_DISCR_P_I<2>" LOC = "D6"; ## "FMC_LA12_P" , G15 on FMC
NET "THRESHOLD_DISCR_N_I<2>" LOC = "C6"; ## "FMC_LA12_N" , G16 on FMC
NET "THRESHOLD_DISCR_P_I<3>" LOC = "C7"; ## "FMC_LA16_P" , G18 on FMC
NET "THRESHOLD_DISCR_N_I<3>" LOC = "A7"; ## "FMC_LA16_N" , G19 on FMC
#NET "SPARE_P<2>" LOC = "R8"; ## "FMC_LA17_CC_P" , D20 on FMC
#NET "SPARE_N<2>" LOC = "T8"; ## "FMC_LA17_CC_N" , D21 on FMC
#NET "SPARE_P<1>" LOC = "T12"; ## "FMC_LA30_P" , H34 on FMC
#NET "SPARE_N<1>" LOC = "V12"; ## "FMC_LA30_N" , H35 on FMC
NET "EXTCLK_P_B" LOC = "C10"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "EXTCLK_N_B" LOC = "A10"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
#NET "HDMI_POWER_ENABLE1" LOC = "C15"; ## "FMC_LA02_P" , H7 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
# GPIO pins for debugging.
#NET "GPIO_HDR<0>" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm)
#NET "GPIO_HDR<1>" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm)
#NET "GPIO_HDR<2>" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm)
#NET "GPIO_HDR<3>" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm)
#NET "GPIO_HDR<4>" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm)
#NET "GPIO_HDR<5>" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm)
#NET "GPIO_HDR<6>" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm)
#NET "GPIO_HDR<7>" LOC = "P12"; ## 8 on J13 (thru series R96 20
NET "output_0_p[0]" LOC = D8;
NET "output_0_p[1]" LOC = U15;
NET "output_0_p[2]" LOC = G11;
NET "output_0_n[0]" LOC = C8;
NET "output_0_n[1]" LOC = V15;
NET "output_0_n[2]" LOC = F10;
NET "output_1_p[0]" LOC = T6;
NET "output_1_p[1]" LOC = U8;
NET "output_1_p[2]" LOC = F11;
NET "output_1_n[0]" LOC = V6;
NET "output_1_n[1]" LOC = V8;
NET "output_1_n[2]" LOC = E11;
NET "output_2_p[0]" LOC = M10;
NET "output_2_p[1]" LOC = T4;
NET "output_2_p[2]" LOC = B16;
NET "output_2_n[0]" LOC = N9;
NET "output_2_n[1]" LOC = V4;
NET "output_2_n[2]" LOC = A16;
NET "output_3_p[0]" LOC = D12;
NET "output_3_p[1]" LOC = U11;
NET "output_3_p[2]" LOC = E7;
NET "output_3_n[0]" LOC = C12;
NET "output_3_n[1]" LOC = V11;
NET "output_3_n[2]" LOC = E8;
\ No newline at end of file
firmware/hdl/test/sp601_FMC_mTLU_v1a.ucf 0 → 100644
View file @ de762276
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firmware/hdl/test/top_extphy_struct.vhd 0 → 100644
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