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AIDA-2020 TLU
Commit f6809ab7 authored by David Cussans's avatar David Cussans
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Improving Doxygen documentation

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firmware/hdl/common/DUTInterfaces_rtl.vhd
View file @ f6809ab7
......@@ -24,13 +24,13 @@ library unisim;
use unisim.VComponents.all;
--! @brief Interfaces to Device Under Test (DUT) connectors.
--
--!
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--!
--! @date 15:09:50 11/09/12
--
--!
--! @version v0.1
--
--!
--! @details
--! \n\n IPBUS Address map:
--! \n (Decodes 3 bits)
......@@ -38,7 +38,7 @@ use unisim.VComponents.all;
--! \li 0x00000001 - Ignore DUT busy. 1 = ignore BUSY from this connector
--! \li 0x00000002 - Ignore shutter veto. 0 = raising shutter vetos triggers.
--! \li 0x00000003 - DUT interface mode, two bits per DUT. Up to 12 inputs
--XXXXXXXXBBAA99887766554433221100 mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
--! XXXXXXXXBBAA99887766554433221100 mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
--! \li 0x00000004 - DUT mask ( read )
--!
--! DUT(0) = RJ45 ( J3 )\n
......@@ -46,10 +46,10 @@ use unisim.VComponents.all;
--! DUT(2) = HDMI ( J2) , closest to RJ45\n
--!
--! <b>Modified by:</b>\n
-------------------------------------------------------------------------------
--! -----------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo Indicate if the DUT works under AIDA/EUDET style
-- todo Indicate if the DUT works under AIDA/EUDET style
--
ENTITY DUTInterfaces IS
......
firmware/hdl/common/coincidenceLogic_rtl.vhd
View file @ f6809ab7
......@@ -9,9 +9,6 @@
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
--
--! @brief Takes a set of input pulses and produces an output pulse based on trigger pattern
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
......@@ -20,27 +17,31 @@ USE ieee.std_logic_1164.all;
Library UNISIM;
use UNISIM.vcomponents.all;
--! @brief Takes a set of input pulses and produces an output pulse based on trigger pattern
--
-------------------------------------------------------------------------------
entity coincidenceLogic is
generic (
g_nInputs : positive := 4; -- --! Number of trigger inputs. Must be four for this implementation
g_patternWidth : positive := 32); -- --! Width of trigger pattern. Must be 32 in this implementation
g_nInputs : positive := 4; --! Number of trigger inputs. Must be four for this implementation
g_patternWidth : positive := 32); --! Width of trigger pattern. Must be 32 in this implementation
port (
configClk_i : in std_logic; -- --! Rising edge active
logicClk_i : in std_logic; -- --! Rising edge active
triggers_i : in std_logic_vector(g_nInputs-1 downto 0); -- --! Array of trigger inputs
trigger_o : out std_logic; -- --! Goes high when trigger pattern matched
auxTrigger_o : out std_logic; -- --! Goes high when auxillary trigger pattern matched
triggerPattern_i : in std_logic_vector(g_patternWidth-1 downto 0); -- --! Pattern to match triggers with
loadPattern_i : in std_logic); -- --! Pattern is loaded when loadPattern goes high.
configClk_i : in std_logic; --! Rising edge active
logicClk_i : in std_logic; --! Rising edge active
triggers_i : in std_logic_vector(g_nInputs-1 downto 0); --! Array of trigger inputs
trigger_o : out std_logic; --! Goes high when trigger pattern matched
auxTrigger_o : out std_logic; --! Goes high when auxillary trigger pattern matched
triggerPattern_i : in std_logic_vector(g_patternWidth-1 downto 0); --! Pattern to match triggers with
loadPattern_i : in std_logic); --! Pattern is loaded when loadPattern goes high.
end entity coincidenceLogic;
architecture rtl of coincidenceLogic is
signal s_configDataSR , s_configEnableSR: std_logic_vector( triggerPattern_i'range ) := ( others => '0' ); -- --! shift reg for config data
signal s_configBit , s_configEnable : std_logic := '0'; -- --! Take high to shift in configuration data.
signal s_configDataSR , s_configEnableSR: std_logic_vector( triggerPattern_i'range ) := ( others => '0' ); --! shift reg for config data
signal s_configBit , s_configEnable : std_logic := '0'; --! Take high to shift in configuration data.
signal s_trigOut , s_auxTrigOut : std_logic := '0'; -- registers for output data.
begin -- architecture rtl
......
firmware/hdl/common/counterWithReset_rtl.vhd
View file @ f6809ab7
......@@ -8,6 +8,13 @@
------------------------------------------------------------------------------- --
-- unit name: counterWithReset (counterWithReset / rtl)
--
--============================================================================
--! Entity declaration for counterWithReset
--============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
--! @brief Simple counter with synchronous reset
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
......@@ -16,32 +23,14 @@
--
--! @version v0.1
--
--! @details
--!
--! <b>Dependencies:</b>\n
--! None
--!
--! <b>References:</b>\n
--! referenced by ipBusMarocTriggerGenerator \n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! @details
--! \n\n<b>Last changes:</b>\n
--! 5/Mar/12 DGC Changed to use numeric_std\n
--! 26/Feb/14 DGC Added registers to output to aid timing closure.
--!
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
---------------------------------------------------------------------------------
--============================================================================
--! Entity declaration for counterWithReset
--============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY counterWithReset IS
GENERIC (g_COUNTER_WIDTH : integer := 32; --! Number of bits
......
firmware/hdl/common/dualSERDES_1to4_rtl.vhd
View file @ f6809ab7
......@@ -9,8 +9,18 @@
------------------------------------------------------------------------------- --
-- VHDL Architecture work.dualSERDES_1to4.rtl
--
--! @brief Two 1:4 Deserializers. One has input delayed w.r.t. other\n
--! based on TDC by Alvaro Dosil\n
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library unisim ;
use unisim.vcomponents.all;
--! @brief Two 1:4 Deserializers. One has input delayed w.r.t. other
--! based on TDC by Alvaro Dosil
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
......@@ -21,10 +31,6 @@
--! @details
--! data_o(7) is the most recently arrived data , data_o(0) is the oldest data.
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
--! Author:
-------------------------------------------------------------------------------
......@@ -32,19 +38,8 @@
--! Separated FSM for calibration control into a separate entity. DGC, 22/Feb/14
-------------------------------------------------------------------------------
--! @todo Implement a periodic calibration sequence\n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library unisim ;
use unisim.vcomponents.all;
ENTITY dualSERDES_1to4 IS
PORT(
......
firmware/hdl/common/eventFormatter_rtl.vhd
View file @ f6809ab7
......@@ -24,13 +24,13 @@ use work.ipbus_reg_types.all;
--! @brief Takes the data delivered on each trigger and turns it into 64-bit
--! words to push into event buffer
--!
--
--!
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--!
--! @date 15:10:35 11/09/12
--
--!
--! @version v0.1
--
--!
--! @details
--! \n\n IPBus address:
--! \n (Decodes 3 bits)
......@@ -39,12 +39,12 @@ use work.ipbus_reg_types.all;
--! \li 010 - read = current timestamp (low 32-bits)
--! \li 011 - read = current timestamp (high 16-bits)
--!
-------------------------------------------------------------------------------
--! -----------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! Modified by: Alvaro Dosil , alvaro.dosil@usc.es \n
--! 27/Feb/14 DGC Change "If" when setting s_word2 to a case ... generate. Questasim
--! doesn't like having an if that can take an array out of bounds.
-------------------------------------------------------------------------------
--!-----------------------------------------------------------------------------
--! @todo Add more input data: \n
--! a) shutter signals. One per DUT. ?? \n
--! b) input levels ( for recording edge data ). Record rising and falling edges\n
......
firmware/hdl/common/triggerInputs_rtl.vhd
View file @ f6809ab7
......@@ -9,68 +9,6 @@
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
--
--! @brief Measures arrival time of trigger pulses using two deserializers
--! clocked on 14x clock ( 640MHz) \n
--! Based on TDC code by Alvaro Dosil\n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--!
--
--! @date 15:43:57 11/08/12
--
--! @version v0.1
--
--! @details
--! IPBus address 0 = control and status
--! bit0 = reset serdes
--! bit1 = reset counter
--! bit2 = calibrate IDELAYs
--! bit3 = not connected
--!
--! bit4 = Thresh discr IDelay(0) status prompt
--! bit5 = Thresh discr IDelay(0) status delayed
--! bit6 = Thresh discr IDelay(1) status prompt
--! bit7 = Thresh discr IDelay(1) status delayed
--! bit8 = Thresh discr IDelay(2) status prompt
--! bit9 = Thresh discr IDelay(2) status delayed
--! bit10= Thresh discr IDelay(3) status prompt
--! bit11= Thresh discr IDelay(3) status delayed
--!
--! bit12= CFD discr IDelay(0) status prompt
--! bit13= CFD discr IDelay(0) status delayed
--! bit14= CFD discr IDelay(1) status prompt
--! bit15= CFD discr IDelay(1) status delayed
--! bit16= CFD discr IDelay(2) status prompt
--! bit17= CFD discr IDelay(2) status delayed
--! bit18= CFD discr IDelay(3) status prompt
--! bit19= CFD discr IDelay(3) status delayed
--!
--! bit20= Thresh deserialized data monitor(0)
--! bit21= Thresh deserialized data monitor(1)
--! bit22= Thresh deserialized data monitor(2)
--! bit23= Thresh deserialized data monitor(3)
--! bit24= CFD deserialized data monitor(0)
--! bit25= CFD deserialized data monitor(1)
--! bit26= CFD deserialized data monitor(2)
--! bit27= CFD deserialized data monitor(3)
--!
--! IPBus address 1 = edge rising(0) counter
--! IPBus address 2 = edge rising(1) counter
--! IPBus address 3 = edge rising(2) counter
--! IPBus address 4 = edge rising(3) counter
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo Implement a periodic calibration sequence \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
......@@ -88,6 +26,62 @@ USE work.fmcTLU.all;
library unisim ;
use unisim.vcomponents.all;
--! @brief Measures arrival time of trigger pulses using two deserializers
--! clocked on 14x clock ( 640MHz)
--! Based on TDC code by Alvaro Dosil
--!
--! @author David Cussans , David.Cussans@bristol.ac.uk
--!
--!
--! @date 15:43:57 11/08/12
--!
--! @version v0.1
--!
--! @details
--! \li IPBus address 0 = control and status
--! \li bit0 = reset serdes
--! \li bit1 = reset counter
--! \li bit2 = calibrate IDELAYs
--! \li bit3 = not connected
--! \li bit4 = Thresh discr IDelay(0) status prompt
--! \li bit5 = Thresh discr IDelay(0) status delayed
--! \li bit6 = Thresh discr IDelay(1) status prompt
--! \li bit7 = Thresh discr IDelay(1) status delayed
--! \li bit8 = Thresh discr IDelay(2) status prompt
--! \li bit9 = Thresh discr IDelay(2) status delayed
--! \li bit10= Thresh discr IDelay(3) status prompt
--! \li bit11= Thresh discr IDelay(3) status delayed
--! \li bit12= CFD discr IDelay(0) status prompt
--! \li bit13= CFD discr IDelay(0) status delayed
--! \li bit14= CFD discr IDelay(1) status prompt
--! \li bit15= CFD discr IDelay(1) status delayed
--! \li bit16= CFD discr IDelay(2) status prompt
--! \li bit17= CFD discr IDelay(2) status delayed
--! \li bit18= CFD discr IDelay(3) status prompt
--! \li bit19= CFD discr IDelay(3) status delayed
--! \li bit20= Thresh deserialized data monitor(0)
--! \li bit21= Thresh deserialized data monitor(1)
--! \li bit22= Thresh deserialized data monitor(2)
--! \li bit23= Thresh deserialized data monitor(3)
--! \li bit24= CFD deserialized data monitor(0)
--! \li bit25= CFD deserialized data monitor(1)
--! \li bit26= CFD deserialized data monitor(2)
--! \li bit27= CFD deserialized data monitor(3)
--!
--! \li IPBus address 1 = edge rising(0) counter
--! \li IPBus address 2 = edge rising(1) counter
--! \li IPBus address 3 = edge rising(2) counter
--! \li IPBus address 4 = edge rising(3) counter
--!
--!
--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo Implement a periodic calibration sequence
--
ENTITY triggerInputs IS
GENERIC(
g_NUM_INPUTS : natural := 1;
......
firmware/hdl/common/triggerLogic_rtl.vhd
View file @ f6809ab7
......@@ -9,55 +9,44 @@
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
--
--! @brief Produces triggers from either trigger inputs or internal generator
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 16:06:19 11/09/12
--
--! @version v0.1
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
--! @details
--! IPBus address map:
--! - 0x00000000 RO - Number of triggers issued since last reset.
--! - 0x00000001 RO - Number of possible triggers since last reset (i.e. pre-veto triggers)
--! - 0x00000010 RW - Interval between internal triggers in ticks of logic_strobe_i
--! - 0x00000011 RW - trigger pattern - value that gets loaded into CFGLUT5
--! - 0x00000100 RW - bit-0 - internal trigger veto. Set to halt vetos.
--! - 0x00000101 RO - state of external veto
--! - 0x00000110 RW - stretch of pulses. Additional width = 0-31 clock cycles.
--! - 0x00000111 RW - delay of pulses. 0-31 clock cycles.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
USE work.fmcTLU.all;
--! @brief Produces triggers from either trigger inputs or internal generator
--!
--! @author David Cussans , David.Cussans@bristol.ac.uk
--!
--! <b>Dependencies:</b>\n
--! @date 16:06:19 11/09/12
--!
--! <b>References:</b>\n
--! @version v0.1
--!
--! @details
--! \br IPBus address map:
--! \li 0x00000000 RO - Number of triggers issued since last reset.
--! \li 0x00000001 RO - Number of possible triggers since last reset (i.e. pre-veto triggers)
--! \li 0x00000010 RW - Interval between internal triggers in ticks of logic_strobe_i
--! \li 0x00000011 RW - trigger pattern - value that gets loaded into CFGLUT5
--! \li 0x00000100 RW - bit-0 - internal trigger veto. Set to halt vetos.
--! \li 0x00000101 RO - state of external veto
--! \li 0x00000110 RW - stretch of pulses. Additional width = 0-31 clock cycles.
--! \li 0x00000111 RW - delay of pulses. 0-31 clock cycles.
--!
--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! Move all IPBus stuff into ipbus_syncreg_v , which also handles clock domain
--! crossing. 20/Feb/2014 , David Cussans
--! Add stretchPulse and coincidenceLogic entities. May/15 , David Cussans
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
USE work.fmcTLU.all;
ENTITY triggerLogic IS
GENERIC(
g_NUM_INPUTS : positive := 4;
......
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