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AIDA-2020 TLU
Commit faa17d06 authored by David Cussans's avatar David Cussans
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* Writing script to set up simulation environment ( scripts/setup_simulation.sh )

* Editing simulation test bench to remove ports no longer present ( simulation_src/fmc-tlu_v0-1_test-bench.vhd )

* Tidying up documentation ( in Doxygen / VHDL need to put @brief etc. near entity decl not at top of file ... )
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firmware/chipscope/fmc_tlu_chipscope.cdc
View file @ faa17d06
#ChipScope Core Inserter Project File Version 3.0
#Wed Aug 26 14:56:41 BST 2015
#Thu Aug 27 14:43:06 BST 2015
Project.device.designInputFile=/users/phdgc/IPBus_stuff/fmc_tlu_test_modify_tpix3_nov14_aug15/workspace/top_extphy_cs.ngc
Project.device.designOutputFile=/users/phdgc/IPBus_stuff/fmc_tlu_test_modify_tpix3_nov14_aug15/workspace/top_extphy_cs.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/users/phdgc/IPBus_stuff/fmc_tlu_test_modify_tpix3_nov14_aug15/workspace/_ngo
Project.device.useSRL16=true
Project.filter.dimension=18
Project.filter<0>=I0/*busy*
Project.filter<10>=*coarse_timestamp*
Project.filter<11>=*veto*
Project.filter<12>=*s_coarse_timestamp_h*
Project.filter<13>=*reset_timestamp*
Project.filter<14>=*coarse_timestamp_h*
Project.filter<15>=*coarse*
Project.filter<16>=*clk*
Project.filter<17>=clk*
Project.filter.dimension=19
Project.filter<0>=*veto*
Project.filter<10>=*T0*
Project.filter<11>=T0
Project.filter<12>=I2/s_coarse_timestamp_h*
Project.filter<13>=I2/*ignore*
Project.filter<14>=I2/*coarse_timestamp*
Project.filter<15>=*coarse_timestamp*
Project.filter<16>=*s_coarse_timestamp_h*
Project.filter<17>=*reset_timestamp*
Project.filter<18>=*coarse_timestamp_h*
Project.filter<1>=*busy*
Project.filter<2>=*shutter*
Project.filter<3>=*T0*
Project.filter<4>=T0
Project.filter<5>=
Project.filter<2>=
Project.filter<3>=*external*
Project.filter<4>=*externali*
Project.filter<5>=*veto_i*
Project.filter<6>=*ignore*
Project.filter<7>=I2/s_coarse_timestamp_h*
Project.filter<8>=I2/*ignore*
Project.filter<9>=I2/*coarse_timestamp*
Project.filter<7>=*ignore_busy*
Project.filter<8>=I0/*busy*
Project.filter<9>=*shutter*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
......@@ -34,16 +35,16 @@ Project.unit.dimension=1
Project.unit<0>.clockChannel=clk_4x_logic
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=I2/s_coarse_timestamp_h<0>
Project.unit<0>.dataChannel<10>=I0/veto_o
Project.unit<0>.dataChannel<11>=overall_veto
Project.unit<0>.dataChannel<12>=I0/s_IgnoreShutterVeto_s_veto_OR_36_o
Project.unit<0>.dataChannel<10>=I0/s_busy_from_dut<2>
Project.unit<0>.dataChannel<11>=I0/veto_o
Project.unit<0>.dataChannel<12>=overall_veto
Project.unit<0>.dataChannel<1>=I2/s_coarse_timestamp_h<1>
Project.unit<0>.dataChannel<2>=I2/s_coarse_timestamp_h<2>
Project.unit<0>.dataChannel<3>=I2/s_coarse_timestamp_h<3>
Project.unit<0>.dataChannel<4>=I2/s_reset_timestamp_ipbus
Project.unit<0>.dataChannel<5>=I2/s_reset_timestamp_4x
Project.unit<0>.dataChannel<6>=I15/T0_o
Project.unit<0>.dataChannel<7>=I15/shutter_o
Project.unit<0>.dataChannel<6>=I10/T0_o
Project.unit<0>.dataChannel<7>=I10/shutter_o
Project.unit<0>.dataChannel<8>=I0/s_busy_from_dut<0>
Project.unit<0>.dataChannel<9>=I0/s_busy_from_dut<1>
Project.unit<0>.dataDepth=2048
......@@ -55,9 +56,9 @@ Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=I2/s_coarse_timestamp_h<0>
Project.unit<0>.triggerChannel<0><10>=I0/s_busy_from_dut<2>
Project.unit<0>.triggerChannel<0><11>=I0/veto_o
Project.unit<0>.triggerChannel<0><12>=overall_veto
Project.unit<0>.triggerChannel<0><10>=I3/Mcount_s_post_veto_trigger_counter_cy<2>
Project.unit<0>.triggerChannel<0><11>=I3/Mcount_s_post_veto_trigger_counter_cy<1>
Project.unit<0>.triggerChannel<0><12>=I3/Mcount_s_post_veto_trigger_counter_cy<0>
Project.unit<0>.triggerChannel<0><1>=I2/s_coarse_timestamp_h<1>
Project.unit<0>.triggerChannel<0><2>=I2/s_coarse_timestamp_h<2>
Project.unit<0>.triggerChannel<0><3>=I2/s_coarse_timestamp_h<3>
......@@ -65,8 +66,8 @@ Project.unit<0>.triggerChannel<0><4>=I2/s_reset_timestamp_ipbus
Project.unit<0>.triggerChannel<0><5>=I2/s_reset_timestamp_4x
Project.unit<0>.triggerChannel<0><6>=I10/T0_o
Project.unit<0>.triggerChannel<0><7>=I10/shutter_o
Project.unit<0>.triggerChannel<0><8>=I0/s_busy_from_dut<0>
Project.unit<0>.triggerChannel<0><9>=I0/s_busy_from_dut<1>
Project.unit<0>.triggerChannel<0><8>=I3/s_post_veto_trigger
Project.unit<0>.triggerChannel<0><9>=I3/Mcount_s_post_veto_trigger_counter_cy<3>
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
......
firmware/documentation/Introduction.markdown 0 → 100644
View file @ faa17d06
Introduction to AIDA FMC Mini-TLU {#mainpage}
=================================
The TLU provides different parts of a Particle Physics Beam-Test
system with the information they need to synchronize data taken with
different detectors. The detectors are also refered to as Devices
Under Test (DUT).
Functions of TLU
----------------
- Trigger.
The TLU can combine signals from detectors in the beam-line ( often
scintillation detectors ) to produce a trigger that is sent to the
different DUT. Each DUT can indicate to the TLU that it is busy and
unable to take any further data.
- Particle Timestamping
The arrival time of every pulse from the beam-detectors is recorded.
- Clock and Synchronization Signals.
The TLU produces clock and synchronization signals that allow the
internal counters of different DUT to be sychronized.
N.B. Not all the functions of the TLU may be used in a given beam-test
system. For example, it is common to only use the Trigger/Busy
function of the TLU.
Firmare Structure
-----------------
The firmware is almost exclusively written in VHDL. The top level
entitity is [top_extphy](top_extphy_struct)
The HDL-Designer package by Mentor graphics has been used to develop
some of the code, mainly the top-level structure. However, is is not
necessary to use HDL-Designer to build the firmware. In fact the VHDL
files produced by HDL-Designer can also be edited "by hand" without
using the tool.
A block diagram, generated by HDL-Designer, is [here](http://www.ohwr.org/attachments/2710/hdl_designer_test_print_2.pdf)
Building Firmware
-----------------
Instructions on building the firmware are found
[here](http://www.ohwr.org/projects/fmc-mtlu/wiki/FirmwareBuild).
firmware/hdl/common/DUTInterfaces_rtl.vhd
View file @ faa17d06
......@@ -9,6 +9,20 @@
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
library unisim;
use unisim.VComponents.all;
--! @brief Interfaces to Device Under Test (DUT) connectors.
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
......@@ -18,43 +32,25 @@
--! @version v0.1
--
--! @details
--! IPBUS Address map:
--! - 0x00000000 - DUT mask(write). 1 = active , 0 = inactive. Inactive DUT don't contribute to BUSY. One bit per DUT XXXXXXXXXXXXXXXXXXXXXXBA9876543210
--! - 0x00000001 - Ignore DUT busy. 1 = ignore BUSY from this connector
--! - 0x00000002 - Ignore shutter veto. 0 = raising shutter vetos triggers.
--! - 0x00000003 - DUT interface mode, two bits per DUT. Up to 12 inputs
--! \n\n IPBUS Address map:
--! \n (Decodes 3 bits)
--! \li 0x00000000 - DUT mask(write). 1 = active , 0 = inactive. Inactive DUT don't contribute to BUSY. One bit per DUT XXXXXXXXXXXXXXXXXXXXXXBA9876543210
--! \li 0x00000001 - Ignore DUT busy. 1 = ignore BUSY from this connector
--! \li 0x00000002 - Ignore shutter veto. 0 = raising shutter vetos triggers.
--! \li 0x00000003 - DUT interface mode, two bits per DUT. Up to 12 inputs
--XXXXXXXXBBAA99887766554433221100 mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
--! - 0x00000004 - DUT mask ( read )
--! \li 0x00000004 - DUT mask ( read )
--!
--! DUT(0) = RJ45 ( J3 )
--! DUT(1) = HDMI ( J1 ) , furthest from RJ45
--! DUT(2) = HDMI ( J2) , closest to RJ45
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--! DUT(0) = RJ45 ( J3 )\n
--! DUT(1) = HDMI ( J1 ) , furthest from RJ45\n
--! DUT(2) = HDMI ( J2) , closest to RJ45\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> Indicate if the DUT works under AIDA/EUDET style\n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--! @todo Indicate if the DUT works under AIDA/EUDET style
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
library unisim;
use unisim.VComponents.all;
ENTITY DUTInterfaces IS
GENERIC(
......@@ -63,15 +59,15 @@ ENTITY DUTInterfaces IS
);
PORT(
clk_4x_logic_i : IN std_logic;
strobe_4x_logic_i : IN std_logic; -- ! goes high every 4th clock cycle
strobe_4x_logic_i : IN std_logic; --! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_i : IN std_logic; -- goes high when trigger logic issues a trigger
trigger_i : IN std_logic; --! goes high when trigger logic issues a trigger
-- clk_to_dut_i : IN std_logic; --! clock to DUT
reset_or_clk_to_dut_i : IN std_logic; --! For interface to TPix3 telescope this is the T0 sync signal
shutter_to_dut_i : IN std_logic; --! For interface to TPix3 telescope this shutter
-- IPBus signals.
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
ipbus_i : IN ipb_wbus; --! Signals from IPBus core to slave
ipbus_reset_i : IN std_logic;
ipbus_o : OUT ipb_rbus; --! signals from slave to IPBus core
-- Signals to/from DUT
......@@ -244,16 +240,19 @@ BEGIN
end generate duts;
-- BODGE BODGE BODGE. Hard wire only one DUT with shutter.
shutter_OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => shutter_to_dut_p_o(1), -- Diff_p output (connect directly to top-level port)
OB => shutter_to_dut_n_o(1), -- Diff_n output (connect directly to top-level port)
I => shutter_to_dut_i
);
-- RJ45 connector (output 0) doesn't have a shutter signal.
dut_shutters: for dut in 1 to g_NUM_DUTS-1 generate
shutter_OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => shutter_to_dut_p_o(dut), -- Diff_p output (connect directly to top-level port)
OB => shutter_to_dut_n_o(dut), -- Diff_n output (connect directly to top-level port)
I => shutter_to_dut_i
);
end generate dut_shutters;
-- purpose: generates a clock from 4x clock and strobe ( high once every 4 cycles )
-- should produce 11001100... etc. ie. 40MHz clock from 160MHz clock
-- type : combinational
......@@ -324,7 +323,8 @@ BEGIN
-- hardwire to shutter for now
veto_o <= ((not s_IgnoreShutterVeto ) and (not shutter_to_dut_i)) or s_veto;
-- veto_o <= '0';
end if;
end process register_signals;
......
firmware/hdl/common/eventFormatter_rtl.vhd
View file @ faa17d06
......@@ -9,9 +9,21 @@
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.eventFormatter.rtl
--
--! @brief Takes the data delivered on each trigger and turns it into a 64-bit
--! word\n
--! \n
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.fmcTLU.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
--! @brief Takes the data delivered on each trigger and turns it into 64-bit
--! words to push into event buffer
--!
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
......@@ -20,20 +32,16 @@
--! @version v0.1
--
--! @details
--! IPBus address:
--! 000 - read/write enable data recording.
--! 001 - write = reset timestamp,
--! 010 - read = current timestamp (low 32-bits)
--! 011 - read = current timestamp (high 16-bits)
--! \n\n IPBus address:
--! \n (Decodes 3 bits)
--! \li 000 - read/write enable data recording.
--! \li 001 - write = reset timestamp,
--! \li 010 - read = current timestamp (low 32-bits)
--! \li 011 - read = current timestamp (high 16-bits)
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! Modified by: Alvaro Dosil , alvaro.dosil@usc.es \n
--! 27/Feb/14 DGC Change "If" when setting s_word2 to a case ... generate. Questasim
--! doesn't like having an if that can take an array out of bounds.
-------------------------------------------------------------------------------
......@@ -47,17 +55,7 @@
--! some ports are redundant - e.g. trigger counter, others confusingly
--! labelled. Sort this out..
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.fmcTLU.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
ENTITY eventFormatter IS
GENERIC(
......@@ -65,33 +63,33 @@ ENTITY eventFormatter IS
g_IPBUS_WIDTH : positive := 32;
g_COUNTER_TRIG_WIDTH : positive := 32;
g_COUNTER_WIDTH : positive := 12;
g_EVTTYPE_WIDTH : positive := 4; -- Width of the event type word
g_EVTTYPE_WIDTH : positive := 4; --! Width of the event type word
--g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
g_NUM_EDGE_INPUTS : positive := 4; -- Number of edge inputs
g_NUM_TRIG_INPUTS : positive := 5 -- Number of trigger inputs
g_NUM_EDGE_INPUTS : positive := 4; --! Number of edge inputs
g_NUM_TRIG_INPUTS : positive := 5 --! Number of trigger inputs
);
PORT(
clk_4x_logic_i : IN std_logic; -- ! Rising edge active
clk_4x_logic_i : IN std_logic; --! Rising edge active
ipbus_clk_i : IN std_logic;
logic_strobe_i : IN std_logic; -- ! Pulses high once every 4 cycles of clk_4x_logic
logic_reset_i : IN std_logic; -- goes high to reset counters. Synchronous with clk_4x_logic
logic_strobe_i : IN std_logic; --! Pulses high once every 4 cycles of clk_4x_logic
logic_reset_i : IN std_logic; --! goes high to reset counters. Synchronous with clk_4x_logic
rst_fifo_i : IN std_logic; --! Goes high to reset FIFOs
buffer_full_i : IN std_logic; --! Goes high when output fifo full
trigger_i : IN std_logic; --! goes high to load trigger data. One cycle of clk_4x_logic
trigger_times_i : IN t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- Array of trigger times ( w.r.t. logic_strobe)
trigger_inputs_fired_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- high for each input that "fired"
trigger_cnt_i : IN std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0);
trigger_times_i : IN t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! Array of trigger times ( w.r.t. logic_strobe)
trigger_inputs_fired_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! high for each input that "fired"
trigger_cnt_i : IN std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0); --! Trigger count
shutter_i : IN std_logic;
shutter_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
spill_i : IN std_logic;
spill_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! High when rising edge
edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! High when falling edge
edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! Array of edge times ( w.r.t. logic_strobe)
edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! Array of edge times ( w.r.t. logic_strobe)
ipbus_i : IN ipb_wbus;
ipbus_o : OUT ipb_rbus;
data_strobe_o : OUT std_logic; -- goes high when data ready to load into event buffer
data_strobe_o : OUT std_logic; --! goes high when data ready to load into event buffer
event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
reset_timestamp_i : IN std_logic; --! Taking high causes timestamp to be reset. Combined with internal timestmap reset and written to reset_timestamp_o
reset_timestamp_o : OUT std_logic; --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
......
firmware/hdl/common/logic_clocks_rtl.vhd
View file @ faa17d06
......@@ -69,8 +69,9 @@ library unisim;
use unisim.vcomponents.all;
ENTITY logic_clocks IS
generic (
g_USE_EXTERNAL_CLK : integer := 1); -- --! Set to one to use clock from external clock
GENERIC(
g_USE_EXTERNAL_CLK : integer := 1
);
PORT(
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
......@@ -82,8 +83,8 @@ ENTITY logic_clocks IS
ipbus_o : OUT ipb_rbus;
strobe_16x_logic_o : OUT std_logic; -- strobes once every 4 cycles of clk_16x
strobe_4x_logic_o : OUT std_logic; -- one pulse every 4 cycles of clk_4x
extclk_p_b : IN std_logic; -- either external clock in, or a clock being driven out
extclk_n_b : IN std_logic;
extclk_p_b : INOUT std_logic; -- either external clock in, or a clock being driven out
extclk_n_b : INOUT std_logic;
DUT_clk_o : OUT std_logic;
logic_clocks_locked_o : OUT std_logic;
logic_reset_o : OUT std_logic -- Goes high to reset counters etc. Sync with clk_4x_logic
......@@ -91,7 +92,7 @@ ENTITY logic_clocks IS
-- Declarations
END logic_clocks ;
END ENTITY logic_clocks ;
--
ARCHITECTURE rtl OF logic_clocks IS
......
firmware/hdl/miniTLU/top_extphy_struct.vhd
View file @ faa17d06
......@@ -2,7 +2,7 @@
--
-- Created:
-- by - phdgc.users (voltar.phy.bris.ac.uk)
-- at - 13:20:39 08/26/15
-- at - 16:01:24 08/26/15
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1b (Build 2)
--
......@@ -65,7 +65,7 @@ END ENTITY top_extphy ;
--
-- Created:
-- by - phdgc.users (voltar.phy.bris.ac.uk)
-- at - 13:20:39 08/26/15
-- at - 16:01:24 08/26/15
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1b (Build 2)
--
......@@ -274,6 +274,9 @@ ARCHITECTURE struct OF top_extphy IS
);
END COMPONENT i2c_master;
COMPONENT logic_clocks
GENERIC (
g_USE_EXTERNAL_CLK : integer := 1
);
PORT (
ipbus_clk_i : IN std_logic ;
ipbus_i : IN ipb_wbus ;
......@@ -534,6 +537,9 @@ BEGIN
ipbus_o => ipbr(5)
);
I6 : logic_clocks
GENERIC MAP (
g_USE_EXTERNAL_CLK => 0
)
PORT MAP (
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(4),
......
firmware/hdl/test/DUTInterfaces_rtl.vhd deleted 100644 → 0
View file @ 492f0ddc
--=============================================================================
--! @file DUTInterfaces_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:09:50 11/09/12
--
--! @version v0.1
--
--! @details
--! Address map:\n
--! 5-bit decoded
--! 0x00000000 - DUT interface mode, two bits per DUT. Up to 12 inputs XXXXXXXXBBAA99887766554433221100\n
--! - mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
--!
--
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> Indicate if the DUT works under AIDA/EUDET style\n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
library unisim;
use unisim.VComponents.all;
ENTITY DUTInterfaces IS
GENERIC(
g_NUM_DUTS : positive := 3;
g_IPBUS_WIDTH : positive := 32
);
PORT(
--busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
--busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
clk_4x_logic_i : IN std_logic;
clk_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
ipbus_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic; -- ! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_i : IN std_logic; -- goes high when trigger logic issues a trigger
--shutter_i : IN std_logic; -- goes high when trigger logic issues a shutter
ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
--reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
--reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
--trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
--trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
--shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
--shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
output_0_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_0_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_1_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_1_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_2_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_2_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_3_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_3_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
veto_o : OUT std_logic -- goes high when one or more DUT are busy
);
-- Declarations
END ENTITY DUTInterfaces ;
--
ARCHITECTURE rtl OF DUTInterfaces IS
signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0); -- OR tree
signal s_veto : std_logic;
signal s_strobe_4x_logic_d1, clk_2x_logic : std_logic;
signal s_busy_from_dut , s_clk_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs not used
signal s_EnableOutput : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
constant c_N_CTRL : positive := 2;
constant c_N_STAT : positive := 2;
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
BEGIN
-- Dummy code.
s_intermediate_busy_or(0) <= '0';
--s_busy_from_dut(g_NUM_DUTS-1 downto 0) <= (others=>'0');
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
ipbus_registers: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => c_N_CTRL,
N_STAT => c_N_STAT
)
port map(
clk => ipbus_clk_i,
reset=> '0',--ipbus_reset_i ,
ipbus_in=> ipbus_i,
ipbus_out=> ipbus_o,
d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb=> open
);
-- Synchronize registers from logic clock to ipbus.
sync_status: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_4x_logic_i,
data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
-- Synchronize registers from logic clock to ipbus.
sync_ctrl: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_CTRL )
port map (
clk_input_i => ipbus_clk_i,
data_i => s_control_from_ipbus,
data_o => s_sync_control_from_ipbus,
clk_output_i => clk_4x_logic_i);
-- Map the control registers
s_DUT_mask <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
s_EnableOutput <= s_sync_control_from_ipbus(1);
-- Map the status registers
s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
s_status_to_ipbus(1) <= s_EnableOutput;
-- purpose: Writes in the positive pin of the signals an 80MHz clock and the strobe_4x_logic_i in the negative one.
--The output signals (one signal is an lvds pair) can be enabled independently in the s_EnableOutput via IPBus.
-- type : combinational
-- inputs : clk_2x_logic , strobe_4x_logic_i, s_EnableOutput
-- outputs: output_0_p, output_0_n, output_1_p, output_1_n, output_2_p, output_2_n, output_3_p, output_3_n
duts: for dut in 1 to g_NUM_DUTS generate
output_0_p_inst : OBUF
port map (
O => output_0_p(dut-1),
I => s_EnableOutput(0) and clk_2x_logic -- Buffer input
);
output_0_n_inst : OBUF
port map (
O => output_0_n(dut-1),
I => s_EnableOutput(0) and strobe_4x_logic_i -- Buffer input
);
output_1_p_inst : OBUF
port map (
O => output_1_p(dut-1),
I => s_EnableOutput(1) and clk_2x_logic -- Buffer input
);
output_1_n_inst : OBUF
port map (
O => output_1_n(dut-1),
I => s_EnableOutput(1) and strobe_4x_logic_i -- Buffer input
);
output_2_p_inst : OBUF
port map (
O => output_2_p(dut-1),
I => s_EnableOutput(2) and clk_2x_logic -- Buffer input
);
output_2_n_inst : OBUF
port map (
O => output_2_n(dut-1),
I => s_EnableOutput(2) and strobe_4x_logic_i -- Buffer input
);
output_3_p_inst : OBUF
port map (
O => output_3_p(dut-1),
I => s_EnableOutput(3) and clk_2x_logic -- Buffer input
);
output_3_n_inst : OBUF
port map (
O => output_3_n(dut-1),
I => s_EnableOutput(3) and strobe_4x_logic_i -- Buffer input
);
s_intermediate_busy_or(dut) <= s_intermediate_busy_or(dut-1) or
(s_busy_from_dut(dut-1) and
s_DUT_mask(dut-1));
end generate duts;
s_veto <= s_intermediate_busy_or(g_NUM_DUTS);
clk_2x_logic <= s_strobe_4x_logic_d1 or strobe_4x_logic_i; --80 MHz clock
-- purpose: register for internal signals and output signals
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
-- outputs: veto_o
register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
begin -- process register_signals
if rising_edge(clk_4x_logic_i) then
veto_o <= s_veto;
s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
s_reset_or_clk_to_dut <= ( others => (s_strobe_4x_logic_d1 or strobe_4x_logic_i));
s_trigger_to_dut <= ( others => trigger_i );
--shutter_to_dut <= ( others => shutter_i );
end if;
end process register_signals;
END ARCHITECTURE rtl;
firmware/hdl/test/top_extphy_struct.vhd deleted 100644 → 0
View file @ 492f0ddc
This diff is collapsed.
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/symbol.sb
View file @ faa17d06
......@@ -1139,7 +1139,7 @@ value "users"
)
(vvPair
variable "graphical_source_time"
value "13:20:39"
value "16:01:24"
)
(vvPair
variable "group"
......@@ -1259,7 +1259,7 @@ value "symbol"
)
(vvPair
variable "time"
value "13:20:39"
value "16:01:24"
)
(vvPair
variable "unit"
......@@ -2831,8 +2831,7 @@ g_EVENT_DATA_WIDTH positive 64
g_IPBUS_WIDTH positive 32
g_NUM_EDGE_INPUTS positive 4
g_SPILL_COUNTER_WIDTH positive 12
g_BUILD_SIMULATED_MAC integer 0
"
g_BUILD_SIMULATED_MAC integer 0 "
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
......@@ -3547,7 +3546,7 @@ xt "42000,0,42000,0"
tm "SyDeclarativeTextMgr"
)
)
lastUid 2679,0
lastUid 2702,0
okToSyncOnLoad 1
OkToSyncGenericsOnLoad 1
activeModelName "Symbol:CDM"
......
firmware/scripts/setup_simulation.sh 0 → 100644
View file @ faa17d06
#!/bin/sh
#
# script to build simulation environment ( Uses Modelsim/Questasim )
# Assumes all code has already been checked out by setup_workspace.sh
#
export FW_WORKSPACE=`pwd`
echo "Current directory (FW_WORKSPACE) = " $FW_WORKSPACE
export SIM_DIR=${FW_WORKSPACE}/workspace/simulation
if [ ! -d "$SIM_DIR" ]; then
echo "Making simulation directory" $SIM_DIR
mkdir $SIM_DIR
pushd $SIM_DIR
cp -v ${FW_WORKSPACE}/fmc-mtlu/firmware/simulation/scripts/setup.sh .
cp -v ${FW_WORKSPACE}/fmc-mtlu/firmware/simulation/scripts/add_files.tcl .
popd
fi
pushd $SIM_DIR
sh setup.sh
firmware/scripts/test_aida_tlu_internal_triggers_v2.py
View file @ faa17d06
......@@ -23,14 +23,37 @@ firmwareID=board.read("FirmwareId")
print "Firmware = " , hex(firmwareID)
print "Enabling DUT 1"
board.write("DUTMaskW",7)
print "Disable data recording"
board.write("Enable_Record_Data",0)
Enable_Record_Data = board.read("Enable_Record_Data")
print "Event recording flags read back as = ",Enable_Record_Data
print "Enabling no DUTs "
board.write("DUTMaskW",0)
DUTMask = board.read("DUTMaskR")
print "DUT mask read back as " , DUTMask
print "Disable Trigger veto by DUT Busy"
board.write("IgnoreDUTBusyW", 7)
IgnoreDUTBusyW = board.read("IgnoreDUTBusyR")
print "DUT ignore BUSY veto read back as " , IgnoreDUTBusyW
print "Disable Trigger veto by DUT Shutter"
board.write("IgnoreShutterVetoW", 1)
IgnoreShutterVetoW = board.read("IgnoreShutterVetoR")
print "DUT ignore shutter veto read back as " , IgnoreShutterVetoW
print "Turn off trigger veto"
board.write("TriggerVetoW",0)
TriggerVeto = board.read("TriggerVetoR")
print "Trigger veto read back as " , TriggerVeto
ExternalTriggerVeto = board.read("ExternalTriggerVetoR")
print "External veto = ", ExternalTriggerVeto
#TriggerInterval = 0xABC
TriggerInterval = 0x0000
TriggerInterval = 0xABC
#TriggerInterval = 0x0000
print "Setting internal trigger interval to " , TriggerInterval
board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
trigInterval = board.read("InternalTriggerIntervalR")
......
firmware/simulation/scripts/add_files.tcl
View file @ faa17d06
......@@ -85,8 +85,7 @@ project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ethernet/sim/eth_m
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/sim/hdl/clock_sim.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/pmtPulseGenerator_rtl.vhd
# Special file for linking to TimePix telescope:
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/TPx3_iface_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/T0_Shutter_Iface_rtl.vhd
project calculateorder
project close
......
firmware/simulation/scripts/setup.sh
View file @ faa17d06
#!/bin/sh
export MODELSIM_ROOT="/software/CAD/Mentor/2014_2015/HDS_2013.1b/questasim/"
#export MODELSIM_ROOT="/eda/mentor/2014-15/RHELx86/QUESTA-SV-AFV_10.4/questasim/"
#export MODELSIM_ROOT="/software/CAD/Mentor/2014_2015/HDS_2013.1b/questasim/"
export MODELSIM_ROOT="/eda/mentor/2014-15/RHELx86/QUESTA-SV-AFV_10.4/questasim/"
export ISE_VHDL_MTI="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.4/lin64/"
export ISE_VLOG_MTI="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.4/lin64/"
export FW_WORKSPACE=../../../..
#export FW_WORKSPACE=../../../..
vsim -c -do add_files.tcl
cp -r ../../../../workspace/ipbus/firmware/ethernet/sim/modelsim_fli ./
cp -r ${FW_WORKSPACE}/workspace/ipbus/firmware/ethernet/sim/modelsim_fli ./
cd modelsim_fli
./mac_fli_compile.sh
cd ..
......
firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd
View file @ faa17d06
......@@ -92,10 +92,6 @@ BEGIN
g_BUILD_SIMULATED_MAC => 1
)
PORT MAP (
T0_n_i => T0_n_i,
T0_p_i => T0_p_i,
TPix_Shutter_n_i => TPix_Shutter_n_i,
TPix_Shutter_p_i => TPix_Shutter_p_i,
busy_n_i => busy_n_i,
busy_p_i => busy_p_i,
cfd_discr_n_i => cfd_discr_n_i,
......
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