To be discussed:
- setting produced variable length with resistors/dip switch/companion
FPGA (via FMC)
- setting constructor ID/model ID with resistors
Specification
- Single width FMC mezzanine
(ANSI/VITA.57,
Chapter 3.2)
IMPORTANT: The FieldTR transformer is ~1 mm higher than what the standard permits. Due to that, the carrier board should have a cut out under the FMC board (see e.g. the SPEC board).
IMPORTANT: The FMC standard says a mezzanine should provide an EEPROM, but due to radiation tolerance requirements it is not desirable. There is a footprint to mount an EEPROM, but the component is not mounted by default. If there is a justified request, EEPROM can be emulated using the nanoFIP FPGA.
* nanoFIP interface:
- standard DB9 male connector with 4-40 UNC threaded bolt for cable
locking
- 2x1 2.54 mm pin header on a side
* FMC interface:
- FMC low pin count connector (ANSI/VITA.57, Table 3).
- Requires 12V & 3.3V as in the VITA.57 standard.
- LVTTL I/O levels.
- Unused pins in the nanoFIP FPGA will be routed to the FMC connector.
- Variable data transfer over an integrated memory accessiblewith an 8-bit-data, 10-bit-addr WISHBONE interconnection.
- Possibility of stand-alone mode with 16 input and 16 output lines without the need to transfer data to or from memory.
- Separate data valid outputs for each variable (consumed and
produced).
- JTAG to reprogram a companion FPGA (on the carrier board) using the
nanoFIP link.
TODO pinout*
* Reset (more):
- External pin available on the FMC connector (might be disconnected by removing a 0 ohm resistor)
- Addressed reset by broadcast consumed variable validated by station address as data
- Power-on reset
- Reset output available to external logic via the FMC connector
* Estimated power consumption (based on nanoFIP test report):
- 90 mA / 3.3V (FPGA 3.3V and 1.5V LDO; LEDs)
- 75 mA / 12V (5V LDO at 70% efficiency for FielDrive and FieldTR which
consume ~120 mA / 5V in total)
- 2 LEDs indicating TX/RX link activity. (TODO configurable?)
- JTAG connector (standard 2x5 2.54 mm or 1.27 mm pin header) Actel FlashPro 4 pinout) for the nanoFIP FPGA and a jumper to disable reprogramming.
- Radiation tolerance up to 200 Gy.
- 8 dip switches on a side/top to configure the station address (accessible without removing the mezzanine).
- Constructor and model IDs set by resistors.
Design constraints
* Board:
- Single width FMC form factor
- Cut out zone in the carrier board limits the area where the FieldTR transformer can be placed
- FIP 2x1 pin header has to be placed away from the cut out zone (it
should be possible to connect it to a carrier board with a female pin
header)
- DIP switches have to be placed on top, so they are accessible without
removing the board from the carrier
- Front panel:
- DB9 connector is almost of the same height as the front panel bezel. It has been checked with 3D models that the selected DB9 connector will fit.
Other designs
There is a number of designs that may serve as a reference for schematics:
- FMC MasterFIP: https://edms.cern.ch/ui/\#\!master/navigator/item?P:1187203503:1037329200:subDocs
- FGClite: https://edms.cern.ch/ui/\#\!master/navigator/item?P:1169840490:1067623240:subDocs
- nanoFIP Test Board: https://www.ohwr.org/project/nanofip-test-board
- Alstom board: http://cern-worldfip.web.cern.ch/cern-worldfip/Docs/Hardware%20Modules/Alstom%20Cards/CC130-131-132%20User%20Reference%20Manual-ENG.pdf
27 April 2017