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FMC TDC 1ns 5cha - Gateware
Commit 0178967d authored by egousiou's avatar egousiou
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vic on spec (not stable yet:s) 

git-svn-id: http://svn.ohwr.org/fmc-tdc@145 85dfdc96-de2c-444c-878d-45b388be74a9
parent 7102fab4
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hdl/syn/spec/syn_tdc.edf
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hdl/syn/spec/synplicity.ucf
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......@@ -8,71 +8,71 @@
#Begin clock constraints
# 1003 : define_clock {p:acam_refclk_p_i} -name {acam_refclk31_25} -freq {31.25} -clockgroup {default_clkgroup30__3}
# c:\fmc-tdc-master\copyoffmc-tdc-master\hdl\syn\spec\tdc_syn_constraints.sdc
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "acam_refclk_p_i" TNM_NET = "acam_refclk_p_i";
TIMESPEC "TS_acam_refclk_p_i" = PERIOD "acam_refclk_p_i" 32.000 ns HIGH 50.00%;
# 1004 : define_clock {n:gnum_interface_block.cmp_clk_in.rx_bufg_pll_x1} -name {gnum_clk200} -freq {200} -clockgroup {default_clkgroup31__4}
# c:\fmc-tdc-master\copyoffmc-tdc-master\hdl\syn\spec\tdc_syn_constraints.sdc
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "gnum_interface_block.sys_clk" TNM_NET = "gnum_interface_block_sys_clk";
TIMESPEC "TS_gnum_interface_block_sys_clk" = PERIOD "gnum_interface_block_sys_clk" 5.000 ns HIGH 50.00%;
# 1002 : define_clock {p:spec_clk_i} -name {spec_clk20} -freq {20} -clockgroup {default_clkgroup29__2}
# c:\fmc-tdc-master\copyoffmc-tdc-master\hdl\syn\spec\tdc_syn_constraints.sdc
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "spec_clk_i" TNM_NET = "spec_clk_i";
TIMESPEC "TS_spec_clk_i" = PERIOD "spec_clk_i" 50.000 ns HIGH 50.00%;
# 1001 : define_clock {p:tdc_clk_p_i} -name {tdc_clk125p} -freq {125} -clockgroup {default_clkgroup28__1}
# c:\fmc-tdc-master\copyoffmc-tdc-master\hdl\syn\spec\tdc_syn_constraints.sdc
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_clk_p_i" TNM_NET = "tdc_clk_p_i";
TIMESPEC "TS_tdc_clk_p_i" = PERIOD "tdc_clk_p_i" 8.000 ns HIGH 50.00%;
#End clock constraints
# 1018 : define_false_path -to {p:tdc_led_status_o}
# c:\fmc-tdc-master\copyoffmc-tdc-master\hdl\syn\spec\tdc_syn_constraints.sdc
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_status_o" TNM = "to_1018_0";
TIMESPEC "TS_1018_0" = TO "to_1018_0" TIG;
# 1019 : define_false_path -to {p:tdc_led_trig1_o}
# c:\fmc-tdc-master\copyoffmc-tdc-master\hdl\syn\spec\tdc_syn_constraints.sdc
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig1_o" TNM = "to_1019_0";
TIMESPEC "TS_1019_0" = TO "to_1019_0" TIG;
# 1020 : define_false_path -to {p:tdc_led_trig2_o}
# c:\fmc-tdc-master\copyoffmc-tdc-master\hdl\syn\spec\tdc_syn_constraints.sdc
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig2_o" TNM = "to_1020_0";
TIMESPEC "TS_1020_0" = TO "to_1020_0" TIG;
# 1021 : define_false_path -to {p:tdc_led_trig3_o}
# c:\fmc-tdc-master\copyoffmc-tdc-master\hdl\syn\spec\tdc_syn_constraints.sdc
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig3_o" TNM = "to_1021_0";
TIMESPEC "TS_1021_0" = TO "to_1021_0" TIG;
# 1022 : define_false_path -to {p:tdc_led_trig4_o}
# c:\fmc-tdc-master\copyoffmc-tdc-master\hdl\syn\spec\tdc_syn_constraints.sdc
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig4_o" TNM = "to_1022_0";
TIMESPEC "TS_1022_0" = TO "to_1022_0" TIG;
# 1023 : define_false_path -to {p:tdc_led_trig5_o}
# c:\fmc-tdc-master\copyoffmc-tdc-master\hdl\syn\spec\tdc_syn_constraints.sdc
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig5_o" TNM = "to_1023_0";
TIMESPEC "TS_1023_0" = TO "to_1023_0" TIG;
# 1024 : define_false_path -from {p:rst_n_a_i}
# c:\fmc-tdc-master\copyoffmc-tdc-master\hdl\syn\spec\tdc_syn_constraints.sdc
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "rst_n_a_i" TNM = "from_1024_0";
TIMESPEC "TS_1024_0" = FROM "from_1024_0" TIG;
# 1025 : define_false_path -from {i:gnum_interface_block.rst_reg}
# c:\fmc-tdc-master\copyoffmc-tdc-master\hdl\syn\spec\tdc_syn_constraints.sdc
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
INST "gnum_interface_block.rst_reg" TNM = "from_1025_0";
TIMESPEC "TS_1025_0" = FROM "from_1025_0" TIG;
......@@ -93,6 +93,6 @@ TIMESPEC "TS_1025_0" = FROM "from_1025_0" TIG;
# Location Constraints
PIN "svec_clk_ibuf_cb.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "cmp_tdc1_clks_rsts_mgment.tdc_clk125_gbuf.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "cmp_tdc_clks_rsts_mgment.tdc_clk125_gbuf.O" CLOCK_DEDICATED_ROUTE = FALSE;
# End of generated constraints
hdl/syn/spec/tdc.bin
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hdl/syn/spec/tdc.bit
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hdl/syn/spec/tdc_par_script.tcl
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cd <to /syn/spec>
ngdbuild -uc synplicity.ucf syn_tdc.edf
map -detail -w -timing -ol high syn_tdc.ngd
par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf
trce -v 32 -u par_tdc.ncd syn_tdc.pcf -o timing_report
#bitgen -w par_tdc.ncd tdc
bitgen -w -g Binary:Yes par_tdc.ncd tdc
ngdbuild -uc synplicity.ucf syn_tdc.edf;map -detail -w -timing -ol high syn_tdc.ngd;par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf;bitgen -w -g Binary:Yes par_tdc.ncd tdc
\ No newline at end of file
hdl/syn/spec/tdc_syn.prj
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......@@ -6,76 +6,92 @@
#project files
add_file -include "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
add_file -include "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ndf"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/genram_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/wishbone_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/gencores_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/sdb_meta_pkg.vhd"
add_file -vhdl -lib work "../src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/generic_async_fifo_wrapper.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_ser.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_des.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/pulse_sync_rtl.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core.vhd"
add_file -vhdl -lib work "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_crossbar/sdb_rom.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_crossbar/xwb_crossbar.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_crossbar/xwb_sdb_crossbar.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_slave_adapter/wb_slave_adapter.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/i2c_master_bit_ctrl.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/i2c_master_byte_ctrl.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/i2c_master_top.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/wb_i2c_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/xwb_i2c_master.vhd"
add_file -verilog -lib work "../src/ip_cores/wb_onewire_master/sockit_owm.v"
add_file -vhdl -lib work "../src/ip_cores/wb_onewire_master/wb_onewire_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_onewire_master/xwb_onewire_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_irq_controller/irq_controller_regs.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_irq_controller/irq_controller.vhd"
add_file -vhdl -lib work "../src/ip_cores/carrier_csr.vhd"
add_file -vhdl -lib work "../src/rtl/fmc_tdc_core.vhd"
add_file -vhdl -lib work "../src/rtl/free_counter.vhd"
add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/decr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clks_rsts_manager.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_retrig_ctrl.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "../src/rtl/circular_buffer.vhd"
add_file -vhdl -lib work "../src/rtl/irq_generator.vhd"
add_file -vhdl -lib work "../src/rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "../src/rtl/leds_manager.vhd"
add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
#add_file -include "../../ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
#add_file -include "../../ip_cores/mem_core/blk_mem_circ_buff_v6_4.ndf"
add_file -vhdl -lib work "../../ip_cores/gnum_core/gn4124_core_pkg.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "../../ip_cores/genrams/genram_pkg.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wishbone_pkg.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wbgen2/wbgen2_pkg.vhd"
add_file -vhdl -lib work "../../ip_cores/common/gencores_pkg.vhd"
add_file -vhdl -lib work "../../top/spec/sdb_meta_pkg.vhd"
add_file -vhdl -lib work "../../top/spec/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../../ip_cores/common/gc_extend_pulse.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/xilinx_cores/generic_async_fifo_wrapper.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/l2p_ser.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/p2l_des.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/pulse_sync_rtl.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/gn4124_core.vhd"
add_file -vhdl -lib work "../../ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_crossbar/sdb_rom.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_crossbar/xwb_crossbar.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_i2c_master/i2c_master_top.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_i2c_master/wb_i2c_master.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_i2c_master/xwb_i2c_master.vhd"
add_file -verilog -lib work "../../ip_cores/wishbone/wb_onewire_master/sockit_owm.v"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_onewire_master/wb_onewire_master.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wbgen2/wbgen2_dpssram.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wbgen2/wbgen2_eic.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wbgen2/wbgen2_fifo_async.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wbgen2/wbgen2_pkg.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_vic/vic_prio_enc.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_vic/wb_slave_vic.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_vic/wb_vic.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_vic/xwb_vic.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/carrier_csr.vhd"
add_file -vhdl -lib work "../../rtl/fmc_tdc_core.vhd"
add_file -vhdl -lib work "../../rtl/tdc_eic.vhd"
add_file -vhdl -lib work "../../rtl/fmc_tdc_mezzanine.vhd"
add_file -vhdl -lib work "../../rtl/free_counter.vhd"
add_file -vhdl -lib work "../../rtl/incr_counter.vhd"
add_file -vhdl -lib work "../../rtl/decr_counter.vhd"
add_file -vhdl -lib work "../../rtl/clks_rsts_manager.vhd"
add_file -vhdl -lib work "../../rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../../rtl/start_retrig_ctrl.vhd"
add_file -vhdl -lib work "../../rtl/data_formatting.vhd"
add_file -vhdl -lib work "../../rtl/data_engine.vhd"
add_file -vhdl -lib work "../../rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../../rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "../../rtl/circular_buffer.vhd"
add_file -vhdl -lib work "../../rtl/irq_generator.vhd"
add_file -vhdl -lib work "../../rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "../../rtl/leds_manager.vhd"
add_file -vhdl -lib work "../../top/spec/dma_eic.vhd"
add_file -vhdl -lib work "../../top/spec/top_tdc.vhd"
add_file -constraint -lib work "./tdc_syn_constraints.sdc"
......@@ -98,6 +114,7 @@ set_option -part_companion ""
set_option -compiler_compatible 0
set_option -resource_sharing 0
set_option -synthesis_onoff_pragma 0
set_option -resolve_mixed_driver 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
......
hdl/syn/spec/tdc_syn_constraints.sdc
View file @ 0178967d
# Synopsys, Inc. constraint file
# C:/FMC_TDC/evas_fmc_tdc/syn/tdc_syn_constraints.sdc
# Written on Wed Jul 17 10:47:25 2013
# Written on Fri Aug 09 16:09:57 2013
# by Synplify Premier with Design Planner, F-2012.03 Scope Editor
#
......@@ -22,6 +22,8 @@ define_clock {n:gnum_interface_block.cmp_clk_in.rx_bufg_pll_x1} -name {gnum_cl
#
# Inputs/Outputs
#
define_input_delay -disable -default 2.00 -improve 0.00 -route 0.00 -ref {tdc_clk125:r}
define_output_delay -disable -default 2.00 -improve 0.00 -route 0.00 -ref {tdc_clk125:r}
#
# Registers
......
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