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FMC TDC 1ns 5cha - Gateware
Commit 07fa5b23 authored by penacoba's avatar penacoba
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First version of binary file that obtains correct timestamps from the ACAM for any delay. 


git-svn-id: http://svn.ohwr.org/fmc-tdc@45 85dfdc96-de2c-444c-878d-45b388be74a9
parent e4bc3c96
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hdl/spec/syn/tdc_syn_constraints.sdc
View file @ 07fa5b23
......@@ -14,8 +14,8 @@ define_clock {n:gnum_interface_block.cmp_clk_in.rx_pllout_x1}
# -clockgroup default_clkgroup_0
# Inputs/Outputs
#
define_input_delay -default 2.00 -ref tdc_clk125:r
define_output_delay -default 2.00 -ref tdc_clk125:r
define_input_delay -default 2.00 -ref tdc_clk125:r
define_output_delay -default 2.00 -ref tdc_clk125:r
define_input_delay {p:p2l_clk_p_i } 2.00 -ref gnum_clk200:r
define_input_delay {p:p2l_clk_n_i } 2.00 -ref gnum_clk200:r
......@@ -51,10 +51,6 @@ define_input_delay {p:pll_refmon_i} 2.00 -ref spec_clk20:r
define_input_delay {p:pll_sdo_i} 2.00 -ref spec_clk20:r
define_input_delay {p:pll_status_i} 2.00 -ref spec_clk20:r
define_false_path -to {p:cs_n_o}
define_false_path -to {p:wr_n_o}
define_false_path -to {p:rd_n_o}
define_false_path -from {p:spec_aux0_i}
define_false_path -from {p:spec_aux1_i}
define_false_path -to {p:spec_aux2_o}
......@@ -71,10 +67,6 @@ define_false_path -to {p:tdc_led_trig3_o}
define_false_path -to {p:tdc_led_trig4_o}
define_false_path -to {p:tdc_led_trig5_o}
define_false_path -to {p:start_from_fpga_o}
#define_path_delay -from {p:adress_o} -to {p:wr_n_o} -max 2
# Attributes
# Global attribute definitions for improving implementation targetting Xilinx
define_global_attribute {syn_useioff} {1}
......@@ -210,6 +202,8 @@ define_attribute {p:term_en_3_o} {syn_loc} {A20}
define_attribute {p:term_en_4_o} {syn_loc} {H10}
define_attribute {p:term_en_5_o} {syn_loc} {E6}
define_attribute {p:tdc_in_fpga_5_i} {syn_loc} {AA14}
define_attribute {p:spec_aux0_i} {syn_loc} {C22}
define_attribute {p:spec_aux1_i} {syn_loc} {D21}
define_attribute {p:spec_aux2_o} {syn_loc} {G19}
......@@ -290,6 +284,8 @@ define_io_standard {term_en_3_o} syn_pad_type {LVCMOS_25}
define_io_standard {term_en_4_o} syn_pad_type {LVCMOS_25}
define_io_standard {term_en_5_o} syn_pad_type {LVCMOS_25}
define_io_standard {tdc_in_fpga_5_i} syn_pad_type {LVCMOS_25}
define_io_standard {spec_aux0_i} syn_pad_type {LVCMOS18}
define_io_standard {spec_aux1_i} syn_pad_type {LVCMOS18}
define_io_standard {spec_aux2_o} syn_pad_type {LVCMOS18}
......
hdl/spec/syn/tdc_syn_script.prj
View file @ 07fa5b23
......@@ -32,14 +32,15 @@ add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_nb_offset_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_retrigger_control.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
#add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
#add_file -vhdl -lib work "../src/rtl/test_tdc_pll/top_test_pll.vhd"
add_file -vhdl -lib work "../src/rtl/test_tdc_acam/top_test_acam.vhd"
#add_file -vhdl -lib work "../src/rtl/test_tdc_acam/top_test_acam.vhd"
add_file -constraint -lib work "./tdc_syn_constraints.sdc"
......@@ -102,7 +103,8 @@ set_option -write_vif 0
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./syn_tdc.edf"
#project -result_file "./test_tdc_pll/syn_tdc.edf"
project -result_file "./test_tdc_acam/syn_tdc.edf"
#project -result_file "./test_tdc_acam/syn_tdc.edf"
#project -run -fg synthesis
#project -run -fg timing
hdl/spec/syn/test_tdc_acam/rpt_top_tdc.areasrr
View file @ 07fa5b23
......@@ -11,10 +11,10 @@ SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 2683 100 %
REGISTERS 2721 100 %
LATCHES 0 0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 2683 (47.45 % Utilization)
Total SEQUENTIAL ELEMENTS in the block top_tdc: 2721 (46.41 % Utilization)
COMBINATIONAL LOGIC
......@@ -22,13 +22,13 @@ COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 1736 100 %
MUXCY 314 100 %
XORCY 317 100 %
LUTS 1806 100 %
MUXCY 344 100 %
XORCY 348 100 %
MULT18x18/MULT18x18S 2 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 2369 (41.90 % Utilization)
Total COMBINATIONAL LOGIC in the block top_tdc: 2500 (42.64 % Utilization)
MEMORY ELEMENTS
......@@ -69,7 +69,7 @@ Name Total elements Utilization Notes
-------------------------------------------------
PADS 122 100 %
=================================================
Total IO PADS in the block top_tdc: 122 (2.16 % Utilization)
Total IO PADS in the block top_tdc: 122 (2.08 % Utilization)
#### START OF Block RAM DETAILED REPORT ####
......
hdl/spec/syn/test_tdc_acam/rpt_top_tdc_areasrr.htm
View file @ 07fa5b23
......@@ -13,10 +13,10 @@ SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 2683 100 %
REGISTERS 2721 100 %
LATCHES 0 0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 2683 (47.45 % Utilization)
Total SEQUENTIAL ELEMENTS in the block top_tdc: 2721 (46.41 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
......@@ -25,13 +25,13 @@ COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 1736 100 %
MUXCY 314 100 %
XORCY 317 100 %
LUTS 1806 100 %
MUXCY 344 100 %
XORCY 348 100 %
MULT18x18/MULT18x18S 2 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 2369 (41.90 % Utilization)
Total COMBINATIONAL LOGIC in the block top_tdc: 2500 (42.64 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
......@@ -76,7 +76,7 @@ Name Total elements Utilization Notes
-------------------------------------------------
PADS 122 100 %
=================================================
Total IO PADS in the block top_tdc: 122 (2.16 % Utilization)
Total IO PADS in the block top_tdc: 122 (2.08 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
#### START OF Block RAM DETAILED REPORT ####
......
hdl/spec/syn/test_tdc_acam/run_options.txt
View file @ 07fa5b23
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/run_options.txt
#-- Written on Thu Jul 21 19:57:38 2011
#-- Written on Tue Aug 2 16:06:31 2011
#project files
......@@ -30,11 +30,12 @@ add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_nb_offset_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_retrigger_control.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "../src/rtl/test_tdc_acam/top_test_acam.vhd"
add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
add_file -constraint "./tdc_syn_constraints.sdc"
......
hdl/spec/syn/test_tdc_acam/scratchproject.prs
View file @ 07fa5b23
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/scratchproject.prs
#-- Written on Thu Jul 21 19:57:38 2011
#-- Written on Tue Aug 2 16:06:31 2011
#project files
......@@ -30,11 +30,12 @@ add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/s
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_nb_offset_gen.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_retrigger_control.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_engine.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd"
add_file -constraint "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn_constraints.sdc"
......
hdl/spec/syn/test_tdc_acam/syn_tdc.edf
View file @ 07fa5b23
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/test_tdc_acam/syn_tdc.map
View file @ 07fa5b23
Release 13.1 Map O.40d (lin64)
Xilinx Map Application Log File for Design 'top_tdc'
Design Information
------------------
Command Line : map -detail -w -timing -ol high syn_tdc.ngd
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Jul 21 19:58:37 2011
Mapping design into LUTs...
Writing file syn_tdc.ngm...
Running directed packing...
WARNING:Pack:2238 - Function generator symbol
"gnum_interface_block.cmp_p2l_dma_master.is_next_item_RNILBMH_o5" (Output
Signal = gnum_interface_block.cmp_p2l_dma_master.N_1514_i) has an invalid use
of the LUTNM constraint. There are no other function generator symbols with a
matching LUTNM constraint value (LUTNM=top_tdc_lutnm000341). The constraint
will be ignored.
WARNING:Pack:2238 - Function generator symbol
"gnum_interface_block.cmp_l2p_dma_master.target_addr_cnt_s_RNIGVVK_o6[1]"
(Output Signal = gnum_interface_block.N_701_i) has an invalid use of the
LUTNM constraint. There are no other function generator symbols with a
matching LUTNM constraint value (LUTNM=top_tdc_lutnm000246). The constraint
will be ignored.
WARNING:Pack:2238 - Function generator symbol
"gnum_interface_block.cmp_p2l_dma_master.p_addr_cnt.un91_p2l_dma_current_stat
e_lut6_2_o5" (Output Signal =
gnum_interface_block.cmp_p2l_dma_master.to_wb_fifo_wr_0) has an invalid use
of the LUTNM constraint. There are no other function generator symbols with a
matching LUTNM constraint value (LUTNM=top_tdc_lutnm000336). The constraint
will be ignored.
WARNING:Pack:2238 - Function generator symbol
"gnum_interface_block.cmp_l2p_dma_master.l2p_dma_current_state_ns_0_0_0_a3_0_
0_lut6_2_o6[2]" (Output Signal =
gnum_interface_block.cmp_l2p_dma_master.l2p_dma_current_state_ns_0_0_0_a3_0(2
)) has an invalid use of the LUTNM constraint. There are no other function
generator symbols with a matching LUTNM constraint value
(LUTNM=top_tdc_lutnm000268). The constraint will be ignored.
WARNING:Pack:2238 - Function generator symbol
"gnum_interface_block.cmp_l2p_dma_master.target_addr_cnt_s_RNIMRMO_o6[2]"
(Output Signal = gnum_interface_block.N_656) has an invalid use of the LUTNM
constraint. There are no other function generator symbols with a matching
LUTNM constraint value (LUTNM=top_tdc_lutnm000284). The constraint will be
ignored.
WARNING:Pack:2548 - The register "spec_aux2_o" has the property IOB=TRUE, but
was not packed into the ILOGIC component.
Running delay-based LUT packing...
Updating timing models...
WARNING:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing
constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE
(command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays
alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to
components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the
environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.
For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual; for more information on TRCE,
consult the Xilinx Command Line Tools User Guide "TRACE" chapter.
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
Number of Timing Constraints that were not applied: 4
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_gnum_interface_block_cmp_clk_in_rx_pll | SETUP | 2.452ns| 2.548ns| 0| 0
out_x1_0 = PERIOD TIMEGRP "gnum_interface | HOLD | -1.333ns| | 36| 47754
_block_cmp_clk_in_rx_pllout_x1_0" TS_gnum | MINPERIOD | 1.430ns| 3.570ns| 0| 0
_interface_block_cmp_clk_in_buf_P_clk PHA | | | | |
SE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
* TS_rx_error_o_gnum_interface_block_cmp_cl | MAXDELAY | -0.042ns| 3.042ns| 2| 84
k_in_rx_pllout_x1 = MAXDELAY FROM TIMEGRP | | | | |
"gnum_interface_block_cmp_clk_in_rx_pllo | | | | |
ut_x1" TO TIMEGRP "rx_error_o" 3 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_l2p_rdy_i_gnum_interface_block_cmp_clk | SETUP | 0.140ns| 2.860ns| 0| 0
_in_rx_pllout_x1 = MAXDELAY FROM TIMEGRP | HOLD | 1.036ns| | 0| 0
"l2p_rdy_i" TO TIMEGRP "gnum_interface_bl | | | | |
ock_cmp_clk_in_rx_pllout_x1" 3 ns | | | | |
----------------------------------------------------------------------------------------------------------
TIMEGRP "data_bus_io___" OFFSET = OUT 6 n | MAXDELAY | 1.147ns| 4.853ns| 0| 0
s AFTER COMP "tdc_clk_p_i" | | | | |
----------------------------------------------------------------------------------------------------------
TS_gnum_interface_block_cmp_clk_in_rx_pll | MINPERIOD | 1.430ns| 3.570ns| 0| 0
out_x1 = PERIOD TIMEGRP "gnum_interface_b | | | | |
lock_cmp_clk_in_rx_pllout_x1" 5 ns HIGH 5 | | | | |
0% | | | | |
----------------------------------------------------------------------------------------------------------
TS_gnum_interface_block_cmp_clk_in_buf_P_ | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
clk = PERIOD TIMEGRP "gnum_interface_bloc | | | | |
k_cmp_clk_in_buf_P_clk" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TIMEGRP "acam_refclk_i" OFFSET = IN 6 ns | SETUP | 3.066ns| 2.934ns| 0| 0
BEFORE COMP "tdc_clk_p_i" | | | | |
----------------------------------------------------------------------------------------------------------
TS_tdc_clk_p_i = PERIOD TIMEGRP "tdc_clk_ | SETUP | 4.687ns| 3.313ns| 0| 0
p_i" 8 ns HIGH 50% | HOLD | 0.132ns| | 0| 0
| MINPERIOD | 4.430ns| 3.570ns| 0| 0
----------------------------------------------------------------------------------------------------------
TIMEGRP "pll_cs_o" OFFSET = OUT 48 ns AFT | MAXDELAY | 41.655ns| 6.345ns| 0| 0
ER COMP "spec_clk_i" | | | | |
----------------------------------------------------------------------------------------------------------
TS_spec_clk_i = PERIOD TIMEGRP "spec_clk_ | SETUP | 45.192ns| 4.808ns| 0| 0
i" 50 ns HIGH 50% | HOLD | 0.353ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_gnum_interface_block_cmp_clk_in_buf_pl | N/A | N/A| N/A| N/A| N/A
l_fb_clk = PERIOD TIMEGRP "gnum_interface | | | | |
_block_cmp_clk_in_buf_pll_fb_clk" 5 ns HI | | | | |
GH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_gnum_interface_block_un1_cmp_clk_in = | N/A | N/A| N/A| N/A| N/A
PERIOD TIMEGRP "gnum_interface_block_un1_ | | | | |
cmp_clk_in" TS_gnum_interface_block_cmp_c | | | | |
lk_in_buf_P_clk / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
PATH "TS_1054_0_path" TIG | MAXDELAY | N/A| 3.422ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_1053_0_path" TIG | MAXDELAY | N/A| 3.422ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_1048_0_path" TIG | MAXDELAY | N/A| 3.422ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_1047_0_path" TIG | MAXDELAY | N/A| 3.422ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_1046_0_path" TIG | MAXDELAY | N/A| 3.379ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_1043_0_path" TIG | MAXDELAY | N/A| 4.100ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_1042_0_path" TIG | MAXDELAY | N/A| 3.402ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_1041_0_path" TIG | SETUP | N/A| 4.061ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_1040_0_path" TIG | MAXDELAY | N/A| 5.243ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_1039_0_path" TIG | MAXDELAY | N/A| 3.119ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_1038_0_path" TIG | MAXDELAY | N/A| 3.119ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_1037_0_path" TIG | MAXDELAY | N/A| 3.119ns| N/A| 0
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_gnum_interface_block_cmp_clk_in_buf_P_clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
| | Period | Actual Period | Timing Errors | Paths
Analyzed |
| Constraint | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct |
Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
|TS_gnum_interface_block_cmp_clk| 5.000ns| 2.800ns| 3.570ns| 0| 36| 0|
23176|
|_in_buf_P_clk | | | | | | |
|
| TS_gnum_interface_block_un1_cm| 2.500ns| N/A| N/A| 0| 0| 0|
0|
| p_clk_in | | | | | | |
|
| TS_gnum_interface_block_cmp_cl| 5.000ns| 3.570ns| N/A| 36| 0| 23176|
0|
| k_in_rx_pllout_x1_0 | | | | | | |
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
2 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 21 secs
Total CPU time at the beginning of Placer: 41 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:b988e37f) REAL time: 24 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:b988e37f) REAL time: 25 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:b988e37f) REAL time: 25 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features (Checksum:a4a8da5f) REAL time: 56 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:a4a8da5f) REAL time: 56 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:a4a8da5f) REAL time: 56 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:a4a8da5f) REAL time: 56 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:a4a8da5f) REAL time: 57 secs
Phase 9.8 Global Placement
.................................
.......................................................................................
................................................................................
...........................
Phase 9.8 Global Placement (Checksum:e7bfae8d) REAL time: 1 mins 20 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:e7bfae8d) REAL time: 1 mins 20 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:d3d2a1f6) REAL time: 2 mins 12 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:d3d2a1f6) REAL time: 2 mins 13 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:762d12d4) REAL time: 2 mins 13 secs
Total REAL time to Placer completion: 2 mins 20 secs
Total CPU time to Placer completion: 4 mins 29 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <vc_rdy_i(0)_IBUF> is incomplete. The signal does not drive any load pins in
the design.
WARNING:PhysDesignRules:367 - The signal <vc_rdy_i(1)_IBUF> is incomplete. The signal does not drive any load pins in
the design.
WARNING:PhysDesignRules:367 - The signal <p_wr_req_i(0)_IBUF> is incomplete. The signal does not drive any load pins in
the design.
WARNING:PhysDesignRules:367 - The signal <p_wr_req_i(1)_IBUF> is incomplete. The signal does not drive any load pins in
the design.
WARNING:PhysDesignRules:367 - The signal <tx_error_i_IBUF> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal <pll_sdo_i_IBUF> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal <pll_refmon_i_IBUF> is incomplete. The signal does not drive any load pins in
the design.
WARNING:PhysDesignRules:367 - The signal <err_flag_i_IBUF> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal <pll_status_i_IBUF> is incomplete. The signal does not drive any load pins in
the design.
WARNING:PhysDesignRules:367 - The signal <int_flag_i_IBUF> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization
data, both user defined and default, may be incorrect and should not be used. For more information, please reference
Xilinx Answer Record 39999.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 18
Slice Logic Utilization:
Number of Slice Registers: 3,115 out of 54,576 5%
Number used as Flip Flops: 3,115
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 2,216 out of 27,288 8%
Number used as logic: 1,938 out of 27,288 7%
Number using O6 output only: 1,411
Number using O5 output only: 19
Number using O5 and O6: 508
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 278
Number with same-slice register load: 277
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,060 out of 6,822 15%
Number of LUT Flip Flop pairs used: 3,431
Number with an unused Flip Flop: 663 out of 3,431 19%
Number with an unused LUT: 1,215 out of 3,431 35%
Number of fully used LUT-FF pairs: 1,553 out of 3,431 45%
Number of unique control sets: 164
Number of slice register sites lost
to control set restrictions: 645 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 135 out of 296 45%
Number of LOCed IOBs: 135 out of 135 100%
IOB Flip Flops: 75
Specific Feature Utilization:
Number of RAMB16BWERs: 4 out of 116 3%
Number of RAMB8BWERs: 1 out of 232 1%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 27 out of 376 7%
Number used as ILOGIC2s: 7
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 3 out of 376 1%
Number used as IODELAY2s: 3
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 60 out of 376 15%
Number used as OLOGIC2s: 40
Number used as OSERDES2s: 20
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 2 out of 58 3%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.38
Peak Memory Usage: 690 MB
Total REAL time to MAP completion: 2 mins 25 secs
Total CPU time to MAP completion: 4 mins 36 secs
Mapping completed.
See MAP report file "syn_tdc.mrp" for details.
%%% protect protected_file
hdl/spec/syn/test_tdc_acam/syn_tdc.sap
View file @ 07fa5b23
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/test_tdc_acam/syn_tdc.srl
View file @ 07fa5b23
......@@ -6,10 +6,10 @@
#
# Created by Synplify VHDL Compiler version comp500rc, Build 027R from Synplicity, Inc.
# Copyright 1994-2010 Synopsys, Inc. , All rights reserved.
# Synthesis Netlist written on Thu Jul 21 19:57:43 2011
# Synthesis Netlist written on Tue Aug 2 16:06:35 2011
#
#
#OPTIONS:"|-top|top_tdc|-dspmac|-pqdpadd|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-dfltencoding|onehot|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|off|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#OPTIONS:"|-top|top_tdc|-dspmac|-pqdpadd|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-dfltencoding|onehot|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|off|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"/afs/cern.ch/project/parc/elec/synplify/D-2010.03/linux/c_vhdl":1266628077
#CUR:"/afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/vhd/location.map":1266734607
#CUR:"/afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/vhd/std.vhd":1266627777
......@@ -30,12 +30,12 @@
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd":1311178071
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/dma_controller_wb_slave.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/tdc_core_pkg.vhd":1311079740
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/tdc_core_pkg.vhd":1311958660
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/free_counter.vhd":1305902268
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/incr_counter.vhd":1305902074
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/countdown_counter.vhd":1306314922
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd":1306489421
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_databus_interface.vhd":1311239445
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_databus_interface.vhd":1312293738
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_ser_s6.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_des_s6.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_decode32.vhd":1310389590
......@@ -47,9 +47,10 @@
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_s6.vhd":1311177581
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":1311001350
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd":1306400619
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_nb_offset_gen.vhd":1307641333
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd":1307642203
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":1311251491
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_retrigger_control.vhd":1312210529
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_engine.vhd":1312293985
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd":1312216371
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":1312205957
f "/afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/vhd/std.vhd"; # file 0
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"; # file 1
......@@ -118,11 +119,13 @@ f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.v
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd"; # file 33
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_nb_offset_gen.vhd"; # file 34
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_retrigger_control.vhd"; # file 34
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd"; # file 35
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_engine.vhd"; # file 35
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd"; # file 36
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd"; # file 36
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd"; # file 37
af .is_vhdl 1;
@E
@
......@@ -317,6 +320,210 @@ j9RRRR0Csk,DVN#VC,NCD#;-
y---------------------------------
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---------------------------------@-
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SMP8_NCDkr:d4jV9=NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,k0sCN,VD,#CV#NDCH
SM=Os0Csk
CSs#=C0OMFk0_CssCC#0O
SF0kM_M8FCH=IMI8F_PHMCCs08O
SkCssMP0_NCDkr:d4jk9=MI4_HFM8IF_OkCM0s4rd:;j9
RNH3M#$_Ck#s__#bNNsl"#RI0H8E;R"
RNHI0H8E.Rd;R
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49RRRRk_M.NlON_#sHCs_CsNVDo__bFb;
Rd@@n4:4ng:d:n44:R(cNPM8RNNOlN_VDHD_MD0VNbo__NFRO_NlVDND_0HMVoDN_Fb_RH#_MV0_DrNojR9
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-y---------------------------------
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......@@ -398,114 +605,119 @@ F;N3HRs_0DFosHMCNlRO"N "_F;
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R.@@.U:4d.:d:d4U:Rdd0RsH8NN0_#Lk__HF4jr49NR80LN_kH#_Fr_.4Rj98_N0Hjr49CRI_;HR
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R.@@.U:4d.:d:d4U:Rdd0RsH8NN0_#Lk__HF4Ur49NR80LN_kH#_Fr_.4RU98_N0HUr49CRI_;HR
[bRFRHM8NN0_#Lk__HF.gr49NR80LN_kH#_Fr_.4Rg98NN0_#Lk_rHF4;g9
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RH[FMNR80LN_kH#_Fr_..Rj98NN0_#Lk__HF.jr.9NR80LN_kH#_Fjr.9b;
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R.@@.U:4d.:d:d4U:Rdd0RsH8NN0_#Lk__HF4.r.9NR80LN_kH#_Fr_..R.98_N0H.r.9CRI_;HR
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R.@@.U:4d.:d:d4U:Rdd0RsH8NN0_#Lk__HF4cr.9NR80LN_kH#_Fr_..Rc98_N0Hcr.9CRI_;HR
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R.@@.g:4c6:d:c4g:RcjHRMPsM8__sFR8__MF8Rs;R
b@.@.:64g::d64:g6cHjRMIPRs__MFsRI_FM_R;Is
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9;b@R@.4.:jcd::d4j:b(RlRkGss8R8NRVD,#CNlON_08NN0_#rRn90Csk,NNOlN_80#N_09r6Rk0sCO,NN8l_N_0N#c0r9R
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R.@@.j:.(d:c:(.j:RcUHRMPFbk0ks0_C#oH0#Cs\#3O_FM__FdRkk0b0C_so0H#C\s#3_O#M__Fd#RO;R
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H;N3HRs_0DFosHMCNlR8"s_FM_"y;
---------------------------------@-
@
ftell;
@E@MR@ng:j:((4nj:j:((4k6RMHH#lARQz1w7RM#$_NLDOL _F
G;N3PRCCG0sDMNR
......@@ -1368,10 +1580,10 @@ R4@@6(:4(::U4:((gMRHPMRk40_#N_0C4MRk40_#N_0C4MRk40_#N;0C
@bR@:464:((U(:4(R:gFRsPk_M4#00NCR_.k_M4#00NCR_.kjMd_N#00#CR0CN0r;c9
@bR@:464:((U(:4(R:gHRMPk_M4#00NCR_dk_M4#00NCR_dk_M4#00NC;_.
@bR@:464:66c6:46R:6NPM8R4kM_kOFM40__l#JkRGNk_M4OMFk0__4#kJlGONRF0kM_#4_JGlkN0R#Nr0C.
9;b@R@d6n:4dg:64:6g6:dR8NMPFROk_M04J_#lNkG_O4RF0kM_#4_JGlkNR_4k_M4L$k#80R#Nr0CdO9RF0kM_#4_JGlkNb;
Rd@@n4:6g6:d:g64:Rd6NPM8RDON_ OD_#j_JGlkNNRODD_O __j#kJlG#NR0CN0gkURM#4_0CN0_
9;b@R@d6(:dd.:6d:6.6:dR8NMPFROk_M04J_#lNkG_O4RF0kM_#4_JGlkNR_4k_M4L$k#80R#Nr0CdO9RF0kM_#4_JGlkNb;
Rd@@(d:6.6:d:.6d:Rd6NPM8RDON_ OD_#j_JGlkNNRODD_O __j#kJlG#NR0CN0gkURM#4_0CN0_
4;b@R@4c6:4.U:c4:cUn:6RPHMR4kM_DON_ OD_#j_JGlkNMRk4N_ODD_O __j#kJlGONRNOD_Dj __l#Jk;GN
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R4@@66:46::c4:666VR8VRsCO_NDORD O_NDORD #00NC__4#kJlGsNRGk_LVbo_DGD_4FRM0G_s_VLkb_DDD8O
RRRR4kM_DON_ OD_#j_JGlkNN;
......@@ -7193,55 +7405,6 @@ Rg@@:(n.c::6nc.(:86RORRmmy;
ftell;
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";NIPRHE80R;d.
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";
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;
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b@g@4::64.6(:4(:dR8N8R4kM_DPNkdCr.9:4R4kM_DPNkdCr.9:4RDPNkdCr49:jROHMsb;
R4@@g.:c:cc:.R:6lRkGOMFk0P\3NCDk_d6r49:jRkOFM30\PkNDCr_6dj4:9MRk4N_PDrkCd4.:9R
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C;b@R@4dg:n::(d4n:48R#VRVsPkNDC4rd:Rj9PkNDC4rd:Rj9OMFk0P\3NCDk_d6r49:jR ODR#sCC
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R4@@g.:c:cc:.R:6FRsPk_M4PkNDCR_4k_M4PkNDCR_4OMFk0k\3MP._NCDkRkOFM80_F_MCjJ_#lNkG;R
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---------------------------------@-
ftell;
@E@MR@:d.d(.:::d..IjRFRs O_D s_#0lNNMossR0
D;N3PRHE#P84DR;P
......@@ -7595,7 +7758,7 @@ H;N3HRs_0DFosHMCNlRH"L0M_H8"CG;-
y---------------------------------
@
ftell;
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......@@ -7621,294 +7784,320 @@ FRs \N"/VO#/C3sMOCE/MCo/8ON/8k#_##Cs/CoVsMMN8s/bFO[C00#/8#O/ssO/0HD/M_OsOMFk03Cs
Is\ R"V/N#C/OsOM3EM/Co8/CN8/O##_kC/s#osVCM8NM/Fbs[0CO#8/0Os/#O0/sDF/Ok8M0F_IMOMFk03CsP\E8"F
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FRs \N"/VO#/C3sMOCE/MCo/8ON/8k#_##Cs/CoVsMMN8s/bFO[C00#/8#O/ssO/0FD/MEC_xC_oME3P8
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Is\ R"V/N#C/OsOM3EM/Co8/CN8/O##_kC/s#osVCM8NM/Fbs[0CO#8/0Os/#O0/sDN/80VN_FNsl0M0HoE3P8
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\""
;
@HR@:dndUn:::dn4snR#M0__HN_R0s#_NM__
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Is\ R"V/N#C/OsOM3EM/Co8/CN8/O##_kC/s#osVCM8NM/Fbs[0CO#8/0Os/#O0/sDO/NN0l_HOlCFsM0FHD_Ms0CVCNO38PE\I"
FRs \N"/VO#/C3sMOCE/MCo/8ON/8k#_##Cs/CoVsMMN8s/bFO[C00#/8#O/ssO/0ND/O_Nl8NN0L_k#HCM0sOVNCE3P8
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"
@HR@:d(dUn:::dn4snR#M0__HN_R0s#_NM__
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@HR@:dndUU:::dU4bUR.OD_Db __bHR.OD_Db __
@HR@:d(dUU:::dU4bUR.OD_Db __bHR.OD_Db __
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";
@HR@:dndUg:::dg4bUR.OD_DM __bHR.OD_DM __
@HR@:d(dUg:::dg4bUR.OD_DM __bHR.OD_DM __
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";
@HR@:dncUj:::cj4b(R.8D_N_0NH6r4:Rj9b_.D8NN0_4Hr69:j;H
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NR03sDs_FHNoMl"CRb_.D8NN0_;H"
@HR@:dncU4:::c44bgR.8D_VlsNCR_Hb_.D8NVslHC_;H
@HR@:d(cU4:::c44bgR.8D_VlsNCR_Hb_.D8NVslHC_;H
NR03sDs_FHNoMl"CRb_.D8NVslHC_"
;
@HR@:dncU.:::c.4bUR.PD_N8DH_bHR.PD_N8DH_
@HR@:d(cU.:::c.4bUR.PD_N8DH_bHR.PD_N8DH_
H;N3HRs_0DFosHMCNlR."bDN_PD_H8H
";
@FR@:dncUd:::cd4bnR.sD_8F$_RDb._$s8_
@FR@:d(cUd:::cd4bnR.sD_8F$_RDb._$s8_
F;N3HRs_0DFosHMCNlR."bD8_s$"_F;
@HR@:dncUc:::cc4b(R__Iss_CJH:r4jb9R__Iss_CJH:r4j
@HR@:d(cUc:::cc4b(R__Iss_CJH:r4jb9R__Iss_CJH:r4j
9;N3HRs_0DFosHMCNlR_"bIss_CHJ_"
;
@FR@:dncU6:::c64b(R__Iss_8$F:r4jb9R__Iss_8$F:r4j
@FR@:d(cU6:::c64b(R__Iss_8$F:r4jb9R__Iss_8$F:r4j
9;N3HRs_0DFosHMCNlR_"bIss_8F$_"
;
@FR@:dncUn:::cn4s(RGs_Cs_FsFGRs_sCsFFs_;H
@FR@:d(cUn:::cn4s(RGs_Cs_FsFGRs_sCsFFs_;H
NR03sDs_FHNoMl"CRsCG_sssF_;F"
@HR@:dncU(:::c(4P6RO8_s$r_H49:jR_POs_8$H:r4j
@HR@:d(cU(:::c(4P6RO8_s$r_H49:jR_POs_8$H:r4j
9;N3HRs_0DFosHMCNlRO"P_$s8_;H"
@FR@:dncUg:::cg4DUR.Ob_Db __DFR.Ob_Db __
@FR@:d(cUg:::cg4DUR.Ob_Db __DFR.Ob_Db __
F;N3HRs_0DFosHMCNlR."DbD_O __bF
";
@FR@:dn6Uj:::6j4DUR.Ob_DM __DFR.Ob_DM __
@FR@:d(6Uj:::6j4DUR.Ob_DM __DFR.Ob_DM __
F;N3HRs_0DFosHMCNlR."DbD_O __MF
";
@FR@:dn6U4:::644D(R.8b_N_0NF6r4:Rj9D_.b8NN0_4Fr69:j;H
@FR@:d(6U4:::644D(R.8b_N_0NF6r4:Rj9D_.b8NN0_4Fr69:j;H
NR03sDs_FHNoMl"CRD_.b8NN0_;F"
@FR@:dn6U.:::6.4DgR.8b_VlsNCR_FD_.b8NVslFC_;H
@FR@:d(6U.:::6.4DgR.8b_VlsNCR_FD_.b8NVslFC_;H
NR03sDs_FHNoMl"CRD_.b8NVslFC_"
;
@FR@:dn6Ud:::6d4DUR.Pb_N8DH_DFR.Pb_N8DH_
@FR@:d(6Ud:::6d4DUR.Pb_N8DH_DFR.Pb_N8DH_
F;N3HRs_0DFosHMCNlR."DbN_PD_H8F
";
@FR@:dn6Uc:::6c4DnR.Cb_8FL_RbD._LC8_
@FR@:d(6Uc:::6c4DnR.Cb_8FL_RbD._LC8_
F;N3HRs_0DFosHMCNlR."Db8_CL"_F;
@HR@:dn6U6:::664DnR.sb_8H$_RbD._$s8_
@HR@:d(6U6:::664DnR.sb_8H$_RbD._$s8_
H;N3HRs_0DFosHMCNlR."Db8_s$"_H;
@HR@:dn6Un:::6n4D(R__Iss_8$H:r4jD9R__Iss_8$H:r4j
@HR@:d(6Un:::6n4D(R__Iss_8$H:r4jD9R__Iss_8$H:r4j
9;N3HRs_0DFosHMCNlR_"DIss_8H$_"
;
@HR@:dn6U(:::6(4bgR__s888_s$r_H49:jRsb_8__8s_8$H:r4j
@HR@:d(6U(:::6(4bgR__s888_s$r_H49:jRsb_8__8s_8$H:r4j
9;N3HRs_0DFosHMCNlR_"bs88__$s8_;H"
@HR@:dn6UU:::6U40(RGs_Cs_FsHGR0_sCsFHs_;H
@HR@:d(6UU:::6U40(RGs_Cs_FsHGR0_sCsFHs_;H
NR03sDs_FHNoMl"CR0CG_sssF_;H"
@FR@:dn6Ug:::6g4HcRsbJ__HFRsbJ__
@FR@:d(6Ug:::6g4HcRsbJ__HFRsbJ__
F;N3HRs_0DFosHMCNlRs"HJ__bF
";
@FR@:dnnUj:::nj4#cRbCNs_#FRbCNs_
@FR@:d(nUj:::nj4#cRbCNs_#FRbCNs_
F;N3HRs_0DFosHMCNlRb"#N_sCF
";N3HR#_$MM#FN#MHol0CMR
4;
@HR@:dnnUd:::nd.NjRO_NlsOCVDH _RNNOlC_sV OD_
@HR@:d(nUd:::nd.NjRO_NlsOCVDH _RNNOlC_sV OD_
H;N3HRs_0DFosHMCNlRO"NNsl_CDVO "_H;
@HR@:dnnUc:::nc4b6RDDD_8R_Hb_DDDH8_;H
@HR@:d(nUc:::nc4b6RDDD_8R_Hb_DDDH8_;H
NR03sDs_FHNoMl"CRb_DDDH8_"
;
@HR@:dnnU6:::n64bgRDsD_CFVlMR_Hb_DDslCVFHM_;H
@HR@:d(nU6:::n64bgRDsD_CFVlMR_Hb_DDslCVFHM_;H
NR03sDs_FHNoMl"CRb_DDslCVFHM_"
;
@HR@:dnnUn:::nn4bnRD#D_8HF_RDbD_F#8_
@HR@:d(nUn:::nn4bnRD#D_8HF_RDbD_F#8_
H;N3HRs_0DFosHMCNlRD"bD8_#F"_H;
@HR@:dnnU(:::n(4bgRD#D_0kN0#R_Hb_DD#00NkH#_;H
@HR@:d(nU(:::n(4bgRD#D_0kN0#R_Hb_DD#00NkH#_;H
NR03sDs_FHNoMl"CRb_DD#00NkH#_"
;
@HR@:dnnUU:::nU40UR8OO_Db __0HR8OO_Db __
@HR@:d(nUU:::nU40UR8OO_Db __0HR8OO_Db __
H;N3HRs_0DFosHMCNlR8"0OD_O __bH
";
@HR@:dnnUg:::ng40UR8OO_DM __0HR8OO_DM __
@HR@:d(nUg:::ng40UR8OO_DM __0HR8OO_DM __
H;N3HRs_0DFosHMCNlR8"0OD_O __MH
";
@FR@:dn(U4:::(44b6RDOD_#R_Fb_DDOF#_;H
@FR@:d((U4:::(44b6RDOD_#R_Fb_DDOF#_;H
NR03sDs_FHNoMl"CRb_DDOF#_"
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@FR@:dn(U.:::(..b4RD8D_N#O_$_MOFDRbDN_8O$_#MFO_;H
@FR@:d((U.:::(..b4RD8D_N#O_$_MOFDRbDN_8O$_#MFO_;H
NR03sDs_FHNoMl"CRb_DD8_NO#O$M_;F"
@FR@:dn(Ud:::(d4bnRD#D_8FH_RDbD_H#8_
@FR@:d((Ud:::(d4bnRD#D_8FH_RDbD_H#8_
F;N3HRs_0DFosHMCNlRD"bD8_#H"_F;
@FR@:dn(Uc:::(c4b(RD#D_O_D FDRbDO_#DF _;H
@FR@:d((Uc:::(c4b(RD#D_O_D FDRbDO_#DF _;H
NR03sDs_FHNoMl"CRb_DD# OD_;F"
@HR@:dn(U(:::((4C(RsVs_D_NoHsRCsD_VNHo_;H
@HR@:d((U(:::((4C(RsVs_D_NoHsRCsD_VNHo_;H
NR03sDs_FHNoMl"CRC_ssVoDN_;H"
@HR@:dn(UU:::(U4H(RMV0_D_NoHMRH0D_VNHo_;H
@HR@:d((UU:::(U4H(RMV0_D_NoHMRH0D_VNHo_;H
NR03sDs_FHNoMl"CRH_M0VoDN_;H"
@FR@:dnUUj:::Uj4#UR00Ns_#8H_#FR00Ns_#8H_
@FR@:d(UUj:::Uj4#UR00Ns_#8H_#FR00Ns_#8H_
F;N3HRs_0DFosHMCNlR0"#N_s08_H#F
";
@FR@:dnUU4:::U4.#cR00Ns_FVslb_VoFN_RN#0sV0_s_FlVNbo_
@FR@:d(UU4:::U4.#cR00Ns_FVslb_VoFN_RN#0sV0_s_FlVNbo_
F;N3HRs_0DFosHMCNlR0"#N_s0VlsF_oVbN"_F;
@FR@:dnUU.:::U.4#(R0_Fb8_H#F0R#F8b_HF#_;H
@FR@:d(UU.:::U.4#(R0_Fb8_H#F0R#F8b_HF#_;H
NR03sDs_FHNoMl"CR#b0F_#8H_;F"
@LR@:dnUU6:::U648URN_0NL_k#H.Fr(9:jR08NNk_L#F_Hr:.(j
@LR@:d(UU6:::U648URN_0NL_k#H.Fr(9:jR08NNk_L#F_Hr:.(j
9;N3HRs_0DFosHMCNlRN"80LN_kH#_F
";
@HR@:dnUUn:::Un4C.RVH4_R4CV_
@HR@:d(UUn:::Un4C.RVH4_R4CV_
H;N3HRs_0DFosHMCNlRV"C4"_H;
@HR@:dnUU(:::U(4C.RVH._R.CV_
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H;N3HRs_0DFosHMCNlRV"C."_H;
@HR@:dnUUU:::UU4D.RVH4_R4DV_
@HR@:d(UUU:::UU4D.RVH4_R4DV_
H;N3HRs_0DFosHMCNlRV"D4"_H;
@HR@:dnUUg:::Ug4D.RVH._R.DV_
@HR@:d(UUg:::Ug4D.RVH._R.DV_
H;N3HRs_0DFosHMCNlRV"D."_H;
@FR@:dngU4:::g44NnR8C8s#F#_rjd:98RN8#sC#r_Fd9:j;H
@FR@:d(gU4:::g44NnR8C8s#F#_rjd:98RN8#sC#r_Fd9:j;H
NR03sDs_FHNoMl"CRNs88C_##F
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@FR@:dngU.:::g.4OdR#__MF#RO_FM_;H
@FR@:d(gU.:::g.4OdR#__MF#RO_FM_;H
NR03sDs_FHNoMl"CROM#__;F"
@FR@:dngUd:::gd4FdRC__MFCRF_FM_;H
@FR@:d(gUd:::gd4FdRC__MFCRF_FM_;H
NR03sDs_FHNoMl"CRFMC__;F"
@FR@:dngUc:::gc4sdR8__MF8Rs_FM_;H
@FR@:d(gUc:::gc4sdR8__MF8Rs_FM_;H
NR03sDs_FHNoMl"CRsM8__;F"
@FR@:dngU6:::g64IdRs__MFsRI_FM_;H
@FR@:d(gU6:::g64IdRs__MFsRI_FM_;H
NR03sDs_FHNoMl"CRIMs__;F"
@FR@:dngUU:::gU.ljRk_0CHkMb0F#_R0lkCM_Hb#k0_
@FR@:d(gUU:::gU.ljRk_0CHkMb0F#_R0lkCM_Hb#k0_
F;N3HRs_0DFosHMCNlRk"l0HC_M0bk#"_F;
@FR@:dngUg:::gg.0dR8DO_C#8_0kN0#R_F0_8OD_C8#00Nk
@FR@:d(gUg:::gg.0dR8DO_C#8_0kN0#R_F0_8OD_C8#00Nk
#;N3HRs_0DFosHMCNlR8"0OC_D80_#N#0k_;F"
@FR@:dn4:jjUj:4j.:.RO08_8DC_H0soF4_RO08_8DC_H0soF4_;H
@FR@:d(4:jjUj:4j.:.RO08_8DC_H0soF4_RO08_8DC_H0soF4_;H
NR03sDs_FHNoMl"CR0_8OD_C80osH4"_F;
@FR@:dn4:j4Uj:44.:.RO08_8DC_H0soF._RO08_8DC_H0soF._;H
@FR@:d(4:j4Uj:44.:.RO08_8DC_H0soF._RO08_8DC_H0soF._;H
NR03sDs_FHNoMl"CR0_8OD_C80osH."_F;
@FR@:dn4:j.Uj:4..:.RO08_8DC_H0soFd_RO08_8DC_H0soFd_;H
@FR@:d(4:j.Uj:4..:.RO08_8DC_H0soFd_RO08_8DC_H0soFd_;H
NR03sDs_FHNoMl"CR0_8OD_C80osHd"_F;
@FR@:dn4:jdUj:4d.:.RO08_8DC_H0soFc_RO08_8DC_H0soFc_;H
@FR@:d(4:jdUj:4d.:.RO08_8DC_H0soFc_RO08_8DC_H0soFc_;H
NR03sDs_FHNoMl"CR0_8OD_C80osHc"_F;
@FR@:dn4:jcUj:4c.:.RO08_8DC_H0soF6_RO08_8DC_H0so
6;N3HRs_0DFosHMCNlR8"0OC_D8s_0H_o6F
";
@FR@:dn4:j6Uj:46U:4Rs0ClM_C_F4_Rs0ClM_C_F4_;H
@FR@:d(4:jcUj:4c.:.RO08_8DC_H0soF6_RO08_8DC_H0soF6_;H
NR03sDs_FHNoMl"CR0_8OD_C80osH6"_F;
@FR@:d(4:j6Uj:46U:4Rs0ClM_C_F4_Rs0ClM_C_F4_;H
NR03sDs_FHNoMl"CR0lCs__CM4"_F;
@FR@:dn4:jnUj:4nU:4Rs0ClM_C_F._Rs0ClM_C_F._;H
@FR@:d(4:jnUj:4nU:4Rs0ClM_C_F._Rs0ClM_C_F._;H
NR03sDs_FHNoMl"CR0lCs__CM."_F;
@FR@:dn4:j(Uj:4(U:4Rs0ClM_C_Fd_Rs0ClM_C_Fd_;H
@FR@:d(4:j(Uj:4(U:4Rs0ClM_C_Fd_Rs0ClM_C_Fd_;H
NR03sDs_FHNoMl"CR0lCs__CMd"_F;
@FR@:dn4:jUUj:4UU:4Rs0ClM_C_Fc_Rs0ClM_C_Fc_;H
@FR@:d(4:jUUj:4UU:4Rs0ClM_C_Fc_Rs0ClM_C_Fc_;H
NR03sDs_FHNoMl"CR0lCs__CMc"_F;
@FR@:dn4:jgUj:4gU:4Rs0ClM_C_F6_Rs0ClM_C_F6_;H
@FR@:d(4:jgUj:4gU:4Rs0ClM_C_F6_Rs0ClM_C_F6_;H
NR03sDs_FHNoMl"CR0lCs__CM6"_F;
@HR@:dn4:4.U4:4.U:4RC#bOk_NGHj_RC#bOk_NGHj_;H
@HR@:d(4:4.U4:4.U:4RC#bOk_NGHj_RC#bOk_NGHj_;H
NR03sDs_FHNoMl"CR#ObC_GNkj"_H;
@HR@:dn4:4dU4:4dU:4RC#bOk_NGH4_RC#bOk_NGH4_;H
@HR@:d(4:4dU4:4dU:4RC#bOk_NGH4_RC#bOk_NGH4_;H
NR03sDs_FHNoMl"CR#ObC_GNk4"_H;
@FR@:dn4:4cU4:4cU:4RC#bOk_NGF._RC#bOk_NGF._;H
@FR@:d(4:4cU4:4cU:4RC#bOk_NGF._RC#bOk_NGF._;H
NR03sDs_FHNoMl"CR#ObC_GNk."_F;
@FR@:dn4:46U4:46U:4RC#bOk_NGFd_RC#bOk_NGFd_;H
@FR@:d(4:46U4:46U:4RC#bOk_NGFd_RC#bOk_NGFd_;H
NR03sDs_FHNoMl"CR#ObC_GNkd"_F;
@FR@:dn4:4nU4:4nU:4RC#bOk_NGFc_RC#bOk_NGFc_;H
@FR@:d(4:4nU4:4nU:4RC#bOk_NGFc_RC#bOk_NGFc_;H
NR03sDs_FHNoMl"CR#ObC_GNkc"_F;
@FR@:dn4:4(U4:4(U:4RC#bOk_NGF6_RC#bOk_NGF6_;H
@FR@:d(4:4(U4:4(U:4RC#bOk_NGF6_RC#bOk_NGF6_;H
NR03sDs_FHNoMl"CR#ObC_GNk6"_F;
@FR@:dn4:4UU4:4Ud:.RC#bOC_D8s_oC_CMFbR#CDO_Co8_sMCC_
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F;N3HRs_0DFosHMCNlRb"#CDO_Co8_sMCC_;F"
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NR03sDs_FHNoMl"CR#ObC_8DC_8sC_;F"
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NS80r_Hdj4:9#=OsN_80r_Idj4:9#
S0HL_=sO#_L#0
......@@ -7917,7 +8106,7 @@ SOF _=lNO_ NO
NS80r_Fdj4:9O=NlN_80r_sdj4:9N;
H#R3$kM_#_Cs#N_bs#NlR_"oI0H8E;R"
RNHoH_I8R0Ed
.;s@R@d6n:4c(::(64:R.dI FsRcoM4_.cOCFsRDs0RkoMlM_H0VCsN_OCLODF s
.;s@R@d6(:dcj::j6d:R.dI FsRcoM4_.cOCFsRDs0RkoMlM_H0VCsN_OCLODF s
S#M0__HN_=0s#_NM__SH
b_.Db_DDD FOCk8=Mo4_M_klHCM0sOVNCD_LF
O SL8CkFo_rj(:9M=k4M_okHl_Ms0CVCNO_FLDO4 _rj(:9b
......@@ -7965,7 +8154,7 @@ ICSN8l_OO$_8F=lON_$SO
8_lN#D0ND=_H#sbNC;_F
RNH3M#$_Ck#s__#bNNsl"#Ro#_OsL_I_N#DP_C#M"LR;H
NRBo_1W)_Ap_1q1e _RhA4s;
Rd@@n(:6d::c6:(d4IgRFRs O_D s_#0lNNMossR0ODRD_ #s##0_lloC
Rd@@(U:6n::c6:Un4IgRFRs O_D s_#0lNNMossR0ODRD_ #s##0_lloC
M0SNNOlC_sV OD_NH=O_NlsOCVDH _
DSbD8_D_bH=DDD_8
_HSDbD_VsCl_FMHD=bDC_sVMlF_SH
......@@ -7986,59 +8175,54 @@ S8OO_DF _= OD;H
NR$3#M#_kC#s__sbNNRl#"DPNk_C#V_Fs#kHlDHN0FMMRLV_F_osCR
";NMHRLV_F_osCR;nU
RNHPkNDCV#_F#s_HDlkNF0HMNRVD;#C
@sR@:dn6:ggcg:6gU:4RsIF FROk8M0F_IMOMFk0RCssR0D0_8OD_C8OMFk0
CsS OD= OD
CSs#=C0oCCMs_NDsCC#0#
S00Ns=N#0sV0_s_FlVNbo_SF
#s0N0N_PDrkCdj4:9N=VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCs,0kVC,NCD#,k0sCs,0k0C,s,kC0Csk,k0sCN,VD,#C0Csk,DVN#0C,s,kC0Csk,k0sCs,0kVC,NCD#,DVN#VC,NCD#,DVN#0C,s,kCV#NDCN,VD,#CV#NDCN,VD,#CV#NDCO
SF0kM_M8FC8=0OC_D8F_Ok_M08CFM
kSOsMsC0N_PDrkCdj4:9M=k48_0OC_D8F_OkCM0s4rd:;j9
@sR@:dnn:.Uc.:nUg:4RsIF sRVCOC_F0kMCssR0#DRb_COD_C8OMFk0
@sR@:d(n:4.c4:n.g:4RsIF sRVCOC_F0kMCssR0#DRb_COD_C8OMFk0
CsS OD=C#bOD_O C
SMDNLCs=0kSC
sCC#0M=oksl_C0#C
0S#N_s0PkNDC4rd:=j9V#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCs,0kVC,NCD#,DVN#0C,s,kC0Csk,DVN#VC,NCD#,DVN#0C,s,kCV#NDCN,VD,#C0Csk,DVN#0C,s,kC0Csk,DVN#0C,s,kCV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD
#CSkOFM80_F=MC#ObC_8DC_kOFM80_F
MCSsOks0CM_DPNkdCr49:j=4kM_C#bOC_D8F_OkCM0s4rd:;j9
@bR@:dnnUc:::nc4L6Rk#VRb_COD_C8oCsCMR_F#ObC_8DC_CosCFM_RDbD__D8Hb;
RH[FMNR80LN_kH#_F(r.:Rj98NN0_#Lk_rHF.j(:9NR80LN_kH#_Fr_4.j(:9b;
Rd@@n4:4.::U4:4.4LURk#VRb_CON6kG_#FRb_CON6kG_#FRb_CONjkG_
H;b@R@d4n:4Ud::d44:R4ULRkV#ObC_GNkcR_F#ObC_GNkcR_F#ObC_GNk4;_H
@bR@:dnn:.ddn4:.cd:(MRHPIR0FC_#O8FM#0\38DO_C08_s6Ho_0cRI#F_CMOF83#\0_8OD_C80osH6
_cRRRR0_8OD_C80osH6b;
Rd@@nc:nc6:d:cnc:R6jHRMP#ObC_8DC\b3#CDO_Cs8_C48_RC#bOC_D8#\3b_COD_C8s_C84bR#CDO_Cs8_C
8;b@R@dnn:n64:jn:n4c:nRPHMRdkM_koMlC_s#RC0k_MdolMk_#sCC#0Rb_CON4kG_
H;b@R@dnn:nd4:.n:n4c:cRPHMR6kM_koMlC_s#RC0k_M6olMk_#sCCs0R#M0__HN_;R
b@:@j4::44R:.0CskRk0sCsR0k
C;b@R@j::44::4.NRVDR#CV#NDCNRVD;#C
@bR@4j::44::8.ROOR8R;8O
@bR@:dndUn:::dn48nRObR#N_sCFbR#N_sCFb;
Rd@@n4:4c::U4:4c48URV#VRb_CON.kG_#FRb_CON.kG_#FRb_CONjkG_OHRD
;N3HRs_0DFosHMCNlRb"#CNO_k_G.F
";b@R@d4n:4U6::644:R4U8RVV#ObC_GNkdR_F#ObC_GNkdR_F#ObC_GNkjR_H#ObC_ OD;H
NR03sDs_FHNoMl"CR#ObC_GNkd"_F;R
b@n@d:gd6::c6d:6gcV(RNCD#RC#bOC_D8C_s8R_.#ObC_8DC_8sC_
.;b@R@j::44::4.kRLVkRl0HC_M0bk#R_FlCk0_bHMk_0#FsR0k
C;b@R@j::44::4.kRLV0R#N_s08_H#F0R#N_s08_H#FNRVD;#C
@bR@4j::44::L.Rk#VR0_Fb8_H#F0R#F8b_HF#_RDVN#
C;b@R@j::44::4.kRLV8R0OC_D8s_0H_o4F8R0OC_D8s_0H_o4FNRVD;#C
@bR@4j::44::L.Rk0VR8DO_C08_s.Ho_0FR8DO_C08_s.Ho_VFRNCD#;R
b@:@j4::44R:.LRkV0_8OD_C80osHdR_F0_8OD_C80osHdR_FV#NDCb;
Rj@@:44::.4:RVLkRO08_8DC_H0soFc_RO08_8DC_H0soFc_RDVN#
C;b@R@j::44::4.kRLVCR0sCl_M__4FCR0sCl_M__4FsR0k
C;b@R@j::44::4.kRLVCR0sCl_M__.FCR0sCl_M__.FsR0k
C;b@R@j::44::4.kRLVCR0sCl_M__dFCR0sCl_M__dFsR0k
C;b@R@j::44::4.kRLVCR0sCl_M__cFCR0sCl_M__cFsR0k
C;b@R@j::44::4.kRLVCR0sCl_M__6FCR0sCl_M__6FsR0k
C;b@R@ddn:n(d::ddn:R4g8CVVRO08_8DC_H0so06R8DO_C08_s6HoRF0I_O#CF#M8\830OC_D8s_0H_o6cR
RRDRO 0R#N_s0VlsF_oVbN;_F
RNH3Ds0_HFsolMNC0R"8DO_C08_s6Ho"N;
H#R3$HM_MPH0N"DRj
";b@R@ddn:6(U::Ud6:R.j#V8V#0CR8DO_C#8_0kN0#8R0OC_D80_#N#0kRDVN#OCRD# R00Ns_FVslb_VoFN_
RRRRO08_8DC_kOFM80_F;MC
RNH3Ds0_HFsolMNC0R"8DO_C#8_0kN0#
";b@R@dnn:nd4:.n:n4c:nRPFsRkoMlC_s#RC0olMk_#sCCk0RMod_M_klsCC#0MRk6M_oksl_C0#C;R
b@n@d:(d6:d(:64(:U8R#VCVsRC#bOC_D8C_s8bR#CDO_Cs8_C#8Rb_COD\C83C#bOC_D8C_s8R_4#ObC_ OD
RRRRkoMlC_s#RC0#ObC_8DC_kOFM80_F;MC
RNH3Ds0_HFsolMNC#R"b_COD_C8s"C8;;
C
@sR@:d(n:.dc.:ndU:4RsIF FROk8M0F_IMOMFk0RCssR0D0_8OD_C8OMFk0
CsS OD= OD
CSs#=C0oCCMs_NDsCC#0#
S00Ns=CFM__Exb#
S00Ns_DPNkdCr49:j=DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,k0sCN,VD,#C0Csk,k0sCs,0k0C,s,kC0Csk,DVN#0C,s,kCV#NDCs,0k0C,s,kC0Csk,k0sCN,VD,#CV#NDCN,VD,#CV#NDCs,0kVC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#
FSOk_M08CFM=O08_8DC_kOFM80_F
MCSsOks0CM_DPNkdCr49:j=4kM_O08_8DC_kOFMs0Cr:d4j
9;b@R@dn(:c::Un4c:6kRLVbR#CDO_Co8_sMCC_#FRb_COD_C8oCsCMR_Fb_DDDH8_;R
b[MFHR08NNk_L#F_Hr:.(j89RN_0NL_k#H.Fr(9:jR08NNk_L#F_H_.4r(9:j;R
b@(@d:.44:4U:44.:UkRLVbR#CNO_k_G6FbR#CNO_k_G6FbR#CNO_k_GjHb;
Rd@@(4:4d::U4:4d4LURk#VRb_CONckG_#FRb_CONckG_#FRb_CON4kG_
H;b@R@dn(:ddg:6d:ngj:6RPHMRC#bOC_D8#\3b_COD_C8s_C8.bR#CDO_C38\#ObC_8DC_8sC_#.Rb_COD_C8s;C8
@bR@:d(n:Ug6nj:Ung:cMRHPMRkdM_oksl_C0#CRdkM_koMlC_s#RC0#ObC_GNk4;_H
@bR@:d(n:Ugdn.:Ucg:cMRHPMRk6M_oksl_C0#CR6kM_koMlC_s#RC0s_#0M__NHb;
Rj@@:44::.4:Rk0sCsR0k0CRs;kC
@bR@4j::44::V.RNCD#RDVN#VCRNCD#;R
b@:@j4::44R:.88OROOR8;R
b@(@d::dnUn:d:R4n8#ORbCNs_#FRbCNs_
F;b@R@d4(:4Uc::c44:R4U8RVV#ObC_GNk.R_F#ObC_GNk.R_F#ObC_GNkjR_HO;D
RNH3Ds0_HFsolMNC#R"b_CON.kG_;F"
@bR@:d(4:46U4:46U:4RV8VRC#bOk_NGFd_RC#bOk_NGFd_RC#bOk_NGHj_RC#bOD_O N;
HsR30FD_sMHoNRlC"C#bOk_NGFd_"b;
Rd@@(n:dn6:c:ndn:Rc(V#NDC8R0OC_D80_#N#0k_04R8DO_C#8_0kN0#;_4
@bR@4j::44::L.RklVRk_0CHkMb0F#_R0lkCM_Hb#k0_0FRs;kC
@bR@4j::44::L.Rk0VR8DO_C08_s4Ho_0FR8DO_C08_s4Ho_VFRNCD#;R
b@:@j4::44R:.LRkV0_8OD_C80osH.R_F0_8OD_C80osH.R_FV#NDCb;
Rj@@:44::.4:RVLkRO08_8DC_H0soFd_RO08_8DC_H0soFd_RDVN#
C;b@R@j::44::4.kRLV8R0OC_D8s_0H_ocF8R0OC_D8s_0H_ocFNRVD;#C
@bR@4j::44::L.Rk0VR8DO_C08_s6Ho_0FR8DO_C08_s6Ho_VFRNCD#;R
b@:@j4::44R:.LRkV0lCs__CM4R_F0lCs__CM4R_F0Csk;R
b@:@j4::44R:.LRkV0lCs__CM.R_F0lCs__CM.R_F0Csk;R
b@:@j4::44R:.LRkV0lCs__CMdR_F0lCs__CMdR_F0Csk;R
b@:@j4::44R:.LRkV0lCs__CMcR_F0lCs__CMcR_F0Csk;R
b@:@j4::44R:.LRkV0lCs__CM6R_F0lCs__CM6R_F0Csk;R
b@(@d:6dn:d(:n.6:j8R#VCV#RO08_8DC_N#00Rk#0_8OD_C8#00NkV#RNCD#R ODRCFM__Exb8R0OC_D8F_Ok_M08CFM;H
NR03sDs_FHNoMl"CR0_8OD_C8#00Nk;#"
@bR@:d(n:Ugdn.:Ung:csRFPMRoksl_C0#CRkoMlC_s#RC0k_MdolMk_#sCCk0RMo6_M_klsCC#0b;
Rd@@(n:dc::(d:nc4#UR8sVVCbR#CDO_Cs8_C#8Rb_COD_C8sRC8#ObC_8DC\b3#CDO_Cs8_C.8_RC#bOD_O R
RRMRoksl_C0#CRC#bOC_D8F_Ok_M08CFM;H
NR03sDs_FHNoMl"CR#ObC_8DC_8sC"C;
;
hdl/spec/syn/test_tdc_acam/syn_tdc.srm
View file @ 07fa5b23
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/test_tdc_acam/syn_tdc.srr
View file @ 07fa5b23
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/test_tdc_acam/syn_tdc.srs
View file @ 07fa5b23
......@@ -6,10 +6,10 @@
#
# Created by Synplify VHDL Compiler version comp500rc, Build 027R from Synplicity, Inc.
# Copyright 1994-2010 Synopsys, Inc. , All rights reserved.
# Synthesis Netlist written on Thu Jul 21 19:57:43 2011
# Synthesis Netlist written on Tue Aug 2 16:06:35 2011
#
#
#OPTIONS:"|-top|top_tdc|-dspmac|-pqdpadd|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-dfltencoding|onehot|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|off|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#OPTIONS:"|-top|top_tdc|-dspmac|-pqdpadd|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-dfltencoding|onehot|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|off|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"/afs/cern.ch/project/parc/elec/synplify/D-2010.03/linux/c_vhdl":1266628077
#CUR:"/afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/vhd/location.map":1266734607
#CUR:"/afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/vhd/std.vhd":1266627777
......@@ -30,12 +30,12 @@
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd":1311178071
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/dma_controller_wb_slave.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/tdc_core_pkg.vhd":1311079740
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/tdc_core_pkg.vhd":1311958660
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/free_counter.vhd":1305902268
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/incr_counter.vhd":1305902074
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/countdown_counter.vhd":1306314922
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd":1306489421
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_databus_interface.vhd":1311239445
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_databus_interface.vhd":1312293738
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_ser_s6.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_des_s6.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_decode32.vhd":1310389590
......@@ -47,9 +47,10 @@
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_s6.vhd":1311177581
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":1311001350
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd":1306400619
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_nb_offset_gen.vhd":1307641333
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd":1307642203
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":1311251491
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_retrigger_control.vhd":1312210529
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_engine.vhd":1312293985
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd":1312216371
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":1312205957
f "/afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/vhd/std.vhd"; # file 0
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"; # file 1
......@@ -118,11 +119,13 @@ f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.v
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd"; # file 33
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_nb_offset_gen.vhd"; # file 34
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_retrigger_control.vhd"; # file 34
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd"; # file 35
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_engine.vhd"; # file 35
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd"; # file 36
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd"; # file 36
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd"; # file 37
af .is_vhdl 1;
@E
@
......@@ -317,6 +320,210 @@ j9RRRR0Csk,DVN#VC,NCD#;-
y---------------------------------
@
ftell;
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NR#3HPDE8R
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";N3PRDoNMuNNsllhNC"#RI0H8E
";NIPRHE80R;d.
@HR@:4g.U4:::.44OjRDO RD
;N3HRs_0DFosHMCNlRD"O
";
@HR@:4g.U.:::..4CnRMP8_NCDkr:d4jC9RMP8_NCDkr:d4j
9;N3HRs_0DFosHMCNlRM"C8N_PD"kC;
@HR@:4g.Ud:::.d4H4RMROsHsMO;H
NR03sDs_FHNoMl"CRHsMO"
;
@HR@:4g.Uc:::.c4s.RC0#CR#sCC
0;N3HRs_0DFosHMCNlRC"s#"C0;
@FR@:4g.Un:::.n4O(RF0kM_M8FCFROk_M08CFM;H
NR03sDs_FHNoMl"CROMFk0F_8M;C"
@FR@:4g.U(:::.(.OjRkCssMP0_NCDkr:d4jP9RNCDkr:d4j
9;N3HRs_0DFosHMCNlRk"OsMsC0N_PD"kC;R
b@:@j4::44R:.0CskRk0sCsR0k
C;b@R@j::44::4.NRVDR#CV#NDCNRVD;#C
@bR@:4gc46:j6:c:R.6COJRF0kM\M3k.N_PDRkCOMFk0k\3MP._NCDkRDPNkdCr49:jR8CM_DPNkdCr49:j;R
b@g@4::64.6(:4(:dR8N8R4kM_DPNkdCr.9:4R4kM_DPNkdCr.9:4RDPNkdCr49:jROHMsb;
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---------------------------------@-
ftell;
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;
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";
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;
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HsMO=8N8_VFV#
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";y--------------------------------
--@
ftell;
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";
@FR@:dndUU:::dU4#(R0_Fb8_H#FNRVD;#C
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";
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;
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";
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-y---------------------------------
@
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......@@ -398,114 +605,119 @@ F;N3HRs_0DFosHMCNlRO"N "_F;
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R.@@.j:.(d:c:(.j:RcUHRMPFbk0ks0_C#oH0#Cs\#3O_FM__FdRkk0b0C_so0H#C\s#3_O#M__Fd#RO;R
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@bR@:dn6:4gd66:4dg:6MRN8sPR#O0_Dj __l#JkRGNs_#0O_D jJ_#lNkGRN#00UCgR4kM_N#00dC_;R
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b@6@4:Uc4::.cc:4U6HnRMkPRMs4_#O0_Dj __l#JkRGNk_M4s_#0O_D jJ_#lNkGR0s#_ OD_#j_JGlkNb;
R4@@66:46::c4:666VR8VRsCO_NDORD O_NDORD #00NC__4#kJlGsNRGk_LVbo_DGD_4FRM0G_s_VLkb_DDD8O
RRRR4kM_DON_ OD_#j_JGlkNN;
......@@ -7193,55 +7405,6 @@ Rg@@:(n.c::6nc.(:86RORRmmy;
ftell;
@E@MR@:4g4(n:::4n4IURFRs HsMO_kOFMs0CRDs0;P
NR#3HPDE8R
4;N3PRHP#_ER8D4N;
PFR3shHoNRlC"OHMsF_OkCM0s
";N3PRDoNMuNNsllhNC"#RI0H8E
";NIPRHE80R;d.
@HR@:4g.U4:::.44OjRDO RD
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";
@HR@:4g.U.:::..4CnRMP8_NCDkr:d4jC9RMP8_NCDkr:d4j
9;N3HRs_0DFosHMCNlRM"C8N_PD"kC;
@HR@:4g.Ud:::.d4H4RMROsHsMO;H
NR03sDs_FHNoMl"CRHsMO"
;
@HR@:4g.Uc:::.c4s.RC0#CR#sCC
0;N3HRs_0DFosHMCNlRC"s#"C0;
@FR@:4g.Un:::.n4O(RF0kM_M8FCFROk_M08CFM;H
NR03sDs_FHNoMl"CROMFk0F_8M;C"
@FR@:4g.U(:::.(.OjRkCssMP0_NCDkr:d4jP9RNCDkr:d4j
9;N3HRs_0DFosHMCNlRk"OsMsC0N_PD"kC;R
b@:@j4::44R:.0CskRk0sCsR0k
C;b@R@j::44::4.NRVDR#CV#NDCNRVD;#C
@bR@:4gc46:j6:c:R.6COJRF0kM\M3k.N_PDRkCOMFk0k\3MP._NCDkRDPNkdCr49:jR8CM_DPNkdCr49:j;R
b@g@4::64.6(:4(:dR8N8R4kM_DPNkdCr.9:4R4kM_DPNkdCr.9:4RDPNkdCr49:jROHMsb;
R4@@g.:c:cc:.R:6lRkGOMFk0P\3NCDk_d6r49:jRkOFM30\PkNDCr_6dj4:9MRk4N_PDrkCd4.:9R
RRMRC8N_PDrkCdj4:9FROk\M03.kM_DPNk
C;b@R@4ng:4(:.::n46N4R8C8RMl8_H#Mk_CFMr:d4jC9RMl8_H#Mk_CFMr:d4jC9RMP8_NCDkr:d4jR9
R0RRs,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0k
C;b@R@4dg:n::(d4n:48R#VRVsPkNDC4rd:Rj9PkNDC4rd:Rj9OMFk0P\3NCDk_d6r49:jR ODR#sCC
0;N3HRs_0DFosHMCNlRN"PD"kC;H
NR$3#MM_HHN0PDjR"jjjjjjjjjjjjjjjjjjjjjjjjjjjjj"jj;R
b@g@4::cg4c4:g4:dRRCJOMFk0k\3MHn_MROsOMFk0k\3MHn_MROsC_M8lkHM#M_FC4rd:Rj9PkNDC4rd:;j9
@bR@:4gc4g:4g:c:Rd4NPM8RkOFM80_F_MCjJ_#lNkGRkOFM80_F_MCjJ_#lNkGROHMsFROk\M03nkM_OHMsb;
R4@@g.:c:cc:.R:6FRsPk_M4PkNDCR_4k_M4PkNDCR_4OMFk0k\3MP._NCDkRkOFM80_F_MCjJ_#lNkG;R
b@g@4::.nUn:.:R4(#V8VsR#COMFk0F_8MOCRF0kM_M8FCNRVDR#CORD sCC#0MRk4N_PD_kC4MRHO
s;N3HRs_0DFosHMCNlRF"Ok_M08CFM"y;
---------------------------------@-
ftell;
@E@MR@:d.d(.:::d..IjRFRs O_D s_#0lNNMossR0
D;N3PRHE#P84DR;P
......@@ -7595,7 +7758,7 @@ H;N3HRs_0DFosHMCNlRH"L0M_H8"CG;-
y---------------------------------
@
ftell;
@E@MR@:dn.(g:::.g4IdRFRs 0_Fb0R8Os;0D
@E@MR@:d(.(g:::.g4IdRFRs 0_Fb0R8Os;0D
RNP3PH#ER8D4N;
PHR3#E_P84DR;P
NR$3#Ml_VN"bRI FsR/\"N/V#OMCs3/OEC/MoC/8NO_8#ks#C#V/oCNsMMb8/sCF[O/0#0/8O#/sOHOb_F#sC/koMlF_OsoC/M.c4cF_OsbC_ #o_nE3P8
......@@ -7621,294 +7784,320 @@ FRs \N"/VO#/C3sMOCE/MCo/8ON/8k#_##Cs/CoVsMMN8s/bFO[C00#/8#O/ssO/0HD/M_OsOMFk03Cs
Is\ R"V/N#C/OsOM3EM/Co8/CN8/O##_kC/s#osVCM8NM/Fbs[0CO#8/0Os/#O0/sDF/Ok8M0F_IMOMFk03CsP\E8"F
Is\ R"V/N#C/OsOM3EM/Co8/CN8/O##_kC/s#osVCM8NM/Fbs[0CO#8/0Os/#O0/sDD/O #_s0N_lMsNo38PE\I"
FRs \N"/VO#/C3sMOCE/MCo/8ON/8k#_##Cs/CoVsMMN8s/bFO[C00#/8#O/ssO/0FD/MEC_xC_oME3P8
\"I FsR/\"N/V#OMCs3/OEC/MoC/8NO_8#ks#C#V/oCNsMMb8/sCF[O/0#0/8O#/sOs/0D#s0N0L_M_VFV#_C0o3CMP\E8"F
\"I FsR/\"N/V#OMCs3/OEC/MoC/8NO_8#ks#C#V/oCNsMMb8/sCF[O/0#0/8O#/sOs/0D#s0N0C_s0osHo_CsO0FMs3FDP\E8"F
Is\ R"V/N#C/OsOM3EM/Co8/CN8/O##_kC/s#osVCM8NM/Fbs[0CO#8/0Os/#O0/sDN/80VN_FNsl0M0HoE3P8
\"I FsR/\"N/V#OMCs3/OEC/MoC/8NO_8#ks#C#V/oCNsMMb8/sCF[O/0#0/8O#/sOs/0DNlON_l0HCMOF0DsF_0HMCNsVOPC3E"8\
sIF "R\/#NV/sOCME3O/oCM/NC8/#O8_Ck#so#/VMCsN/M8b[sFC#O0/O08/O#s/Ds0/NNOlN_80kNL#M_H0VCsN3OCP\E8"F
Is\ R"V/N#C/OsOM3EM/Co8/CN8/O##_kC/s#osVCM8NM/Fbs[0CO#8/0Os/#O0/sDC/0#00_8NO_O/Nl0_Fb00C#_NNOlE3P8
\""
;
@HR@:dndUn:::dn4snR#M0__HN_R0s#_NM__
\"I FsR/\"N/V#OMCs3/OEC/MoC/8NO_8#ks#C#V/oCNsMMb8/sCF[O/0#0/8O#/sOs/0D8NN0_oCMH3MCP\E8"F
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FRs \N"/VO#/C3sMOCE/MCo/8ON/8k#_##Cs/CoVsMMN8s/bFO[C00#/8#O/ssO/0ND/O_Nl8NN0L_k#HCM0sOVNCE3P8
\"I FsR/\"N/V#OMCs3/OEC/MoC/8NO_8#ks#C#V/oCNsMMb8/sCF[O/0#0/8O#/sOs/0D0_Fb038OP\E8";
"
@HR@:d(dUn:::dn4snR#M0__HN_R0s#_NM__
H;N3HRs_0DFosHMCNlR#"s0__MN"_H;
@HR@:dndUU:::dU4bUR.OD_Db __bHR.OD_Db __
@HR@:d(dUU:::dU4bUR.OD_Db __bHR.OD_Db __
H;N3HRs_0DFosHMCNlR."bDD_O __bH
";
@HR@:dndUg:::dg4bUR.OD_DM __bHR.OD_DM __
@HR@:d(dUg:::dg4bUR.OD_DM __bHR.OD_DM __
H;N3HRs_0DFosHMCNlR."bDD_O __MH
";
@HR@:dncUj:::cj4b(R.8D_N_0NH6r4:Rj9b_.D8NN0_4Hr69:j;H
@HR@:d(cUj:::cj4b(R.8D_N_0NH6r4:Rj9b_.D8NN0_4Hr69:j;H
NR03sDs_FHNoMl"CRb_.D8NN0_;H"
@HR@:dncU4:::c44bgR.8D_VlsNCR_Hb_.D8NVslHC_;H
@HR@:d(cU4:::c44bgR.8D_VlsNCR_Hb_.D8NVslHC_;H
NR03sDs_FHNoMl"CRb_.D8NVslHC_"
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@HR@:dncU.:::c.4bUR.PD_N8DH_bHR.PD_N8DH_
@HR@:d(cU.:::c.4bUR.PD_N8DH_bHR.PD_N8DH_
H;N3HRs_0DFosHMCNlR."bDN_PD_H8H
";
@FR@:dncUd:::cd4bnR.sD_8F$_RDb._$s8_
@FR@:d(cUd:::cd4bnR.sD_8F$_RDb._$s8_
F;N3HRs_0DFosHMCNlR."bD8_s$"_F;
@HR@:dncUc:::cc4b(R__Iss_CJH:r4jb9R__Iss_CJH:r4j
@HR@:d(cUc:::cc4b(R__Iss_CJH:r4jb9R__Iss_CJH:r4j
9;N3HRs_0DFosHMCNlR_"bIss_CHJ_"
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@FR@:dncU6:::c64b(R__Iss_8$F:r4jb9R__Iss_8$F:r4j
@FR@:d(cU6:::c64b(R__Iss_8$F:r4jb9R__Iss_8$F:r4j
9;N3HRs_0DFosHMCNlR_"bIss_8F$_"
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@FR@:dncUn:::cn4s(RGs_Cs_FsFGRs_sCsFFs_;H
@FR@:d(cUn:::cn4s(RGs_Cs_FsFGRs_sCsFFs_;H
NR03sDs_FHNoMl"CRsCG_sssF_;F"
@HR@:dncU(:::c(4P6RO8_s$r_H49:jR_POs_8$H:r4j
@HR@:d(cU(:::c(4P6RO8_s$r_H49:jR_POs_8$H:r4j
9;N3HRs_0DFosHMCNlRO"P_$s8_;H"
@FR@:dncUg:::cg4DUR.Ob_Db __DFR.Ob_Db __
@FR@:d(cUg:::cg4DUR.Ob_Db __DFR.Ob_Db __
F;N3HRs_0DFosHMCNlR."DbD_O __bF
";
@FR@:dn6Uj:::6j4DUR.Ob_DM __DFR.Ob_DM __
@FR@:d(6Uj:::6j4DUR.Ob_DM __DFR.Ob_DM __
F;N3HRs_0DFosHMCNlR."DbD_O __MF
";
@FR@:dn6U4:::644D(R.8b_N_0NF6r4:Rj9D_.b8NN0_4Fr69:j;H
@FR@:d(6U4:::644D(R.8b_N_0NF6r4:Rj9D_.b8NN0_4Fr69:j;H
NR03sDs_FHNoMl"CRD_.b8NN0_;F"
@FR@:dn6U.:::6.4DgR.8b_VlsNCR_FD_.b8NVslFC_;H
@FR@:d(6U.:::6.4DgR.8b_VlsNCR_FD_.b8NVslFC_;H
NR03sDs_FHNoMl"CRD_.b8NVslFC_"
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@FR@:dn6Ud:::6d4DUR.Pb_N8DH_DFR.Pb_N8DH_
@FR@:d(6Ud:::6d4DUR.Pb_N8DH_DFR.Pb_N8DH_
F;N3HRs_0DFosHMCNlR."DbN_PD_H8F
";
@FR@:dn6Uc:::6c4DnR.Cb_8FL_RbD._LC8_
@FR@:d(6Uc:::6c4DnR.Cb_8FL_RbD._LC8_
F;N3HRs_0DFosHMCNlR."Db8_CL"_F;
@HR@:dn6U6:::664DnR.sb_8H$_RbD._$s8_
@HR@:d(6U6:::664DnR.sb_8H$_RbD._$s8_
H;N3HRs_0DFosHMCNlR."Db8_s$"_H;
@HR@:dn6Un:::6n4D(R__Iss_8$H:r4jD9R__Iss_8$H:r4j
@HR@:d(6Un:::6n4D(R__Iss_8$H:r4jD9R__Iss_8$H:r4j
9;N3HRs_0DFosHMCNlR_"DIss_8H$_"
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@HR@:dn6U(:::6(4bgR__s888_s$r_H49:jRsb_8__8s_8$H:r4j
@HR@:d(6U(:::6(4bgR__s888_s$r_H49:jRsb_8__8s_8$H:r4j
9;N3HRs_0DFosHMCNlR_"bs88__$s8_;H"
@HR@:dn6UU:::6U40(RGs_Cs_FsHGR0_sCsFHs_;H
@HR@:d(6UU:::6U40(RGs_Cs_FsHGR0_sCsFHs_;H
NR03sDs_FHNoMl"CR0CG_sssF_;H"
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@FR@:d(6Ug:::6g4HcRsbJ__HFRsbJ__
F;N3HRs_0DFosHMCNlRs"HJ__bF
";
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@FR@:d(nUj:::nj4#cRbCNs_#FRbCNs_
F;N3HRs_0DFosHMCNlRb"#N_sCF
";N3HR#_$MM#FN#MHol0CMR
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@HR@:d(nUd:::nd.NjRO_NlsOCVDH _RNNOlC_sV OD_
H;N3HRs_0DFosHMCNlRO"NNsl_CDVO "_H;
@HR@:dnnUc:::nc4b6RDDD_8R_Hb_DDDH8_;H
@HR@:d(nUc:::nc4b6RDDD_8R_Hb_DDDH8_;H
NR03sDs_FHNoMl"CRb_DDDH8_"
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@HR@:d(nU6:::n64bgRDsD_CFVlMR_Hb_DDslCVFHM_;H
NR03sDs_FHNoMl"CRb_DDslCVFHM_"
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@HR@:d(nUn:::nn4bnRD#D_8HF_RDbD_F#8_
H;N3HRs_0DFosHMCNlRD"bD8_#F"_H;
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@HR@:d(nU(:::n(4bgRD#D_0kN0#R_Hb_DD#00NkH#_;H
NR03sDs_FHNoMl"CRb_DD#00NkH#_"
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@HR@:d(nUU:::nU40UR8OO_Db __0HR8OO_Db __
H;N3HRs_0DFosHMCNlR8"0OD_O __bH
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@HR@:d(nUg:::ng40UR8OO_DM __0HR8OO_DM __
H;N3HRs_0DFosHMCNlR8"0OD_O __MH
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@FR@:d((U4:::(44b6RDOD_#R_Fb_DDOF#_;H
NR03sDs_FHNoMl"CRb_DDOF#_"
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F;N3HRs_0DFosHMCNlRD"bD8_#H"_F;
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@HR@:d((UU:::(U4H(RMV0_D_NoHMRH0D_VNHo_;H
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@FR@:d(UUj:::Uj4#UR00Ns_#8H_#FR00Ns_#8H_
F;N3HRs_0DFosHMCNlR0"#N_s08_H#F
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NR03sDs_FHNoMl"CR#b0F_#8H_;F"
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9;N3HRs_0DFosHMCNlRN"80LN_kH#_F
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@HR@:d(UUn:::Un4C.RVH4_R4CV_
H;N3HRs_0DFosHMCNlRV"C4"_H;
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@HR@:d(UU(:::U(4C.RVH._R.CV_
H;N3HRs_0DFosHMCNlRV"C."_H;
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@HR@:d(UUU:::UU4D.RVH4_R4DV_
H;N3HRs_0DFosHMCNlRV"D4"_H;
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@HR@:d(UUg:::Ug4D.RVH._R.DV_
H;N3HRs_0DFosHMCNlRV"D."_H;
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NR03sDs_FHNoMl"CRNs88C_##F
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NR03sDs_FHNoMl"CROM#__;F"
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@FR@:d(gUd:::gd4FdRC__MFCRF_FM_;H
NR03sDs_FHNoMl"CRFMC__;F"
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@FR@:d(gUc:::gc4sdR8__MF8Rs_FM_;H
NR03sDs_FHNoMl"CRsM8__;F"
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NR03sDs_FHNoMl"CRIMs__;F"
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F;N3HRs_0DFosHMCNlRk"l0HC_M0bk#"_F;
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NR03sDs_FHNoMl"CR0_8OD_C80osH4"_F;
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NR03sDs_FHNoMl"CR0_8OD_C80osH."_F;
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NR03sDs_FHNoMl"CR0_8OD_C80osHd"_F;
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NR03sDs_FHNoMl"CR0_8OD_C80osHc"_F;
@FR@:dn4:jcUj:4c.:.RO08_8DC_H0soF6_RO08_8DC_H0so
6;N3HRs_0DFosHMCNlR8"0OC_D8s_0H_o6F
";
@FR@:dn4:j6Uj:46U:4Rs0ClM_C_F4_Rs0ClM_C_F4_;H
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NR03sDs_FHNoMl"CR0_8OD_C80osH6"_F;
@FR@:d(4:j6Uj:46U:4Rs0ClM_C_F4_Rs0ClM_C_F4_;H
NR03sDs_FHNoMl"CR0lCs__CM4"_F;
@FR@:dn4:jnUj:4nU:4Rs0ClM_C_F._Rs0ClM_C_F._;H
@FR@:d(4:jnUj:4nU:4Rs0ClM_C_F._Rs0ClM_C_F._;H
NR03sDs_FHNoMl"CR0lCs__CM."_F;
@FR@:dn4:j(Uj:4(U:4Rs0ClM_C_Fd_Rs0ClM_C_Fd_;H
@FR@:d(4:j(Uj:4(U:4Rs0ClM_C_Fd_Rs0ClM_C_Fd_;H
NR03sDs_FHNoMl"CR0lCs__CMd"_F;
@FR@:dn4:jUUj:4UU:4Rs0ClM_C_Fc_Rs0ClM_C_Fc_;H
@FR@:d(4:jUUj:4UU:4Rs0ClM_C_Fc_Rs0ClM_C_Fc_;H
NR03sDs_FHNoMl"CR0lCs__CMc"_F;
@FR@:dn4:jgUj:4gU:4Rs0ClM_C_F6_Rs0ClM_C_F6_;H
@FR@:d(4:jgUj:4gU:4Rs0ClM_C_F6_Rs0ClM_C_F6_;H
NR03sDs_FHNoMl"CR0lCs__CM6"_F;
@HR@:dn4:4.U4:4.U:4RC#bOk_NGHj_RC#bOk_NGHj_;H
@HR@:d(4:4.U4:4.U:4RC#bOk_NGHj_RC#bOk_NGHj_;H
NR03sDs_FHNoMl"CR#ObC_GNkj"_H;
@HR@:dn4:4dU4:4dU:4RC#bOk_NGH4_RC#bOk_NGH4_;H
@HR@:d(4:4dU4:4dU:4RC#bOk_NGH4_RC#bOk_NGH4_;H
NR03sDs_FHNoMl"CR#ObC_GNk4"_H;
@FR@:dn4:4cU4:4cU:4RC#bOk_NGF._RC#bOk_NGF._;H
@FR@:d(4:4cU4:4cU:4RC#bOk_NGF._RC#bOk_NGF._;H
NR03sDs_FHNoMl"CR#ObC_GNk."_F;
@FR@:dn4:46U4:46U:4RC#bOk_NGFd_RC#bOk_NGFd_;H
@FR@:d(4:46U4:46U:4RC#bOk_NGFd_RC#bOk_NGFd_;H
NR03sDs_FHNoMl"CR#ObC_GNkd"_F;
@FR@:dn4:4nU4:4nU:4RC#bOk_NGFc_RC#bOk_NGFc_;H
@FR@:d(4:4nU4:4nU:4RC#bOk_NGFc_RC#bOk_NGFc_;H
NR03sDs_FHNoMl"CR#ObC_GNkc"_F;
@FR@:dn4:4(U4:4(U:4RC#bOk_NGF6_RC#bOk_NGF6_;H
@FR@:d(4:4(U4:4(U:4RC#bOk_NGF6_RC#bOk_NGF6_;H
NR03sDs_FHNoMl"CR#ObC_GNk6"_F;
@FR@:dn4:4UU4:4Ud:.RC#bOC_D8s_oC_CMFbR#CDO_Co8_sMCC_
@FR@:d(4:4UU4:4Ud:.RC#bOC_D8s_oC_CMFbR#CDO_Co8_sMCC_
F;N3HRs_0DFosHMCNlRb"#CDO_Co8_sMCC_;F"
@FR@:dn4:4gU4:4g4:.RC#bOC_D8C_s8R_F#ObC_8DC_8sC;H
@FR@:d(4:4gU4:4g4:.RC#bOC_D8C_s8R_F#ObC_8DC_8sC;H
NR03sDs_FHNoMl"CR#ObC_8DC_8sC_;F"
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Rd@@n4:c(::cc:4(4IgRFRs F_MCEox_CsMR0FDRM#C_CMOF8D_LF
Rd@@(.:c(::cc:.(4IgRFRs F_MCEox_CsMR0FDRM#C_CMOF8D_LF
O SNNOlC_sV OD_NH=O_NlsOCVDS
O_D HD=O O
SD FO_sbCH_F8H4rd:=j9V#NDCN,VD,#CV#NDCN,VD,#CV#NDCs,0k0C,s,kC0Csk,DVN#0C,s,kC0Csk,k0sCN,VD,#CV#NDCs,0k0C,s,kCV#NDCs,0kVC,NCD#,k0sCs,0kVC,NCD#,DVN#0C,s,kCV#NDCs,0kVC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#SC
b#kDCC_8D_N$H4rd:=j9V#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD
#CS#sCCH0_=MoCCDsN_#sCCS0
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b#kDCC_8D_N$H4rd:=j9V#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCs,0kSC
sCC#0=_HoCCMs_NDsCC#0F
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SC__MFC=F_FM_
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SC0#C_oH=CsMCNsD_C0#C
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Rd@@((:cd::cc:(d.IjRFRs NlON_l0HCMOF0DsF_0HMCNsVOsCR0NDRO_Nl0HHlMLo_D FO
sSCsD_VNHo_=sCs_NVDo
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#s0N0H_8#=_F#s0N0H_8#
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OSNNsl_H_#CHVM0D_Nob=_FNlON_#sHCM_H0NVDo
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O_$OH#=Os$_OO9rj
NS80r_Hdj4:9#=OsN_80r_Idj4:9#
S0HL_=sO#_L#0
......@@ -7917,7 +8106,7 @@ SOF _=lNO_ NO
NS80r_Fdj4:9O=NlN_80r_sdj4:9N;
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......@@ -7965,7 +8154,7 @@ ICSN8l_OO$_8F=lON_$SO
8_lN#D0ND=_H#sbNC;_F
RNH3M#$_Ck#s__#bNNsl"#Ro#_OsL_I_N#DP_C#M"LR;H
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Rd@@n(:6d::c6:(d4IgRFRs O_D s_#0lNNMossR0ODRD_ #s##0_lloC
Rd@@(U:6n::c6:Un4IgRFRs O_D s_#0lNNMossR0ODRD_ #s##0_lloC
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DSbD8_D_bH=DDD_8
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......@@ -7986,59 +8175,54 @@ S8OO_DF _= OD;H
NR$3#M#_kC#s__sbNNRl#"DPNk_C#V_Fs#kHlDHN0FMMRLV_F_osCR
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SF0kM_M8FC8=0OC_D8F_Ok_M08CFM
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CsS OD=C#bOD_O C
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Rd@@(n:dc::(d:nc4#UR8sVVCbR#CDO_Cs8_C#8Rb_COD_C8sRC8#ObC_8DC\b3#CDO_Cs8_C.8_RC#bOD_O R
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NR03sDs_FHNoMl"CR#ObC_8DC_8sC"C;
;
hdl/spec/syn/test_tdc_acam/syn_tdc.tlg
View file @ 07fa5b23
@N: CD630 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":29:7:29:13|Synthesizing work.top_tdc.rtl
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":354:7:354:12|Signal pll_cs is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":359:7:359:19|Signal tdc_led_trig1 is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":360:7:360:19|Signal tdc_led_trig2 is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":361:7:361:19|Signal tdc_led_trig3 is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":362:7:362:19|Signal tdc_led_trig4 is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":367:7:367:18|Signal acam_start01 is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":368:7:368:20|Signal acam_timestamp is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":369:7:369:26|Signal acam_timestamp_valid is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":370:7:370:20|Signal full_timestamp is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":371:7:371:26|Signal full_timestamp_valid is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":374:7:374:21|Signal start_nb_offset is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":375:7:375:21|Signal start_timer_reg is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":376:7:376:22|Signal utc_current_time is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":387:7:387:11|Signal irq_p is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":404:7:404:15|Signal dma_dat_o is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":405:7:405:13|Signal dma_ack is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":406:7:406:15|Signal dma_stall is undriven
@N: CD630 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/free_counter.vhd":15:7:15:18|Synthesizing work.free_counter.rtl
Post processing for work.free_counter.rtl
@N: CD630 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":29:7:29:13|Synthesizing work.top_tdc.rtl
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":353:7:353:20|Signal tdc_led_period is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":361:7:361:12|Signal pll_cs is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":366:7:366:19|Signal tdc_led_trig1 is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":367:7:367:19|Signal tdc_led_trig2 is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":368:7:368:19|Signal tdc_led_trig3 is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":369:7:369:19|Signal tdc_led_trig4 is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":370:7:370:19|Signal tdc_led_trig5 is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":376:7:376:18|Signal acam_start01 is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":377:7:377:20|Signal acam_timestamp is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":378:7:378:26|Signal acam_timestamp_valid is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":385:7:385:21|Signal start_timer_reg is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":386:7:386:22|Signal utc_current_time is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":397:7:397:11|Signal irq_p is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":414:7:414:15|Signal dma_dat_o is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":415:7:415:13|Signal dma_ack is undriven
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":416:7:416:15|Signal dma_stall is undriven
@N: CD630 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/countdown_counter.vhd":17:7:17:23|Synthesizing work.countdown_counter.rtl
Post processing for work.countdown_counter.rtl
@N: CD630 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/free_counter.vhd":15:7:15:18|Synthesizing work.free_counter.rtl
Post processing for work.free_counter.rtl
@N: CD630 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":32:7:32:20|Synthesizing work.clk_rst_managr.rtl
@N: CD231 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":84:24:84:25|Using onehot encoding for type t_pll_init_st (start="10000")
@N: CD630 :"/afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/xilinx/unisim.vhd":6077:10:6077:15|Synthesizing unisim.ibufds.syn_black_box
......@@ -393,49 +392,61 @@ Post processing for work.gn4124_core.rtl
Post processing for work.acam_databus_interface.rtl
@N: CD630 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd":27:7:27:32|Synthesizing work.acam_timecontrol_interface.rtl
Post processing for work.acam_timecontrol_interface.rtl
@N: CL177 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd":79:7:79:15|Sharing sequential element start_dis.
@N: CD630 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd":28:7:28:21|Synthesizing work.data_formatting.rtl
@W: CD638 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd":64:7:64:14|Signal reserved is undriven
Post processing for work.data_formatting.rtl
@W: CL111 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd":61:7:61:20|All reachable assignments to full_timestamp(0) assign '0', register removed by optimization
@W: CL111 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd":61:7:61:20|All reachable assignments to full_timestamp(1) assign '0', register removed by optimization
@W: CL111 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd":61:7:61:20|All reachable assignments to full_timestamp(2) assign '0', register removed by optimization
@N: CD630 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_retrigger_control.vhd":31:7:31:29|Synthesizing work.start_retrigger_control.rtl
Post processing for work.start_retrigger_control.rtl
@N: CD630 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd":27:7:27:16|Synthesizing work.one_hz_gen.rtl
Post processing for work.one_hz_gen.rtl
Post processing for work.top_tdc.rtl
@W: CL240 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":406:7:406:15|dma_stall is not assigned a value (floating) - a simulation mismatch is possible
@W: CL240 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":405:7:405:13|dma_ack is not assigned a value (floating) - a simulation mismatch is possible
@W: CL240 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":387:7:387:11|irq_p is not assigned a value (floating) - a simulation mismatch is possible
@W: CL240 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":60:8:60:14|spare_o is not assigned a value (floating) - a simulation mismatch is possible
@W: CL168 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":461:4:461:20|Pruning instance acam_timing_block - not in use ...
@W: CL167 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Input irq_p_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 0 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 1 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 2 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 3 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 4 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 5 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 6 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 7 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 8 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 9 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 10 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 11 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 12 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 13 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 14 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 15 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 16 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 17 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 18 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 19 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 20 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 21 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 22 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 23 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 24 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 25 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 26 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 27 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 28 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 29 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 30 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Bit 31 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL167 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Input dma_ack_i of instance gnum_interface_block is floating
@W: CL167 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":517:4:517:23|Input dma_stall_i of instance gnum_interface_block is floating
@W: CL240 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":416:7:416:15|dma_stall is not assigned a value (floating) - a simulation mismatch is possible
@W: CL240 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":415:7:415:13|dma_ack is not assigned a value (floating) - a simulation mismatch is possible
@W: CL240 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":397:7:397:11|irq_p is not assigned a value (floating) - a simulation mismatch is possible
@W: CL240 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":378:7:378:26|acam_timestamp_valid is not assigned a value (floating) - a simulation mismatch is possible
@W: CL240 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":60:8:60:14|spare_o is not assigned a value (floating) - a simulation mismatch is possible
@W: CL168 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":456:4:456:24|Pruning instance data_formatting_block - not in use ...
@W: CL167 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Input irq_p_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 0 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 1 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 2 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 3 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 4 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 5 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 6 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 7 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 8 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 9 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 10 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 11 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 12 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 13 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 14 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 15 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 16 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 17 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 18 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 19 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 20 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 21 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 22 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 23 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 24 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 25 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 26 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 27 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 28 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 29 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 30 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL245 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Bit 31 of input dma_dat_i of instance gnum_interface_block is floating
@W: CL167 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Input dma_ack_i of instance gnum_interface_block is floating
@W: CL167 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd":530:4:530:23|Input dma_stall_i of instance gnum_interface_block is floating
@W: CL247 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd":34:8:34:23|Input port bit 17 of acam_timestamp_i(28 downto 0) is unused
@W: CL246 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd":38:8:38:24|Input port bits 31 to 24 of start_nb_offset_i(31 downto 0) are unused
@N: CL201 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_databus_interface.vhd":68:7:68:18|Trying to extract state machine for register acam_data_st
Extracted state machine for register acam_data_st
State machine has 7 reachable states with original encodings of:
......@@ -585,5 +596,3 @@ State machine has 5 reachable states with original encodings of:
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":40:8:40:19|Input pll_refmon_i is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":41:8:41:16|Input pll_sdo_i is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":42:8:42:19|Input pll_status_i is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":77:8:77:17|Input err_flag_i is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd":78:8:78:17|Input int_flag_i is unused
hdl/spec/syn/test_tdc_acam/synplicity.ucf
View file @ 07fa5b23
......@@ -22,9 +22,14 @@ NET "pll_cs_o" TNM = "pll_cs_o";
NET "pll_sdi_o" TNM = "pll_cs_o";
NET "pll_sclk_o" TNM = "pll_cs_o";
TIMEGRP "pll_cs_o" OFFSET = OUT: 48.000 : AFTER spec_clk_i;
NET "data_bus_io(*)" TNM = "data_bus_io___";
NET "address_o(*)" TNM = "data_bus_io___";
TIMEGRP "data_bus_io___" OFFSET = OUT: 6.000 : AFTER tdc_clk_p_i;
NET "start_dis_o" TNM = "start_dis_o";
NET "start_from_fpga_o" TNM = "start_dis_o";
NET "cs_n_o" TNM = "start_dis_o";
NET "rd_n_o" TNM = "start_dis_o";
NET "wr_n_o" TNM = "start_dis_o";
NET "data_bus_io(*)" TNM = "start_dis_o";
NET "address_o(*)" TNM = "start_dis_o";
TIMEGRP "start_dis_o" OFFSET = OUT: 6.000 : AFTER tdc_clk_p_i;
NET "rx_error_o" TNM = "rx_error_o";
NET "l2p_edb_o" TNM = "rx_error_o";
TIMESPEC TS_rx_error_o_gnum_interface_block_cmp_clk_in_rx_pllout_x1 = FROM "gnum_interface_block_cmp_clk_in_rx_pllout_x1" TO "rx_error_o" 3.000 ns;
......@@ -39,65 +44,40 @@ TIMEGRP "acam_refclk_i" OFFSET = IN: 6.000 : BEFORE tdc_clk_p_i;
NET "l2p_rdy_i" TNM = "l2p_rdy_i";
TIMESPEC TS_l2p_rdy_i_gnum_interface_block_cmp_clk_in_rx_pllout_x1 = FROM "l2p_rdy_i" TO "gnum_interface_block_cmp_clk_in_rx_pllout_x1" 3.000 ns;
# 1037 : define_false_path -to { p:cs_n_o }
# 1037 : define_false_path -from { p:spec_aux0_i }
NET "cs_n_o" TNM = "to_1037_0";
TIMESPEC "TS_1037_0" = TO "to_1037_0" TIG;
NET "spec_aux0_i" TNM = "from_1037_0";
TIMESPEC "TS_1037_0" = FROM "from_1037_0" TIG;
# 1038 : define_false_path -to { p:wr_n_o }
# 1038 : define_false_path -from { p:spec_aux1_i }
NET "wr_n_o" TNM = "to_1038_0";
TIMESPEC "TS_1038_0" = TO "to_1038_0" TIG;
NET "spec_aux1_i" TNM = "from_1038_0";
TIMESPEC "TS_1038_0" = FROM "from_1038_0" TIG;
# 1039 : define_false_path -to { p:rd_n_o }
# 1039 : define_false_path -to { p:spec_aux2_o }
NET "rd_n_o" TNM = "to_1039_0";
NET "spec_aux2_o" TNM = "to_1039_0";
TIMESPEC "TS_1039_0" = TO "to_1039_0" TIG;
# 1040 : define_false_path -from { p:spec_aux0_i }
# 1040 : define_false_path -to { p:spec_aux3_o }
NET "spec_aux0_i" TNM = "from_1040_0";
TIMESPEC "TS_1040_0" = FROM "from_1040_0" TIG;
NET "spec_aux3_o" TNM = "to_1040_0";
TIMESPEC "TS_1040_0" = TO "to_1040_0" TIG;
# 1041 : define_false_path -from { p:spec_aux1_i }
# 1043 : define_false_path -to { p:spec_led_green_o }
NET "spec_aux1_i" TNM = "from_1041_0";
TIMESPEC "TS_1041_0" = FROM "from_1041_0" TIG;
# 1042 : define_false_path -to { p:spec_aux2_o }
NET "spec_aux2_o" TNM = "to_1042_0";
TIMESPEC "TS_1042_0" = TO "to_1042_0" TIG;
# 1043 : define_false_path -to { p:spec_aux3_o }
NET "spec_aux3_o" TNM = "to_1043_0";
NET "spec_led_green_o" TNM = "to_1043_0";
TIMESPEC "TS_1043_0" = TO "to_1043_0" TIG;
# 1046 : define_false_path -to { p:spec_led_green_o }
NET "spec_led_green_o" TNM = "to_1046_0";
TIMESPEC "TS_1046_0" = TO "to_1046_0" TIG;
# 1047 : define_false_path -to { p:spec_led_red_o }
NET "spec_led_red_o" TNM = "to_1047_0";
TIMESPEC "TS_1047_0" = TO "to_1047_0" TIG;
# 1048 : define_false_path -to { p:tdc_led_status_o }
NET "tdc_led_status_o" TNM = "to_1048_0";
TIMESPEC "TS_1048_0" = TO "to_1048_0" TIG;
# 1053 : define_false_path -to { p:tdc_led_trig5_o }
# 1044 : define_false_path -to { p:spec_led_red_o }
NET "tdc_led_trig5_o" TNM = "to_1053_0";
TIMESPEC "TS_1053_0" = TO "to_1053_0" TIG;
NET "spec_led_red_o" TNM = "to_1044_0";
TIMESPEC "TS_1044_0" = TO "to_1044_0" TIG;
# 1054 : define_false_path -to { p:start_from_fpga_o }
# 1045 : define_false_path -to { p:tdc_led_status_o }
NET "start_from_fpga_o" TNM = "to_1054_0";
TIMESPEC "TS_1054_0" = TO "to_1054_0" TIG;
NET "tdc_led_status_o" TNM = "to_1045_0";
TIMESPEC "TS_1045_0" = TO "to_1045_0" TIG;
# Unused constraints (intentionally commented out)
......@@ -107,6 +87,7 @@ TIMESPEC "TS_1054_0" = TO "to_1054_0" TIG;
# define_false_path -to { p:tdc_led_trig2_o }
# define_false_path -to { p:tdc_led_trig3_o }
# define_false_path -to { p:tdc_led_trig4_o }
# define_false_path -to { p:tdc_led_trig5_o }
# Location Constraints
PIN "clks_rsts_mgment.spec_clk_gbuf.O" CLOCK_DEDICATED_ROUTE = FALSE;
......
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