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FMC TDC 1ns 5cha - Gateware
Commit 10b74dcd authored by egousiou's avatar egousiou
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svec code cleanup 

git-svn-id: http://svn.ohwr.org/fmc-tdc@171 85dfdc96-de2c-444c-878d-45b388be74a9
parent 9c3cd122
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Showing with 1653 additions and 1629 deletions
hdl/wrabbit_tdc/hdl/rtl/clks_rsts_manager.vhd
View file @ 10b74dcd
......@@ -37,7 +37,7 @@
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 02/2014 |
-- Version v0.4 |
-- Version v1 |
-- Depends on |
-- |
---------------- |
......@@ -48,7 +48,7 @@
-- on the pll_status activation |
-- General revamping, comments added, signals renamed |
-- 05/2012 v0.3 EG Added logic for DAC configuration |
-- 02/2014 v0.4 EG Correction for the DAC on rising edges; added wrabbit support |
-- 02/2014 v1 EG Correction for the DAC on rising edges; added wrabbit support |
-- |
---------------------------------------------------------------------------------------------------
......@@ -462,7 +462,7 @@ begin
---------------------------------------------------------------------------------------------------
pll_dac_initialization_comb: process (config_st, dac_bit_index, pll_byte_index, pll_bit_index, sclk,
sclk_r_edge, sclk_f_edge)
sclk_r_edge, sclk_f_edge, dac_only)
begin
case config_st is
......
hdl/wrabbit_tdc/hdl/rtl/data_engine.vhd
View file @ 10b74dcd
......@@ -194,7 +194,8 @@ begin
data_engine_fsm_comb: process (engine_st, activate_acq_p_i, deactivate_acq_p_i, acam_ef1_i, acam_adr,
acam_ef2_i, acam_ef1_meta_i, acam_ef2_meta_i, acam_wr_config_p_i,
acam_rdbk_config_p_i, acam_rdbk_status_p_i, acam_ack_i, acam_rst_p_i,
acam_rdbk_ififo1_p_i, acam_rdbk_ififo2_p_i, acam_rdbk_start01_p_i)
acam_rdbk_ififo1_p_i, acam_rdbk_ififo2_p_i, acam_rdbk_start01_p_i,
start_from_fpga_i, time_c, time_c_full_p)
begin
case engine_st is
......
hdl/wrabbit_tdc/hdl/rtl/data_formatting.vhd
View file @ 10b74dcd
......@@ -135,7 +135,7 @@ architecture rtl of data_formatting is
constant c_MULTIPLY_BY_SIXTEEN : std_logic_vector(3 downto 0) := "0000";
-- ACAM timestamp fields
signal acam_channel : std_logic_vector(2 downto 0);
signal acam_slope, acam_fifo_ef : std_logic;
signal acam_slope : std_logic;
signal acam_fine_timestamp : std_logic_vector(16 downto 0);
signal acam_start_nb : unsigned(7 downto 0);
-- timestamp manipulations
......@@ -328,21 +328,18 @@ begin
if rising_edge (clk_i) then
if rst_i ='1' then
acam_channel <= (others => '0');
acam_fifo_ef <= '0';
acam_fine_timestamp <= (others => '0');
acam_slope <= '0';
acam_start_nb <= (others => '0');
elsif acam_tstamp1_ok_p_i = '1' then
acam_channel <= "0" & acam_tstamp1_i(27 downto 26);
acam_fifo_ef <= acam_tstamp1_i(31);
acam_fine_timestamp <= acam_tstamp1_i(16 downto 0);
acam_slope <= acam_tstamp1_i(17);
acam_start_nb <= unsigned(acam_tstamp1_i(25 downto 18))-1;
elsif acam_tstamp2_ok_p_i ='1' then
acam_channel <= "1" & acam_tstamp2_i(27 downto 26);
acam_fifo_ef <= acam_tstamp2_i(30);
acam_fine_timestamp <= acam_tstamp2_i(16 downto 0);
acam_slope <= acam_tstamp2_i(17);
acam_start_nb <= unsigned(acam_tstamp2_i(25 downto 18))-1;
......
hdl/wrabbit_tdc/hdl/rtl/fmc_tdc_core.vhd
View file @ 10b74dcd
......@@ -416,7 +416,6 @@ begin
state_active_p_i => state_active_p,
deactivate_acq_p_i => deactivate_acq_p,
rst_i => rst_i,
window_delay_i => window_delay,
acam_errflag_f_edge_p_o => acam_errflag_f_edge_p,
acam_errflag_r_edge_p_o => acam_errflag_r_edge_p,
acam_intflag_f_edge_p_o => acam_intflag_f_edge_p);
......@@ -463,7 +462,7 @@ begin
clk_i => clk_125m_i,
utc_p_i => utc_p,
rst_i => rst_i,
current_retrig_nb_o => current_retrig_nb,
current_retrig_nb_o => current_retrig_nb, -- for debug
roll_over_incr_recent_o => roll_over_incr_recent,
clk_i_cycles_offset_o => clk_i_cycles_offset,
roll_over_nb_o => roll_over_nb,
......
hdl/wrabbit_tdc/hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 10b74dcd
......@@ -22,14 +22,7 @@
-- sources into one WISHBONE interrupt request line. |
-- |
-- For the interconnection between the GN4124/VME core and the different cores (TDC, |
-- I2C, 1W, EIC) the unit instantiates an SDB crossbar. |
-- |
-- Note that the TDC core has two WISHBONE buses, one for the configuration (of the |
-- core itself and of the ACAM) and one for the retrieval of the timestamps from the |
-- memory. |
-- |
-- Note that the SPI interface for the DAC on the TDC board is implemented in the |
-- clcks_rsts_manager;no access to the DAC is provided through GN4124/VME interface |
-- I2C, 1W, EIC, timestamps memory) the unit instantiates an SDB crossbar. |
-- |
-- Note that the TDC core uses word addressing, whereas the GN4124/VME cores use byte|
-- addressing |
......@@ -112,7 +105,8 @@ use work.wishbone_pkg.all;
--=================================================================================================
entity fmc_tdc_mezzanine is
generic
(g_span : integer := 32;
(g_with_wrabbit_core : boolean := FALSE;
g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := FALSE);
port
......@@ -183,12 +177,12 @@ entity fmc_tdc_mezzanine is
wb_tdc_csr_stall_o : out std_logic;
wb_irq_o : out std_logic;
-- I2C EEPROM interface
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_oen_o : out std_logic;
i2c_sda_o : out std_logic;
i2c_sda_i : in std_logic;
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_oen_o : out std_logic;
i2c_sda_o : out std_logic;
i2c_sda_i : in std_logic;
-- 1-Wire interface
onewire_b : inout std_logic);
end fmc_tdc_mezzanine;
......@@ -306,19 +300,19 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
(g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map
(clk_sys_i => clk_ref_0_i,
rst_n_i => rst_ref_0_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
(clk_sys_i => clk_ref_0_i,
rst_n_i => rst_ref_0_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
---------------------------------------------------------------------------------------------------
......@@ -420,7 +414,7 @@ begin
cmp_wrabbit_synch: wrabbit_sync
generic map
(g_simulation => false,
g_with_wrabbit_core => true)
g_with_wrabbit_core => g_with_wrabbit_core)
port map
(clk_sys_i => clk_sys_i,
rst_n_sys_i => rst_sys_n_i,
......@@ -441,7 +435,7 @@ begin
wrabbit_one_hz_pulse : process(clk_ref_0_i)
begin
if rising_edge(clk_ref_0_i) then
if((wrabbit_clk_aux_locked_i = '1' and g_with_wrabbit_core = '1') then
if wrabbit_clk_aux_locked_i = '1' and g_with_wrabbit_core then
if unsigned(wrabbit_cycles_i) = unsigned(c_SYN_CLK_PERIOD) -1 then
wrabbit_utc_p <= '1';
else
......
hdl/wrabbit_tdc/hdl/rtl/wrabbit_sync.vhd
View file @ 10b74dcd
......@@ -53,10 +53,9 @@ use work.gencores_pkg.all;
entity wrabbit_sync is
generic (
-- when true, reduces some timeouts to speed up simulations
g_simulation : boolean;
g_with_wrabbit_core : boolean);
generic
(g_simulation : boolean; -- when true, reduces some timeouts to speed up simulations
g_with_wrabbit_core : boolean);
port(
clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic;
......@@ -94,10 +93,10 @@ entity wrabbit_sync is
end wrabbit_sync;
architecture behavioral of wrabbit_sync is
architecture rtl of wrabbit_sync is
-- System clock frequency in Hz
constant c_SYS_CLK_FREQ : integer := 125000000;
constant c_SYS_CLK_FREQ : integer := 62500000;
-- FSM timeout period calculation
impure function f_eval_timeout return integer is
begin
......@@ -113,7 +112,6 @@ architecture behavioral of wrabbit_sync is
type t_wrabbit_sync_state is (wrabbit_CORE_OFFLINE, wrabbit_WAIT_READY, wrabbit_SYNCING, wrabbit_SYNCED);
signal wrabbit_state : t_wrabbit_sync_state;
signal wrabbit_state_changed : std_logic;
signal csync_wrabbit_sysclk : std_logic;
signal wrabbit_state_syncing, wrabbit_en : std_logic;
signal wrabbit_clk_aux_lock_en : std_logic;
-- FSM timeout counter
......@@ -124,27 +122,28 @@ architecture behavioral of wrabbit_sync is
signal clk_aux_locked, link_up : std_logic_vector (1 downto 0);
signal state_syncing, clk_aux_lock_en : std_logic_vector (1 downto 0);
-- aux
signal dac_p_c : unsigned(23 downto 0);
signal with_wrabbit_core : std_logic;
signal dac_p_c : unsigned(23 downto 0); -- for debug
begin -- behavioral
begin
p_dac_p_counter : process(clk_sys_i)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronization of the wrabbit_reg_i(0) of the reg_ctrl unit to the 62.5 MHz domain
input_synchronizer: process (clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rising_edge (clk_sys_i) then
if rst_n_sys_i = '0' then
dac_p_c <= (others => '0');
wrabbit_en_sync <= (others => '0');
else
if dac_p_c = "111111111111111111111111" then
dac_p_c <= (others => '0');
elsif wrabbit_dac_wr_p_i = '1' then
dac_p_c <= dac_p_c + 1;
end if;
wrabbit_en_sync <= wrabbit_en_sync(0) & wrabbit_reg_i(0);
end if;
end if;
end process;
wrabbit_en <= wrabbit_en_sync(1);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FSM timeout counter
p_timeout_counter : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
......@@ -159,27 +158,15 @@ begin -- behavioral
end if;
end if;
end process;
tmo_restart <= wrabbit_state_changed;
input_synchronizer: process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if rst_n_sys_i = '0' then
wrabbit_en_sync <= (others => '0');
else
wrabbit_en_sync <= wrabbit_en_sync(0) & wrabbit_reg_i(0);
end if;
end if;
end process;
wrabbit_en <= wrabbit_en_sync(1);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FSM
gen_with_wr_core : if(g_with_wrabbit_core) generate
p_whiterabbit_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_sys_i = '0' then
csync_wrabbit_sysclk <= '0';
wrabbit_clk_aux_lock_en <= '0';
wrabbit_state <= wrabbit_CORE_OFFLINE;
wrabbit_state_changed <= '0';
else
......@@ -214,14 +201,12 @@ begin -- behavioral
wrabbit_state_changed <= '1';
elsif(wrabbit_clk_aux_locked_i = '1' and tmo_hit = '1') then
wrabbit_state <= wrabbit_SYNCED;
csync_wrabbit_sysclk <= '1';
wrabbit_state_changed <= '1';
else
wrabbit_state_changed <= '0';
end if;
when wrabbit_SYNCED =>
csync_wrabbit_sysclk <= '0';
if(wrabbit_time_valid_i = '0' or wrabbit_en = '0' or wrabbit_clk_aux_locked_i = '0') then
wrabbit_state <= wrabbit_SYNCING;
......@@ -233,8 +218,10 @@ begin -- behavioral
end if;
end if;
end process;
end generate gen_with_wr_core;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronization of the outputs to the 125 MHz domain to be used by the reg_ctrl unit
outputs_synchronizer: process (clk_ref_i)
begin
if rising_edge (clk_ref_i) then
......@@ -254,21 +241,39 @@ begin -- behavioral
end if;
end process;
wrabbit_synched_o <= clk_aux_locked(1);
wrabbit_state_syncing <= '1' when (wrabbit_state = wrabbit_SYNCING or wrabbit_state = wrabbit_SYNCED) else '0';
wrabbit_clk_aux_lock_en_o <= clk_aux_lock_en(1);
with_wrabbit_core <= '1' when g_with_wrabbit_core else '0';
wrabbit_synched_o <= clk_aux_locked(1) and with_wrabbit_core;
wrabbit_clk_aux_lock_en_o <= clk_aux_lock_en(1) and with_wrabbit_core;
wrabbit_state_syncing <= '1' when ((wrabbit_state = wrabbit_SYNCING or wrabbit_state = wrabbit_SYNCED) and with_wrabbit_core = '1') else '0';
wrabbit_reg_o(0) <= '1'; -- reserved
wrabbit_reg_o(1) <= '1'; -- reserved
wrabbit_reg_o(2) <= link_up(1);
wrabbit_reg_o(3) <= state_syncing(1);
wrabbit_reg_o(4) <= clk_aux_locked(1);
wrabbit_reg_o(5) <= time_valid(1);
wrabbit_reg_o(6) <= wrabbit_reg_i(0);
wrabbit_reg_o(7) <= clk_aux_locked(1);
wrabbit_reg_o(8) <= time_valid(1);
wrabbit_reg_o(9) <= clk_aux_lock_en(1);
wrabbit_reg_o(15 downto 10) <= std_logic_vector(dac_p_c(5 downto 0));
wrabbit_reg_o(31 downto 16) <= wrabbit_dac_value_i(15 downto 0);
end behavioral;
wrabbit_reg_o(1) <= with_wrabbit_core;
wrabbit_reg_o(2) <= link_up(1) and with_wrabbit_core;
wrabbit_reg_o(3) <= state_syncing(1) and with_wrabbit_core;
wrabbit_reg_o(4) <= clk_aux_locked(1) and with_wrabbit_core;
wrabbit_reg_o(5) <= time_valid(1) and with_wrabbit_core;
wrabbit_reg_o(6) <= wrabbit_reg_i(0) and with_wrabbit_core;
wrabbit_reg_o(7) <= clk_aux_locked(1) and with_wrabbit_core;
wrabbit_reg_o(8) <= time_valid(1) and with_wrabbit_core;
wrabbit_reg_o(9) <= clk_aux_lock_en(1) and with_wrabbit_core;
wrabbit_reg_o(15 downto 10) <= (others => '0') when with_wrabbit_core = '1' else std_logic_vector(dac_p_c(5 downto 0));
wrabbit_reg_o(31 downto 16) <= (others => '0') when with_wrabbit_core = '1' else wrabbit_dac_value_i(15 downto 0);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- used only for debug
p_dac_p_counter : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_sys_i = '0' then
dac_p_c <= (others => '0');
else
if dac_p_c = "111111111111111111111111" then
dac_p_c <= (others => '0');
elsif wrabbit_dac_wr_p_i = '1' then
dac_p_c <= dac_p_c + 1;
end if;
end if;
end if;
end process;
end rtl;
hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.twr
View file @ 10b74dcd
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc_map.mrp
View file @ 10b74dcd
......@@ -11,23 +11,23 @@ Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Jun 05 18:39:40 2014
Mapped Date : Fri Jun 13 19:47:57 2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 10
Slice Logic Utilization:
Number of Slice Registers: 11,618 out of 184,304 6%
Number used as Flip Flops: 11,567
Number of Slice Registers: 11,568 out of 184,304 6%
Number used as Flip Flops: 11,517
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 47
Number of Slice LUTs: 15,904 out of 92,152 17%
Number used as logic: 15,581 out of 92,152 16%
Number using O6 output only: 11,173
Number using O5 output only: 876
Number using O5 and O6: 3,532
Number of Slice LUTs: 15,931 out of 92,152 17%
Number used as logic: 15,521 out of 92,152 16%
Number using O6 output only: 11,161
Number using O5 output only: 830
Number using O5 and O6: 3,530
Number used as ROM: 0
Number used as Memory: 87 out of 21,680 1%
Number used as Dual Port RAM: 24
......@@ -39,21 +39,21 @@ Slice Logic Utilization:
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 38
Number used exclusively as route-thrus: 236
Number with same-slice register load: 134
Number used exclusively as route-thrus: 323
Number with same-slice register load: 221
Number with same-slice carry load: 102
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 6,491 out of 23,038 28%
Nummber of MUXCYs used: 3,636 out of 46,076 7%
Number of LUT Flip Flop pairs used: 18,634
Number with an unused Flip Flop: 7,901 out of 18,634 42%
Number with an unused LUT: 2,730 out of 18,634 14%
Number of fully used LUT-FF pairs: 8,003 out of 18,634 42%
Number of unique control sets: 501
Number of occupied Slices: 5,999 out of 23,038 26%
Nummber of MUXCYs used: 3,580 out of 46,076 7%
Number of LUT Flip Flop pairs used: 18,089
Number with an unused Flip Flop: 7,507 out of 18,089 41%
Number with an unused LUT: 2,158 out of 18,089 11%
Number of fully used LUT-FF pairs: 8,424 out of 18,089 46%
Number of unique control sets: 500
Number of slice register sites lost
to control set restrictions: 1,176 out of 184,304 1%
to control set restrictions: 1,202 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -63,7 +63,7 @@ Slice Logic Distribution:
IO Utilization:
Number of bonded IOBs: 269 out of 540 49%
Number of LOCed IOBs: 267 out of 269 99%
Number of LOCed IOBs: 269 out of 269 100%
IOB Flip Flops: 203
Number of bonded IPADs: 4 out of 32 12%
Number of LOCed IPADs: 4 out of 4 100%
......@@ -105,9 +105,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.80
Peak Memory Usage: 606 MB
Peak Memory Usage: 603 MB
Total REAL time to MAP completion: 5 mins 57 secs
Total CPU time to MAP completion: 5 mins 53 secs
Total CPU time to MAP completion: 5 mins 55 secs
Table of Contents
-----------------
......@@ -134,36 +134,36 @@ WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc2/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_291_o_Mux_41_o is
cmp_tdc2/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_290_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc1/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_291_o_Mux_41_o is
cmp_tdc1/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_290_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
......@@ -203,9 +203,6 @@ INFO:Timing:3386 - Intersecting Constraints found and resolved. For more inform
Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Place:834 - Only a subset of IOs are locked. Out of 269 IOs, 267 are locked
and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
......
hdl/wrabbit_tdc/hdl/top/svec/sdb_meta_pkg.vhd
View file @ 10b74dcd
......@@ -12,7 +12,7 @@
---------------------------------------------------------------------------------------------------
-- File sdb_meta_pkg.vhd |
-- |
-- Description Sdb meta-information for the FMC TDC design for SPEC. |
-- Description Sdb meta-information for the FMC TDC design for SVEC. |
-- |
-- Authors Matthieu Cattin (matthieu.cattin@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
......@@ -50,12 +50,12 @@ package sdb_meta_pkg is
-- Top module repository url
constant c_SDB_REPO_URL : t_sdb_repo_url := (
-- url (string, 63 char)
repo_url => "http://svn.ohwr.org/fmc-tdc/hdl/spec/ ");
repo_url => "http://svn.ohwr.org/fmc-tdc/hdl/ ");
-- Synthesis informations
constant c_SDB_SYNTHESIS : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_tdc",
syn_module_name => "svec_top_fmc_tdc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-320
syn_commit_id => x"00000000",
......
hdl/wrabbit_tdc/hdl/top/svec/svec_tdc.ucf
View file @ 10b74dcd
#
# Clocks
#
NET "clk_62m5_sys" TNM_NET = "clk_62m5_sys";
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
NET "tdc1_clk_125m" TNM_NET = "tdc1_clk_125m";
NET "tdc2_clk_125m" TNM_NET = "tdc2_clk_125m";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# FMC1/FMC2 detection
#----------------------------------------
NET "tdc1_prsntm2c_n_i" LOC = N30;
NET "tdc2_prsntm2c_n_i" LOC = AE29;
TIMESPEC ts_ignore_xclock1 = FROM "clk_62m5_sys" TO "tdc1_clk_125m" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "tdc1_clk_125m" TO "clk_62m5_sys" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_62m5_sys" TO "tdc1_clk_125m" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "tdc1_clk_125m" TO "clk_62m5_sys" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_20m_vcxo_i" TO "clk_62m5_sys" 200ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_62m5_sys" TO "clk_20m_vcxo_i" 200ns DATAPATHONLY;
# SVEC clock/reset
NET "clk_20m_vcxo_i" LOC = V26;
NET "por_n_i" LOC = AD28;
NET "clk_20m_vcxo_i" IOSTANDARD="LVCMOS33";
NET "por_n_i" IOSTANDARD="LVCMOS33";
NET "tdc1_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
NET "tdc2_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
# mezzanine detection / i2c
NET "tdc1_prsntm2c_n_i" LOC = N30;
#----------------------------------------
# FMC1/FMC2 I2C
#----------------------------------------
NET "tdc1_scl_b" LOC = P28;
NET "tdc1_sda_b" LOC = P30;
NET "tdc2_prsntm2c_n_i" LOC = AE29;
NET "tdc2_scl_b" LOC = W29;
NET "tdc2_sda_b" LOC = V30;
NET "tdc2_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
NET "tdc1_scl_b" IOSTANDARD = "LVCMOS33";
NET "tdc1_sda_b" IOSTANDARD = "LVCMOS33";
NET "tdc2_scl_b" IOSTANDARD = "LVCMOS33";
NET "tdc2_sda_b" IOSTANDARD = "LVCMOS33";
NET "tdc1_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
NET "tdc1_scl_b" IOSTANDARD = "LVCMOS33";
NET "tdc1_sda_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Carrier 1-Wire
#----------------------------------------
NET "carrier_onewire_b" LOC = AC30;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# PCB version
#----------------------------------------
NET "pcb_ver_i[0]" LOC = AD20;
NET "pcb_ver_i[1]" LOC = AE20;
NET "pcb_ver_i[2]" LOC = AD18;
NET "pcb_ver_i[3]" LOC = AE17;
NET "pcb_ver_i[0]" IOSTANDARD="LVCMOS33";
NET "pcb_ver_i[1]" IOSTANDARD="LVCMOS33";
NET "pcb_ver_i[2]" IOSTANDARD="LVCMOS33";
NET "pcb_ver_i[3]" IOSTANDARD="LVCMOS33";
#----------------------------------------
# SVEC front panel LEDs
#----------------------------------------
NET "fp_led_line_oen_o[0]" LOC = AD26;
NET "fp_led_line_oen_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_oen_o[1]" LOC = AD27;
NET "fp_led_line_oen_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[0]" LOC = AC27;
NET "fp_led_line_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[1]" LOC = AC28;
NET "fp_led_line_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[0]" LOC = AE30;
NET "fp_led_column_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[1]" LOC = AE27;
NET "fp_led_column_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[2]" LOC = AE28;
NET "fp_led_column_o[2]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[3]" LOC = AF28;
NET "fp_led_line_oen_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_oen_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[2]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[3]" IOSTANDARD="LVCMOS33";
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_rst_n_i" LOC = P4;
#NET "vme_sysclk_i" LOC = P3;
......@@ -273,6 +271,9 @@ NET "vme_addr_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[1]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMC1
#----------------------------------------
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
......@@ -408,6 +409,10 @@ NET "tdc1_enable_inputs_o" LOC = "J12";
NET "tdc1_enable_inputs_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_onewire_b" LOC = "H12";
NET "tdc1_onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC2
#----------------------------------------
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 1
NET "tdc2_acam_refclk_p_i" LOC = "AF16";
NET "tdc2_acam_refclk_p_i" IOSTANDARD = "LVDS_25";
......@@ -542,18 +547,21 @@ NET "tdc2_enable_inputs_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_onewire_b" LOC = "AB19";
NET "tdc2_onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SFP slot
#----------------------------------------
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
NET "sfp_txp_o" LOC = B23;
NET "sfp_txn_o" LOC = A23;
NET "sfp_rxp_i" LOC = D22;
NET "sfp_rxn_i" LOC = C22;
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "sfp_los_i" LOC = W25;
NET "sfp_mod_def0_b" LOC = Y26;
NET "sfp_mod_def1_b" LOC = Y27;
......@@ -592,11 +600,35 @@ NET "uart_rxd_i" LOC = U25;
NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock stuff
#----------------------------------------
# SVEC VCXO clock/reset
NET "clk_20m_vcxo_i" LOC = V26;
NET "por_n_i" LOC = AD28;
NET "clk_20m_vcxo_i" IOSTANDARD="LVCMOS33";
NET "por_n_i" IOSTANDARD="LVCMOS33";
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
# 62.5MHz Xilinx PLL clock/reset
NET "clk_62m5_sys" TNM_NET = "clk_62m5_sys";
# 125MHz PLL ref
NET "clk_125m_pllref_n_i" LOC = AB30;
NET "clk_125m_pllref_p_i" LOC = AB28;
# 125MHz TDC PLL clock
NET "tdc1_125m_clk" TNM_NET = "tdc1_125m_clk";
NET "tdc2_125m_clk" TNM_NET = "tdc2_125m_clk";
# <ucfgen_end>
#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2013/07/19
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
......@@ -612,7 +644,16 @@ TIMESPEC TS_tdc2_tdc_125m_clk_p_i = PERIOD "tdc2_125m_clk_p_i" 8 ns HIGH 50%;
NET "tdc2_125m_clk_n_i" TNM_NET = tdc2_125m_clk_n_i;
TIMESPEC TS_tdc2_tdc_125m_clk_n_i = PERIOD "tdc2_125m_clk_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
# TS_IGNORE
TIMESPEC ts_ignore_xclock1 = FROM "clk_62m5_sys" TO "tdc1_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "tdc1_125m_clk" TO "clk_62m5_sys" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_62m5_sys" TO "tdc1_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "tdc1_125m_clk" TO "clk_62m5_sys" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock1 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "tdc2_125m_clk" TO "clk_62m5_sys" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "tdc2_125m_clk" TO "clk_62m5_sys" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_20m_vcxo_i" TO "clk_62m5_sys" 200ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_62m5_sys" TO "clk_20m_vcxo_i" 200ns DATAPATHONLY;
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