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FMC TDC 1ns 5cha - Gateware
Commit 12d884ea authored by egousiou's avatar egousiou
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small changes on spec tdc testbench 

git-svn-id: http://svn.ohwr.org/fmc-tdc@159 85dfdc96-de2c-444c-878d-45b388be74a9
parent 8a92aa76
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Showing with 17 additions and 222 deletions
hdl/sim/spec/data_vectors/acam_test_cmd0.vec deleted 100644 → 0
View file @ 8a92aa76
-------------------------------------------------------------------------------
-- acam_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
-- Initialize the BFM to its default state
init
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
bfm_bar 1 0000000020000000 20000000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d50000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d60000
-------------------------------------------------------------------------------
-- Access the tdc core register space
-------------------------------------------------------------------------------
-- the following writes will go out in a single packet
-- Gonzalo: 3 writings outside of the BAR defined memory space to check that
-- the BFM model does not forward them to the Local bus
wr 0000000040000808 F 0001F04C
wait %d50
wr 0000000040000800 F 00021040
wait %d50
wr 0000000040000800 F 00025000
wait %d50
-- Gonzalo: 5 reads inside Matthieu's core memory space to check that the core
-- does not forward them to the wishbone bus
rd 0000000000000000 F 0000A0A1
wait %d20
rd 0000000000000004 F 0000A0A2
wait %d20
rd 0000000000000008 F 0000A0A3
wait %d20
rd 000000000000000C F 0000A0A4
wait %d20
rd 0000000000000010 F 0000A0A5
wait %d60
-- Gonzalo: actual wr and rd for test
wr 0000000000005000 F 0000FC81
wait %d50
wr 000000000000502C F 00FF0000
wait %d50
rd 0000000000080000 F 0000FC81
wait %d50
rd 000000000008002C F 00FF0000
wait %d50
wr 0000000000080030 F 04000000
wait %d50
rd 0000000000080030 F 04000000
wait %d50
hdl/sim/spec/data_vectors/atdc_test_cmd0.vec
View file @ 12d884ea
......@@ -86,7 +86,7 @@ wr 00000000000510FC F 00000001
wait %d540000
-- read circular buffer wr pointer
rd 000000000005109C F 00000000
rd 00000000000510A8 F 00000000
wait %d200
......@@ -94,6 +94,18 @@ wait %d200
wr 00000000000510FC F 00000002
wait %d200
-- read a timestamps from memory
rd 0000000000054000 F 00000000
wait %d100
rd 0000000000054004 F 00000000
wait %d100
rd 0000000000054008 F 00000000
wait %d100
rd 000000000005400C F 00000000
wait %d100
-- read acam status
wr 00000000000510FC F 00000010
wait %d100
......@@ -136,35 +148,3 @@ wait %d200
--wr 00000000000510FC F 00000002
--wait %d100
-----------------------------------------------------------------------------
---- Gonzalo: registers inside Matthieu's core memory space are written with the
---- settings for DMA transfer
--
---- Start address on the carrier local memory
--wr 0000000000000008 F 00000000
--wait %d20
--
---- Start addresses on the PCI host memory
--wr 000000000000000C F 0000A0A4
--wait %d20
--wr 0000000000000010 F 0000A0A5
--wait %d20
--
---- Transfer length
--wr 0000000000000014 F 00000060
--wait %d20
--
---- Chain control
--wr 0000000000000020 F 00000000
--wait %d60
--
---- Start transfer through the Control register and check through the status register
--wr 0000000000000000 F 00000001
--wait %d100
--rd 0000000000000004 F 00000001
--wait %d100
--
--
hdl/sim/spec/data_vectors/memo_test_cmd0.vec deleted 100644 → 0
View file @ 8a92aa76
-------------------------------------------------------------------------------
-- acam_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
-- Initialize the BFM to its default state
init
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
bfm_bar 1 0000000020000000 20000000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d50000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d60000
-------------------------------------------------------------------------------
-- Access the tdc core register space
-------------------------------------------------------------------------------
-- the following writes will go out in a single packet
-- Gonzalo: 3 writings outside of the BAR defined memory space to check that
-- the BFM model does not forward them to the Local bus
wr 0000000040000808 F 0001F04C
wait %d20
wr 0000000040000800 F 00021040
wait %d20
wr 0000000040000800 F 00025000
wait %d60
-- Gonzalo: 3 reads inside Matthieu's core memory space to check that the core
-- does not forward them to the wishbone bus
rd 0000000000000000 F 0000A0A1
wait %d20
rd 0000000000000004 F 0000A0A2
wait %d20
rd 0000000000000008 F 0000A0A3
wait %d60
-- Gonzalo: actual wr and rd on the application memory space for test
wr 0000000000080000 F 00001234
wait %d20
wr 0000000000080004 F 00005678
wait %d20
wr 0000000000080008 F 0000abcd
wait %d20
wr 000000000008000C F 0000ef90
wait %d60
rd 0000000000080000 F 00001234
wait %d20
rd 0000000000080004 F 00005678
wait %d20
rd 0000000000080008 F 0000abcd
wait %d20
rd 000000000008000C F 0000ef90
wait %d60
wr 0000000000080100 F 00000001
wait %d100
wr 0000000000080100 F 00000002
wait %d100
-- Gonzalo: registers inside Matthieu's core memory space are written with the
-- settings for DMA transfer
-- Start address on the carrier local memory
wr 0000000000000008 F 00000000
wait %d20
-- Start addresses on the PCI host memory
wr 000000000000000C F 0000A0A4
wait %d20
wr 0000000000000010 F 0000A0A5
wait %d20
-- Transfer length
wr 0000000000000014 F 00000060
wait %d20
-- Chain control
wr 0000000000000020 F 00000000
wait %d60
-- Start transfer through the Control register and check through the status register
wr 0000000000000000 F 00000001
wait %d100
rd 0000000000000004 F 00000001
wait %d100
hdl/sim/spec/spec_fmc_tdc_sim.xise
View file @ 12d884ea
......@@ -216,10 +216,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../ip_cores/wishbone/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../ip_cores/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
......
hdl/testbench/spec/tb_tdc.vhd
View file @ 12d884ea
......@@ -34,7 +34,8 @@ architecture behavioral of tb_tdc is
);
port(
-- interface with GNUM circuit
rst_n_a_i : in std_logic;
rst_n_a_i : in std_logic;
spec_clk_i : in std_logic;
-- P2L Direction
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
......@@ -394,7 +395,8 @@ begin
)
port map(
-- interface with GNUM circuit
rst_n_a_i => rst_n,
rst_n_a_i => rst_n,
spec_clk_i => spec_clk_i,
p2l_clk_p_i => p2l_clkp,
p2l_clk_n_i => p2l_clkn,
p2l_data_i => p2l_data,
......
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