folders restructuring; one core for both spec and svec

git-svn-id: http://svn.ohwr.org/fmc-tdc@120 85dfdc96-de2c-444c-878d-45b388be74a9

folders restructuring; one core for both spec and svec
git-svn-id: http://svn.ohwr.org/fmc-tdc@120 85dfdc96-de2c-444c-878d-45b388be74a9
13d729a4 · egousiou · a7b11dc6 · 13d729a4 · 13d729a4 · 13d729a4
Commit 13d729a4 authored Oct 02, 2013 by egousiou
33 changed files
--- a/hdl/rtl/acam_databus_interface.vhd
+++ b/hdl/rtl/acam_databus_interface.vhd
--- a/hdl/rtl/acam_timecontrol_interface.vhd
+++ b/hdl/rtl/acam_timecontrol_interface.vhd
--- a/hdl/rtl/circular_buffer.vhd
+++ b/hdl/rtl/circular_buffer.vhd
--- a/hdl/rtl/clks_rsts_manager.vhd
+++ b/hdl/rtl/clks_rsts_manager.vhd
--- a/hdl/rtl/data_engine.vhd
+++ b/hdl/rtl/data_engine.vhd
--- a/hdl/rtl/data_formatting.vhd
+++ b/hdl/rtl/data_formatting.vhd
--- a/hdl/rtl/decr_counter.vhd
+++ b/hdl/rtl/decr_counter.vhd
+--_________________________________________________________________________________________________
+--                                                                                                |
+--                                           |TDC core|                                           |
+--                                                                                                |
+--                                         CERN,BE/CO-HT                                          |
+--________________________________________________________________________________________________|
+
+---------------------------------------------------------------------------------------------------
+--                                                                                                |
+--                                         decr_counter                                           |
+--                                                                                                |
+---------------------------------------------------------------------------------------------------
+-- File         decr_counter.vhd                                                                  |
+--                                                                                                |
+-- Description  Stop counter. Configurable "counter_top_i" and "width".                           |
+--       		"Current count value" and "counting done" signals available.                      |
+--				"Counter done" signal asserted simultaneous to "current count value = 0".         |
+--              Countdown is launched each time "counter_load_i" is asserted for one clock tick.  |
+--                                                                                                |
+--                                                                                                |
+-- Authors      Gonzalo Penacoba  (Gonzalo.Penacoba@cern.ch)                                      |
+--              Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
+-- Date         04/2012                                                                           |
+-- Version      v0.11                                                                             |
+-- Depends on                                                                                     |
+--                                                                                                |
+----------------                                                                                  |
+-- Last changes                                                                                   |
+--     05/2011  v0.1  GP  First version                                                           |
+--     04/2012  v0.11 EG  Revamping; Comments added, signals renamed                              |
+--                                                                                                |
+---------------------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------------------------
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                |
+--                              ------------------------------------                              |
+-- This source file is free software; you can redistribute it and/or modify it under the terms of |
+-- the GNU Lesser General Public License as published by the Free Software Foundation; either     |
+-- version 2.1 of the License, or (at your option) any later version.                             |
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       |
+-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.      |
+-- See the GNU Lesser General Public License for more details.                                    |
+-- You should have received a copy of the GNU Lesser General Public License along with this       |
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     |
+---------------------------------------------------------------------------------------------------
+
+
+
+--=================================================================================================
+--                                       Libraries & Packages
+--=================================================================================================
+
+-- Standard library
+library IEEE;
+use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
+use IEEE.NUMERIC_STD.all;    -- conversion functions
+
+
+--=================================================================================================
+--                            Entity declaration for decr_counter
+--=================================================================================================
+
+entity decr_counter is
+
+  generic
+    (width             : integer := 32);                        -- default size
+  port
+  -- INPUTS
+     -- Signals from the clk_rst_manager
+    (clk_i             : in std_logic;
+     rst_i             : in std_logic;
+
+     -- Signals from any unit
+     counter_load_i    : in std_logic;                          -- loads counter with counter_top_i value
+     counter_top_i     : in std_logic_vector(width-1 downto 0); -- counter start value
+
+
+  -- OUTPUTS
+     -- Signals to any unit
+     counter_o         : out std_logic_vector(width-1 downto 0);
+     counter_is_zero_o : out std_logic);                        -- counter empty indication
+
+end decr_counter;
+
+
+--=================================================================================================
+--                                    architecture declaration
+--=================================================================================================
+
+architecture rtl of decr_counter is
+
+  constant zeroes : unsigned(width-1 downto 0):=(others=>'0');
+  signal one      : unsigned(width-1 downto 0);
+  signal counter  : unsigned(width-1 downto 0) := (others=>'0'); -- init to avoid sim warnings
+
+
+--=================================================================================================
+--                                       architecture begin
+--=================================================================================================
+begin
+	
+  decr_counting: process (clk_i)
+  begin
+    if rising_edge (clk_i) then
+
+      if rst_i = '1' then
+        counter_is_zero_o <= '0';
+        counter           <= zeroes;
+
+      elsif counter_load_i = '1' then
+        counter_is_zero_o <= '0';
+        counter           <= unsigned(counter_top_i) - "1";
+
+      elsif counter = zeroes then
+        counter_is_zero_o <= '0';
+        counter           <= zeroes;
+
+      elsif counter = one then
+        counter_is_zero_o <= '1';
+        counter           <= counter - "1";
+
+      else
+        counter_is_zero_o <= '0';
+        counter           <= counter - "1";
+      end if;
+    end if;
+  end process;
+
+  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+  counter_o   <= std_logic_vector(counter);
+  one         <= zeroes + "1";
+
+
+end architecture rtl;
+--=================================================================================================
+--                                        architecture end
+--=================================================================================================
+---------------------------------------------------------------------------------------------------
+--                                      E N D   O F   F I L E
+---------------------------------------------------------------------------------------------------
\ No newline at end of file
--- a/hdl/rtl/fmc_tdc_core.vhd
+++ b/hdl/rtl/fmc_tdc_core.vhd
--- a/hdl/rtl/fmc_tdc_mezzanine.vhd
+++ b/hdl/rtl/fmc_tdc_mezzanine.vhd
--- a/hdl/rtl/free_counter.vhd
+++ b/hdl/rtl/free_counter.vhd
+--_________________________________________________________________________________________________
+--                                                                                                |
+--                                           |TDC core|                                           |
+--                                                                                                |
+--                                         CERN,BE/CO-HT                                          |
+--________________________________________________________________________________________________|
+
+---------------------------------------------------------------------------------------------------
+--                                                                                                |
+--                                         free_counter                                           |
+--                                                                                                |
+---------------------------------------------------------------------------------------------------
+-- File         free_counter.vhd                                                                  |
+--                                                                                                |
+-- Description  Free running counter. Configurable "counter_top_i" and "width".                   |
+--				"Current count value" and "counting done" signal available.                       |
+--				"Counting done" signal asserted simultaneous to "current count value = 0".        |
+--                                                                                                |
+--                                                                                                |
+-- Authors      Gonzalo Penacoba  (Gonzalo.Penacoba@cern.ch)                                      |
+--              Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
+-- Date         04/2012                                                                           |
+-- Version      v0.11                                                                             |
+-- Depends on                                                                                     |
+--                                                                                                |
+----------------                                                                                  |
+-- Last changes                                                                                   |
+--     05/2011  v0.1  GP  First version                                                           |
+--     04/2012  v0.11 EG  Revamping; Comments added, signals renamed                              |
+--                                                                                                |
+---------------------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------------------------
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                |
+--                              ------------------------------------                              |
+-- This source file is free software; you can redistribute it and/or modify it under the terms of |
+-- the GNU Lesser General Public License as published by the Free Software Foundation; either     |
+-- version 2.1 of the License, or (at your option) any later version.                             |
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       |
+-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.      |
+-- See the GNU Lesser General Public License for more details.                                    |
+-- You should have received a copy of the GNU Lesser General Public License along with this       |
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     |
+---------------------------------------------------------------------------------------------------
+
+
+
+--=================================================================================================
+--                                       Libraries & Packages
+--=================================================================================================
+
+-- Standard library
+library IEEE;
+use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
+use IEEE.NUMERIC_STD.all;    -- conversion functions
+
+
+--=================================================================================================
+--                            Entity declaration for free_counter
+--=================================================================================================
+
+entity free_counter is
+  generic
+    (width             : integer := 32);                        -- default size
+  port
+  -- INPUTS
+     -- Signals from the clk_rst_manager
+    (clk_i             : in std_logic;
+     rst_i             : in std_logic;
+
+     -- Signals from any unit
+     counter_en_i      : in std_logic;                          -- enables counting
+     counter_top_i     : in std_logic_vector(width-1 downto 0); -- start value;
+                                                                -- when zero is reached counter reloads
+                                                                -- start value and restarts counting
+  -- OUTPUTS
+     -- Signals to any unit
+     counter_o         : out std_logic_vector(width-1 downto 0);
+     counter_is_zero_o : out std_logic);                        -- empty counter indication
+
+end free_counter;
+
+
+--=================================================================================================
+--                                    architecture declaration
+--=================================================================================================
+architecture rtl of free_counter is
+
+  constant zeroes : unsigned(width-1 downto 0):=(others=>'0');
+  signal counter  : unsigned(width-1 downto 0):=(others=>'0'); -- init to avoid sim warnings
+
+
+--=================================================================================================
+--                                       architecture begin
+--=================================================================================================
+begin
+	
+  decr_counting: process (clk_i)
+  begin
+    if rising_edge (clk_i) then
+      if rst_i = '1' then
+        counter_is_zero_o   <= '0';
+        counter             <= unsigned(counter_top_i) - "1";
+
+      elsif counter = zeroes then
+        counter_is_zero_o   <= '0';
+        counter             <= unsigned(counter_top_i) - "1";
+
+      elsif counter_en_i = '1' then
+        if counter = zeroes + "1" then
+          counter_is_zero_o <= '1';
+          counter           <= counter - "1";
+        else
+          counter_is_zero_o <= '0';
+          counter           <= counter - "1";
+        end if;
+
+      end if;
+    end if;
+  end process;
+
+  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+  counter_o                 <= std_logic_vector(counter);
+
+
+end architecture rtl;
+--=================================================================================================
+--                                        architecture end
+--=================================================================================================
+---------------------------------------------------------------------------------------------------
+--                                      E N D   O F   F I L E
+---------------------------------------------------------------------------------------------------
--- a/hdl/rtl/incr_counter.vhd
+++ b/hdl/rtl/incr_counter.vhd
+--_________________________________________________________________________________________________
+--                                                                                                |
+--                                           |TDC core|                                           |
+--                                                                                                |
+--                                         CERN,BE/CO-HT                                          |
+--________________________________________________________________________________________________|
+
+---------------------------------------------------------------------------------------------------
+--                                                                                                |
+--                                         incr_counter                                           |
+--                                                                                                |
+---------------------------------------------------------------------------------------------------
+-- File         incr_counter.vhd                                                                  |
+--                                                                                                |
+-- Description  Stop counter. Configurable "counter_top_i" and "width".                           |
+--				"Current count value" and "counting done" signals available.                      |
+--				"Counting done" signal asserted simultaneous to"current count value=counter_top_i"|
+--				Needs a rst_i to restart.                                                         |
+--                                                                                                |
+--                                                                                                |
+-- Authors      Gonzalo Penacoba  (Gonzalo.Penacoba@cern.ch)                                      |
+--              Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
+-- Date         04/2012                                                                           |
+-- Version      v0.11                                                                             |
+-- Depends on                                                                                     |
+--                                                                                                |
+----------------                                                                                  |
+-- Last changes                                                                                   |
+--     05/2011  v0.1  GP  First version                                                           |
+--     04/2012  v0.11 EG  Revamping; Comments added, signals renamed                              |
+--                                                                                                |
+---------------------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------------------------
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                |
+--                              ------------------------------------                              |
+-- This source file is free software; you can redistribute it and/or modify it under the terms of |
+-- the GNU Lesser General Public License as published by the Free Software Foundation; either     |
+-- version 2.1 of the License, or (at your option) any later version.                             |
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       |
+-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.      |
+-- See the GNU Lesser General Public License for more details.                                    |
+-- You should have received a copy of the GNU Lesser General Public License along with this       |
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     |
+---------------------------------------------------------------------------------------------------
+
+
+
+--=================================================================================================
+--                                       Libraries & Packages
+--=================================================================================================
+
+-- Standard library
+library IEEE;
+use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
+use IEEE.NUMERIC_STD.all;    -- conversion functions
+
+
+--=================================================================================================
+--                            Entity declaration for incr_counter
+--=================================================================================================
+
+entity incr_counter is
+  generic
+    (width             : integer := 32);                        -- default size
+  port
+  -- INPUTS
+     -- Signals from the clk_rst_manager
+    (clk_i             : in std_logic;
+     rst_i             : in std_logic;
+
+     -- Signals from any unit
+     counter_top_i     : in std_logic_vector(width-1 downto 0); -- max value to be counted; when reached
+                                                                -- counter stays at it, until a reset
+     counter_incr_en_i : in std_logic;                          -- enables counting
+
+  -- OUTPUTS
+     -- Signals to any unit
+     counter_o         : out std_logic_vector(width-1 downto 0);
+     counter_is_full_o : out std_logic);                        -- counter reahed counter_top_i value
+
+  end incr_counter;
+
+--=================================================================================================
+--                                    architecture declaration
+--=================================================================================================
+architecture rtl of incr_counter is
+
+  constant zeroes : unsigned(width-1 downto 0) := (others=>'0');
+  signal counter  : unsigned(width-1 downto 0) := (others=>'0'); -- init to avoid sim warnings
+
+
+--=================================================================================================
+--                                       architecture begin
+--=================================================================================================
+begin
+	
+  incr_counting: process (clk_i)
+  begin
+    if rising_edge (clk_i) then
+      if rst_i = '1' then
+        counter_is_full_o   <= '0';
+        counter             <= zeroes;
+
+      elsif counter = unsigned (counter_top_i) then
+        counter_is_full_o   <= '1';
+        counter             <= unsigned (counter_top_i);
+
+      elsif counter_incr_en_i ='1' then
+
+        if counter = unsigned(counter_top_i) - "1" then
+          counter_is_full_o <= '1';
+          counter           <= counter + "1";
+        else
+          counter_is_full_o <= '0';
+          counter           <= counter + "1";
+        end if;
+
+      end if;
+    end if;
+  end process;
+
+  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+  counter_o                 <= std_logic_vector(counter);
+
+
+end architecture rtl;
+--=================================================================================================
+--                                        architecture end
+--=================================================================================================
+---------------------------------------------------------------------------------------------------
+--                                      E N D   O F   F I L E
+---------------------------------------------------------------------------------------------------
--- a/hdl/rtl/irq_generator.vhd
+++ b/hdl/rtl/irq_generator.vhd
--- a/hdl/rtl/leds_manager.vhd
+++ b/hdl/rtl/leds_manager.vhd
--- a/hdl/rtl/one_hz_gen.vhd
+++ b/hdl/rtl/one_hz_gen.vhd
--- a/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/rtl/reg_ctrl.vhd
--- a/hdl/rtl/start_retrig_ctrl.vhd
+++ b/hdl/rtl/start_retrig_ctrl.vhd
--- a/hdl/scripts/fmc-tdc-v3.pins
+++ b/hdl/scripts/fmc-tdc-v3.pins
--- a/hdl/scripts/spec.pins
+++ b/hdl/scripts/spec.pins
--- a/hdl/scripts/svec.pins
+++ b/hdl/scripts/svec.pins
--- a/hdl/scripts/ucfgen.py
+++ b/hdl/scripts/ucfgen.py
--- a/hdl/top/spec/sdb_meta_pkg.vhd
+++ b/hdl/top/spec/sdb_meta_pkg.vhd
--- a/hdl/top/spec/tdc_core_pkg.vhd
+++ b/hdl/top/spec/tdc_core_pkg.vhd
--- a/hdl/top/spec/top_tdc.vhd
+++ b/hdl/top/spec/top_tdc.vhd
--- a/hdl/top/spec/wb_irq_controller/irq_controller.vhd
+++ b/hdl/top/spec/wb_irq_controller/irq_controller.vhd
--- a/hdl/top/spec/wb_irq_controller/irq_controller_regs.vhd
+++ b/hdl/top/spec/wb_irq_controller/irq_controller_regs.vhd
--- a/hdl/top/svec/carrier_csr.vhd
+++ b/hdl/top/svec/carrier_csr.vhd
--- a/hdl/top/svec/sdb_meta_pkg.vhd
+++ b/hdl/top/svec/sdb_meta_pkg.vhd
--- a/hdl/top/svec/svec_tdc.ucf
+++ b/hdl/top/svec/svec_tdc.ucf
--- a/hdl/top/svec/tdc_core_pkg.vhd
+++ b/hdl/top/svec/tdc_core_pkg.vhd
--- a/hdl/top/svec/top_tdc.vhd
+++ b/hdl/top/svec/top_tdc.vhd
--- a/hdl/top/svec/wb_irq_controller/irq_controller.vhd
+++ b/hdl/top/svec/wb_irq_controller/irq_controller.vhd
--- a/hdl/top/svec/wb_irq_controller/irq_controller_regs.vhd
+++ b/hdl/top/svec/wb_irq_controller/irq_controller_regs.vhd
--- a/hdl/top/svec/xvme64x_core.vhd
+++ b/hdl/top/svec/xvme64x_core.vhd