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F
FMC TDC 1ns 5cha - Gateware
Commit 2d2d830b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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merged optimizations

parents 489536a5 aee4cec7
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Showing with 117 additions and 80 deletions
hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 2d2d830b
......@@ -529,12 +529,12 @@ begin
slave_i => cnx_master_out(c_WB_SLAVE_TDC_I2C),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_I2C),
desc_o => open,
scl_pad_i => i2c_scl_i,
scl_pad_o => sys_scl_out,
scl_padoen_o => sys_scl_oe_n,
sda_pad_i => i2c_sda_i,
sda_pad_o => sys_sda_out,
sda_padoen_o => sys_sda_oe_n);
scl_pad_i(0) => i2c_scl_i,
scl_pad_o(0) => sys_scl_out,
scl_padoen_o(0) => sys_scl_oe_n,
sda_pad_i(0) => i2c_sda_i,
sda_pad_o(0) => sys_sda_out,
sda_padoen_o(0) => sys_sda_oe_n);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
i2c_sda_oen_o <= sys_sda_oe_n;
......@@ -546,4 +546,4 @@ begin
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
\ No newline at end of file
----------------------------------------------------------------------------------------------------
hdl/wr_spec_tdc/hdl/rtl/reg_ctrl.vhd
View file @ 2d2d830b
This diff is collapsed.
hdl/wr_spec_tdc/hdl/top/spec/fmc_tdc_direct_readout.vhd
View file @ 2d2d830b
......@@ -67,9 +67,12 @@ architecture rtl of fmc_tdc_direct_readout is
signal ts_bins : std_logic_vector(17 downto 0);
signal ts_edge : std_logic;
signal ts_channel : std_logic_vector(2 downto 0);
signal direct_slave_out: t_wishbone_slave_out;
begin
ts_channel <= direct_timestamp_i(98 downto 96);
ts_edge <= direct_timestamp_i(100);
ts_seconds <= direct_timestamp_i(95 downto 64);
......@@ -82,19 +85,21 @@ begin
clk_sys_i => clk_sys_i,
wb_adr_i => direct_slave_i.adr(4 downto 2),
wb_dat_i => direct_slave_i.dat,
wb_dat_o => direct_slave_o.dat,
wb_dat_o => direct_slave_out.dat,
wb_cyc_i => direct_slave_i.cyc,
wb_sel_i => direct_slave_i.sel,
wb_stb_i => direct_slave_i.stb,
wb_we_i => direct_slave_i.we,
wb_ack_o => direct_slave_o.ack,
wb_stall_o => direct_slave_o.stall,
wb_ack_o => direct_slave_out.ack,
wb_stall_o => direct_slave_out.stall,
clk_tdc_i => clk_tdc_i,
regs_i => regs_in,
regs_o => regs_out);
direct_slave_o.err <= '0';
direct_slave_o.rty <= '0';
direct_slave_out.err <= '0';
direct_slave_out.rty <= '0';
direct_slave_o <= direct_slave_out;
regs_in.fifo_cycles_i <= ts_cycles;
regs_in.fifo_edge_i <= '1';
......@@ -102,6 +107,7 @@ begin
regs_in.fifo_channel_i <= '0'&ts_channel;
regs_in.fifo_bins_i <= ts_bins;
gen_channels : for i in 0 to c_num_channels-1 generate
p_dead_time : process (clk_tdc_i)
......@@ -139,8 +145,12 @@ begin
if rst_tdc_n_i = '0' then
regs_in.fifo_wr_req_i <= '0';
else
regs_in.fifo_wr_req_i <= '0';
for i in 0 to c_num_channels-1 loop
regs_in.fifo_wr_req_i <= c(i).fifo_wr and not regs_out.fifo_wr_full_o;
if(c(i).fifo_wr = '1' and regs_out.fifo_wr_full_o = '0') then
regs_in.fifo_wr_req_i <= '1';
end if;
end loop;
end if;
end if;
......@@ -148,3 +158,4 @@ begin
end rtl;
hdl/wr_spec_tdc/hdl/top/spec/fmc_tdc_wrapper.vhd
View file @ 2d2d830b
......@@ -214,7 +214,9 @@ entity fmc_tdc_wrapper is
direct_slave_i : in t_wishbone_slave_in;
direct_slave_o : out t_wishbone_slave_out;
irq_o : out std_logic
irq_o : out std_logic;
clk_125m_tdc_o: out std_logic
); -- Mezzanine presence (active low)
end fmc_tdc_wrapper;
......@@ -289,6 +291,7 @@ begin
pll_sdi_o <= pll_sdi;
pll_sclk_o <= pll_sclk;
clk_125m_tdc_o <= clk_125m_mezz;
---------------------------------------------------------------------------------------------------
-- TDC BOARD --
---------------------------------------------------------------------------------------------------
......
hdl/wr_spec_tdc/hdl/top/spec/tdc_core_pkg.vhd
View file @ 2d2d830b
......@@ -1070,7 +1070,8 @@ package tdc_core_pkg is
direct_slave_i : in t_wishbone_slave_in;
direct_slave_o : out t_wishbone_slave_out;
irq_o : out std_logic);
irq_o : out std_logic;
clk_125m_tdc_o: out std_logic);
end component fmc_tdc_wrapper;
component fmc_tdc_direct_readout is
......
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