Comments added on the VHDL code

git-svn-id: http://svn.ohwr.org/fmc-tdc@66 85dfdc96-de2c-444c-878d-45b388be74a9

Comments added on the VHDL code
git-svn-id: http://svn.ohwr.org/fmc-tdc@66 85dfdc96-de2c-444c-878d-45b388be74a9
49fc1bea · penacoba · 10895a83 · 49fc1bea · 49fc1bea · 49fc1bea
Commit 49fc1bea authored Nov 08, 2011 by penacoba
6 changed files
--- a/hdl/spec/src/rtl/acam_databus_interface.vhd
+++ b/hdl/spec/src/rtl/acam_databus_interface.vhd
@@ -98,7 +98,10 @@ signal ack                      : std_logic;
 --  architecture begins
 ----------------------------------------------------------------------------------------------------
 begin
+    -- the following state machine implements the slave side of the Wishbone interface
+    -- and converts the signals for the Acam proprietary bus interface
    databus_access_seq_fsm: process
    begin
        if reset ='1' then
@@ -195,7 +198,11 @@ begin
    cs          <= ((stb and cyc)               or cs_extend) and not(ack);
    rd          <= ((stb and cyc and not(we))   or rd_extend) and not(ack);
-    wr          <= ((stb and cyc and we)        or wr_extend) and not(wr_remove) and not(ack);
+    wr          <= ((stb and cyc and we)        or wr_extend) and not(wr_remove) and not(ack);      -- the wr signal
+                                                                                                    -- has to be
+                                                                                                    -- removed to 
+                                                                                                    -- respect the
+                                                                                                    -- Acam specs
    -- inputs from other blocks    
    clk                         <= clk_i;

--- a/hdl/spec/src/rtl/acam_timecontrol_interface.vhd
+++ b/hdl/spec/src/rtl/acam_timecontrol_interface.vhd
@@ -183,6 +183,10 @@ begin
    -- After many tests with the ACAM chip, the Start Disable feature
    -- doesn't seem to be stable. It has therefore been decided to
    -- avoid its usage.
+    -- The generation of the window is maintained to allow the for
+    -- the control of the delay between the Start_From_FPGA pulse
+    -- and the Reference Clock edge
 --    start_disable_control: process
 --    begin

--- a/hdl/spec/src/rtl/circular_buffer.vhd
+++ b/hdl/spec/src/rtl/circular_buffer.vhd
@@ -6,7 +6,7 @@
 --  author      : G. Penacoba
 --  date        : Oct 2011
 --  version     : Revision 1
--  description : contains the RAM block (512 x 32) and the wishbone slave interfaces.
+--  description : contains the RAM block (1024 x 32) and the wishbone slave interfaces.
 --                From the side of the timestamps coming from the ACAM the wishbone interface is
 --                classic. On the side of the DMA access from the PCI, the wishbone interface is
 --                pipelined.

--- a/hdl/spec/src/rtl/clk_rst_managr.vhd
+++ b/hdl/spec/src/rtl/clk_rst_managr.vhd
@@ -167,7 +167,8 @@ constant reg_232        : t_byte:=x"01";
 constant sim_reset      : std_logic_vector(31 downto 0):=x"00000400";
 constant syn_reset      : std_logic_vector(31 downto 0):=x"00004E20";
+-- this value may still need adjustment according to the dispersion
+-- in the performance of the PLL observed during the production tests
 signal pll_init_st              : t_pll_init_st;
 signal nxt_pll_init_st          : t_pll_init_st;
@@ -246,6 +247,13 @@ begin
 --    );
    acam_refclk     <= acam_refclk_i;
+    -- The following processes generate a general internal reset signal for the whole core.
+    -- This internal reset is triggered by the reset signal coming from the GNUM chip.
+    -- The idea is to keep the internal reset asserted until the clock signal received
+    -- from the PLL is stable enough.
+    --
+    -- The way to evaluate that is to count a minimum number of edges on the 125 MHz clock
    general_poreset: incr_counter
    port map(
        clk                 => spec_clk,
@@ -259,8 +267,11 @@ begin
    gral_reset_duration          <= sim_reset when values_for_simulation
                                    else syn_reset;
+    -- the number of edges will probably need to be better adjusted
+    -- depending on the actual performances of the PLL
-    silly: process
+    silly: process      -- this signal only exists to reset the sampling of the 125 MHz 
+                        -- edges
    begin
        if gnum_reset ='1' then
            silly_altern        <= '0';

--- a/hdl/spec/src/rtl/one_hz_gen.vhd
+++ b/hdl/spec/src/rtl/one_hz_gen.vhd
@@ -8,6 +8,7 @@
 --  version     : Revision 1
 --  description : generates one pulse every second synchronously with the acam reference clock.
 --                  The phase with the reference clock can be adjusted.
+--                  It also keeps track of the UTC time based on the local clock
 --  dependencies:
 --  references  :
 --  modified by :

--- a/hdl/spec/src/rtl/start_retrigger_control.vhd
+++ b/hdl/spec/src/rtl/start_retrigger_control.vhd
@@ -121,20 +121,6 @@ begin
        current_value   => current_cycles
    );
--    retrig_number_counter: free_counter
--    generic map(
--        width           => g_width
--    )
--    port map(
--        clk             => clk,
--        enable          => retrig_p,
--        reset           => retrig_nb_reset,
--        start_value     => x"00000100",
--        
--        count_done      => open,
--        current_value   => current_retrig_nb
--    );
    retrig_nb_counter: incr_counter
    generic map(
        width           => g_width
@@ -148,6 +134,8 @@ begin
        count_done      => open,
        current_value   => current_retrig_nb
    );
+    -- These two counters keep a track of the current internal start retrigger
+    -- of the Acam in parallel with the Acam itself
    roll_over_counter: incr_counter
    generic map(
@@ -162,6 +150,8 @@ begin
        count_done      => open,
        current_value   => roll_over_value
    );
+    -- This counter keeps track of the number of overflows of the Acam counter
+    -- for the internal start retrigger
    capture_offset: process
    begin
@@ -174,6 +164,9 @@ begin
        end if;
        wait until clk ='1';
    end process;
+    -- When a new second starts, all values are captured and stored as offsets.
+    -- when a timestamps arrives, these offset will be subrstracted in order
+    -- to base the final timestamp with respect to the current second.
    retrig_period_reset             <= acam_fall_intflag_p;
    retrig_nb_reset                 <= acam_fall_intflag_p;
@@ -193,24 +186,6 @@ begin
    retrig_nb_offset_o          <= retrig_nb_offset;
    current_roll_over_o         <= roll_over_value;
--    halfcounter_monitor: process                    -- The halfcounter monitor is needed to make
--    begin                                           -- sure that the falling edge pulse received 
--        if reset ='1' or one_hz_p ='1' then         -- corresponds to a real overflow of the ACAM
--            acam_halfcounter_gone       <= '0';     -- counter and not to a different reason,
--        elsif acam_rise_intflag_p ='1' then         -- for example a reset. 
--            acam_halfcounter_gone       <= '1';     -- This way the start_nb_offset will really 
--        elsif acam_fall_intflag_p ='1' then         -- track the number of internal start retriggers
--            acam_halfcounter_gone       <= '0';     -- inside the ACAM.
--        end if;
--        wait until clk ='1';
--    end process;
--    
--    add_offset          <= acam_fall_intflag_p and acam_halfcounter_gone;
--    counter_reset       <= reset or one_hz_p;
--    offset_to_shift     <= unsigned(offset_value);
--    start_nb_offset     <= std_logic_vector(shift_left(offset_to_shift,8));
--    start_trig          <= one_hz_p;
 end rtl;
 ----------------------------------------------------------------------------------------------------
 --  architecture ends