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FMC TDC 1ns 5cha - Gateware
Commit 4a2e47ff authored by egousiou's avatar egousiou
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ip_cores added some missing files:-/ 

git-svn-id: http://svn.ohwr.org/fmc-tdc@183 85dfdc96-de2c-444c-878d-45b388be74a9
parent 11dd82b0
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hdl/ip_cores/gnum_core/l2p_dma_master.vhd
View file @ 4a2e47ff
......@@ -81,6 +81,7 @@ entity l2p_dma_master is
l2p_edb_o : out std_logic; -- Asserted when transfer is aborted
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Asserted when GN4124 is ready to receive master write
l2p_rdy_i : in std_logic; -- De-asserted to pause transfer already in progress
tx_error_i : in std_logic; -- Asserted when unexpected or malformed packet recevied
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
......@@ -407,7 +408,7 @@ begin
ldm_arb_valid_o <= '0';
end if;
if (dma_ctrl_abort_i = '1') then
if (dma_ctrl_abort_i = '1' or tx_error_i = '1') then
l2p_edb_o <= '1';
l2p_dma_current_state <= L2P_IDLE;
elsif (l2p_rdy_i = '0') then
......
hdl/ip_cores/gnum_core/wbmaster32.vhd
View file @ 4a2e47ff
......@@ -43,7 +43,6 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.gn4124_core_pkg.all;
use work.genram_pkg.all;
......
hdl/ip_cores/gnum_core/xilinx_cores/coregen.cgc deleted 100644 → 0
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hdl/ip_cores/gnum_core/xilinx_cores/coregen.cgp deleted 100644 → 0
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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET package = fgg484
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.gise deleted 100644 → 0
View file @ 11dd82b0
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_32x512.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_32x512.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="fifo_32x512.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_32x512.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo_32x512.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1391772794" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8777296749647723518" xil_pn:start_ts="1391772794">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1391772794" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="2104667735123416897" xil_pn:start_ts="1391772794">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1391772794" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1391772794">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1391772794" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1627810207069309888" xil_pn:start_ts="1391772794">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ndf deleted 100644 → 0
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hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc deleted 100644 → 0
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hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd deleted 100644 → 0
View file @ 11dd82b0
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_32x512.vhd when simulating
-- the core, fifo_32x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_32x512 IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
END fifo_32x512;
ARCHITECTURE fifo_32x512_a OF fifo_32x512 IS
-- synthesis translate_off
component wrapped_fifo_32x512
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_32x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 32,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan6",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 32,
c_msgon_val => 1,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 508,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 509,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 4,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_32x512
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full);
-- synthesis translate_on
END fifo_32x512_a;
hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vho deleted 100644 → 0
View file @ 11dd82b0
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component fifo_32x512
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_32x512: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : fifo_32x512
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file fifo_32x512.vhd when simulating
-- the core, fifo_32x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.xco deleted 100644 → 0
View file @ 11dd82b0
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Thu Feb 3 16:40:52 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=fifo_32x512
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=509
CSET full_threshold_negate_value=508
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=32
CSET input_depth=512
CSET output_data_width=32
CSET output_depth=512
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=Multiple_Programmable_Full_Threshold_Input_Ports
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=9
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=true
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=9
# END Parameters
GENERATE
# CRC: adce0ad2
hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.xise deleted 100644 → 0
View file @ 11dd82b0
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="fifo_32x512.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="fifo_32x512.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="fifo_32x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|fifo_32x512|fifo_32x512_a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="fifo_32x512.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_32x512" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_32x512" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-02-03T17:40:59" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7848BC49ECBEC697042292BDA767D393" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.gise deleted 100644 → 0
View file @ 11dd82b0
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_64x512.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_64x512.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="fifo_64x512.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_64x512.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo_64x512.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1391772794" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-5972887507274424632" xil_pn:start_ts="1391772794">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1391772794" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6973896807994015797" xil_pn:start_ts="1391772794">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1391772794" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1391772794">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1391772794" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5324370023856713354" xil_pn:start_ts="1391772794">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ndf deleted 100644 → 0
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hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc deleted 100644 → 0
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hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd deleted 100644 → 0
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_64x512.vhd when simulating
-- the core, fifo_64x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_64x512 IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(63 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
END fifo_64x512;
ARCHITECTURE fifo_64x512_a OF fifo_64x512 IS
-- synthesis translate_off
component wrapped_fifo_64x512
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(63 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_64x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 64,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan6",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 64,
c_msgon_val => 1,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 508,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 509,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x72",
c_count_type => 0,
c_prog_full_type => 4,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_64x512
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full);
-- synthesis translate_on
END fifo_64x512_a;
hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vho deleted 100644 → 0
View file @ 11dd82b0
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component fifo_64x512
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(63 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_64x512: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : fifo_64x512
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file fifo_64x512.vhd when simulating
-- the core, fifo_64x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.xco deleted 100644 → 0
View file @ 11dd82b0
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Thu Feb 3 16:45:57 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=fifo_64x512
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=509
CSET full_threshold_negate_value=508
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=64
CSET input_depth=512
CSET output_data_width=64
CSET output_depth=512
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=Multiple_Programmable_Full_Threshold_Input_Ports
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=9
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=true
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=9
# END Parameters
GENERATE
# CRC: d8162d61
hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.xise deleted 100644 → 0
View file @ 11dd82b0
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="fifo_64x512.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="fifo_64x512.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="fifo_64x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|fifo_64x512|fifo_64x512_a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="fifo_64x512.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_64x512" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_64x512" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-02-03T17:46:02" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="854009E4CFB5E321F7E82E7B56A5D782" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/ip_cores/gnum_core/xilinx_cores/generic_async_fifo_wrapper.vhd deleted 100644 → 0
View file @ 11dd82b0
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Generic asynchronous FIFO wrapper
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: generic_async_fifo (generic_async_fifo_wrapper.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 05-12-2011
--
-- version: 1.0
--
-- description: Wrapper to use Xilinx Coregen FIFOs instead of generic FIFOs
-- from Generics RAMs and FIFOs collection.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library XilinxCoreLib;
use work.gn4124_core_pkg.all;
entity generic_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_rd_empty : boolean := true; -- with empty flag
g_with_rd_full : boolean := false; -- with full flag
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; -- with words counter
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
-- write port
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0);
-- read port
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0)
);
end generic_async_fifo;
architecture syn of generic_async_fifo is
component fifo_32x512
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(8 downto 0);
prog_full_thresh_negate : in std_logic_vector(8 downto 0);
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic;
prog_full : out std_logic);
end component fifo_32x512;
component fifo_64x512
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(8 downto 0);
prog_full_thresh_negate : in std_logic_vector(8 downto 0);
dout : out std_logic_vector(63 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic;
prog_full : out std_logic);
end component fifo_64x512;
signal rst : std_logic;
begin
-- Active high reset for FIFOs
rst <= not(rst_n_i);
-- Assign unused outputs
wr_empty_o <= '0';
wr_almost_empty_o <= '0';
wr_count_o <= (others => '0');
rd_full_o <= '0';
rd_almost_full_o <= '0';
rd_almost_empty_o <= '0';
rd_count_o <= (others => '0');
gen_fifo_32bit : if g_data_width = 32 generate
cmp_fifo_32x512 : fifo_32x512
port map (
rst => rst,
wr_clk => clk_wr_i,
rd_clk => clk_rd_i,
din => d_i,
wr_en => we_i,
rd_en => rd_i,
prog_full_thresh_assert => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
dout => q_o,
full => wr_full_o,
empty => rd_empty_o,
valid => open,
prog_full => wr_almost_full_o);
end generate gen_fifo_32bit;
gen_fifo_64bit : if g_data_width = 64 generate
cmp_fifo_64x512 : fifo_64x512
port map (
rst => rst,
wr_clk => clk_wr_i,
rd_clk => clk_rd_i,
din => d_i,
wr_en => we_i,
rd_en => rd_i,
prog_full_thresh_assert => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
dout => q_o,
full => wr_full_o,
empty => rd_empty_o,
valid => open,
prog_full => wr_almost_full_o);
end generate gen_fifo_64bit;
end syn;
hdl/ip_cores/gnum_core/xilinx_cores/ngc2edif.log deleted 100644 → 0
View file @ 11dd82b0
Release 13.2 - ngc2edif O.61xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Reading design fifo_64x512.ngc ...
WARNING:NetListWriters:298 - No output is written to fifo_64x512.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file fifo_64x512.ndf ...
ngc2edif: Total memory usage is 36440 kilobytes
hdl/ip_cores/platform/Manifest.py 0 → 100644
View file @ 4a2e47ff
if target=="altera":
modules = {"local" : "altera"}
elif target=="xilinx":
modules = {"local" : "xilinx"}
\ No newline at end of file
hdl/ip_cores/platform/altera/Manifest.py 0 → 100644
View file @ 4a2e47ff
modules = { "local" : [
"wb_pcie",
"flash",
"networks",
]}
hdl/ip_cores/platform/altera/flash/Manifest.py 0 → 100644
View file @ 4a2e47ff
files = [
"altera_spi.vhd",
"flash_top.vhd",
"altera_flash_pkg.vhd",
]
hdl/ip_cores/platform/altera/flash/altera_flash_pkg.vhd 0 → 100644
View file @ 4a2e47ff
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
package altera_flash_pkg is
component flash_top is
generic(
-- Sadly, all of this shit must be tuned by hand
g_family : string;
g_port_width : natural := 1;
g_addr_width : natural := 24;
g_dummy_time : natural := 8;
g_config : boolean := false;
g_input_latch_edge : std_logic;
g_output_latch_edge : std_logic;
g_input_to_output_cycles : natural);
port(
-- Wishbone interface
clk_i : in std_logic;
rstn_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- Clock lines for flash chip (might need phase offsets)
clk_ext_i : in std_logic; -- fed off-chip
clk_out_i : in std_logic; -- output registers latch to this
clk_in_i : in std_logic); -- input registers latch to this
end component;
end altera_flash_pkg;
hdl/ip_cores/platform/altera/flash/altera_spi.vhd 0 → 100644
View file @ 4a2e47ff
library ieee;
use ieee.std_logic_1164.all;
-- A wrapper for undocumented Altera SPI interface pins
entity altera_spi is
generic(
g_family : string := "none";
g_port_width : natural := 1);
port(
dclk_i : in std_logic;
ncs_i : in std_logic;
oe_i : in std_logic_vector(g_port_width-1 downto 0);
asdo_i : in std_logic_vector(g_port_width-1 downto 0);
data_o : out std_logic_vector(g_port_width-1 downto 0));
end entity;
architecture rtl of altera_spi is
-- Undocumented Altera ASMI interface components:
component cyclone_asmiblock
port(
dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
data0out : out std_logic;
oe : in std_logic);
end component;
component cycloneii_asmiblock
port(
dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
data0out : out std_logic;
oe : in std_logic);
end component;
component cyclonev_asmiblock
port(
dclk : in std_logic;
sce : in std_logic;
oe : in std_logic;
data0out : in std_logic;
data1out : in std_logic;
data2out : in std_logic;
data3out : in std_logic;
data0oe : in std_logic;
data1oe : in std_logic;
data2oe : in std_logic;
data3oe : in std_logic;
data0in : out std_logic;
data1in : out std_logic;
data2in : out std_logic;
data3in : out std_logic);
end component;
component stratixii_asmiblock
port(
dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
data0out : out std_logic;
oe : in std_logic);
end component;
component stratixiii_asmiblock
port(
dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
data0out : out std_logic;
oe : in std_logic);
end component;
component stratixiv_asmiblock
port(
dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
data0out : out std_logic;
oe : in std_logic);
end component;
component stratixv_asmiblock
port(
dclk : in std_logic;
sce : in std_logic;
oe : in std_logic;
data0out : in std_logic;
data1out : in std_logic;
data2out : in std_logic;
data3out : in std_logic;
data0oe : in std_logic;
data1oe : in std_logic;
data2oe : in std_logic;
data3oe : in std_logic;
data0in : out std_logic;
data1in : out std_logic;
data2in : out std_logic;
data3in : out std_logic);
end component;
component arriav_asmiblock
port(
dclk : in std_logic;
sce : in std_logic;
oe : in std_logic;
data0out : in std_logic;
data1out : in std_logic;
data2out : in std_logic;
data3out : in std_logic;
data0oe : in std_logic;
data1oe : in std_logic;
data2oe : in std_logic;
data3oe : in std_logic;
data0in : out std_logic;
data1in : out std_logic;
data2in : out std_logic;
data3in : out std_logic);
end component;
type t_block is (T_CYCLONE, T_CYCLONEII, T_CYCLONEV,
T_STRATIXII, T_STRATIXIII, T_STRATIXIV, T_STRATIXV,
T_ARRIAV,
T_UNKNOWN);
function f_block(family : string) return t_block is
variable identifier : string(1 to 15) := (others => ' ');
begin
identifier(family'range) := family;
case identifier is
when "Cyclone " => return T_CYCLONE;
when "Cyclone II " => return T_CYCLONEII;
when "Cyclone III " => return T_CYCLONEII;
when "Cyclone III LS " => return T_CYCLONEII;
when "Cyclone IV E " => return T_CYCLONEII;
when "Cyclone IV GX " => return T_CYCLONEII;
when "Cyclone V " => return T_CYCLONEV;
when "Stratix II " => return T_STRATIXII;
when "Stratix II GX " => return T_STRATIXII;
when "Arria GX " => return T_STRATIXII;
when "Stratix III " => return T_STRATIXIII;
when "Stratix IV " => return T_STRATIXIV;
when "Arria II GX " => return T_STRATIXIV;
when "Arria II GZ " => return T_STRATIXIV;
when "Stratix V " => return T_STRATIXV;
when "Arria V " => return T_ARRIAV;
when others => return T_UNKNOWN;
end case;
end f_block;
function f_support4(x : t_block) return boolean is
begin
case x is
when T_ARRIAV => return true;
when T_CYCLONEV => return true;
when T_STRATIXV => return true;
when others => return false;
end case;
end f_support4;
constant c_block : t_block := f_block(g_family);
constant c_support4 : boolean := f_support4(c_block);
signal oe : std_logic_vector(3 downto 0);
signal asdo : std_logic_vector(3 downto 0);
signal data : std_logic_vector(3 downto 0);
-- attribute altera_attribute : string;
-- attribute altera_attribute of rtl: architecture is "SUPPRESS_DA_RULE_INTERNAL=C104";
begin
assert (c_block /= T_UNKNOWN)
report "g_family = " & g_family & " is unsupported"
severity error;
assert (g_port_width = 1 or g_port_width = 4)
report "g_port_width must be 1 or 4, not " & integer'image(g_port_width)
severity error;
assert (g_port_width /= 4 or c_support4)
report "g_family = " & g_family & " does not support g_port_width = 4"
severity error;
data_o <= data(data_o'range);
width1 : if g_port_width = 1 generate
oe <= (0 => '1', 1 => '0', others => '1');
asdo <= (0 => asdo_i(0), others => '1');
end generate;
width4 : if g_port_width = 4 generate
oe <= oe_i;
asdo <= asdo_i;
end generate;
cyclone : if c_block = T_CYCLONE generate
cyclone_inst : cyclone_asmiblock
port map(
dclkin => dclk_i,
scein => ncs_i,
sdoin => asdo(0),
data0out => data(0),
oe => '0');
end generate;
cycloneii : if c_block = T_CYCLONEII generate
cycloneii_inst: cycloneii_asmiblock
port map(
dclkin => dclk_i,
scein => ncs_i,
sdoin => asdo(0),
data0out => data(0),
oe => '0');
end generate;
stratixii : if c_block = T_STRATIXII generate
stratixii_inst : stratixii_asmiblock
port map(
dclkin => dclk_i,
scein => ncs_i,
sdoin => asdo(0),
data0out => data(0),
oe => '0');
end generate;
stratixiii : if c_block = T_STRATIXIII generate
stratixiii_inst: stratixiii_asmiblock
port map(
dclkin => dclk_i,
scein => ncs_i,
sdoin => asdo(0),
data0out => data(0),
oe => '0');
end generate;
stratixiv : if c_block = T_STRATIXIV generate
asmi_inst: stratixiv_asmiblock
port map(
dclkin => dclk_i,
scein => ncs_i,
sdoin => asdo(0),
data0out => data(0),
oe => '0');
end generate;
stratixv : if c_block = T_STRATIXV generate
stratixv_inst : stratixv_asmiblock
port map(
dclk => dclk_i,
sce => ncs_i,
oe => '0',
data0out => asdo(0),
data1out => asdo(1),
data2out => asdo(2),
data3out => asdo(3),
data0oe => oe(0),
data1oe => oe(1),
data2oe => oe(2),
data3oe => oe(3),
data0in => data(0),
data1in => data(1),
data2in => data(2),
data3in => data(3));
end generate;
arriav : if c_block = T_ARRIAV generate
arriav_inst : arriav_asmiblock
port map(
dclk => dclk_i,
sce => ncs_i,
oe => '0',
data0out => asdo(0),
data1out => asdo(1),
data2out => asdo(2),
data3out => asdo(3),
data0oe => oe(0),
data1oe => oe(1),
data2oe => oe(2),
data3oe => oe(3),
data0in => data(0),
data1in => data(1),
data2in => data(2),
data3in => data(3));
end generate;
cyclonev : if c_block = T_CYCLONEV generate
cyclonev_inst : cyclonev_asmiblock
port map(
dclk => dclk_i,
sce => ncs_i,
oe => '0',
data0out => asdo(0),
data1out => asdo(1),
data2out => asdo(2),
data3out => asdo(3),
data0oe => oe(0),
data1oe => oe(1),
data2oe => oe(2),
data3oe => oe(3),
data0in => data(0),
data1in => data(1),
data2in => data(2),
data3in => data(3));
end generate;
end rtl;
hdl/ip_cores/platform/altera/flash/flash_top.vhd 0 → 100644
View file @ 4a2e47ff
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
entity flash_top is
generic(
g_family : string;
g_port_width : natural := 1;
g_addr_width : natural := 24;
g_dummy_time : natural := 8;
g_config : boolean := false;
g_input_latch_edge : std_logic;
g_output_latch_edge : std_logic;
g_input_to_output_cycles : natural);
port(
-- Wishbone interface
clk_i : in std_logic;
rstn_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- Clock lines for flash chip
clk_ext_i : in std_logic;
clk_out_i : in std_logic;
clk_in_i : in std_logic);
end flash_top;
architecture rtl of flash_top is
component altera_spi is
generic(
g_family : string := "none";
g_port_width : natural := 1);
port(
dclk_i : in std_logic;
ncs_i : in std_logic;
oe_i : in std_logic_vector(g_port_width-1 downto 0);
asdo_i : in std_logic_vector(g_port_width-1 downto 0);
data_o : out std_logic_vector(g_port_width-1 downto 0));
end component;
signal flash_ncs : std_logic;
signal flash_oe : std_logic_vector(g_port_width-1 downto 0);
signal flash_asdo : std_logic_vector(g_port_width-1 downto 0);
signal flash_data : std_logic_vector(g_port_width-1 downto 0);
begin
wb : wb_spi_flash
generic map(
g_port_width => g_port_width,
g_addr_width => g_addr_width,
g_idle_time => 3,
g_dummy_time => g_dummy_time,
g_config => g_config,
g_input_latch_edge => g_input_latch_edge,
g_output_latch_edge => g_output_latch_edge,
g_input_to_output_cycles => g_input_to_output_cycles)
port map(
clk_i => clk_i,
rstn_i => rstn_i,
slave_i => slave_i,
slave_o => slave_o,
clk_out_i => clk_out_i,
clk_in_i => clk_in_i,
ncs_o => flash_ncs,
oe_o => flash_oe,
asdi_o => flash_asdo,
data_i => flash_data,
external_request_i => '0',
external_granted_o => open);
spi : altera_spi
generic map(
g_family => g_family,
g_port_width => g_port_width)
port map(
dclk_i => clk_ext_i,
ncs_i => flash_ncs,
oe_i => flash_oe,
asdo_i => flash_asdo,
data_o => flash_data);
end rtl;
hdl/ip_cores/platform/altera/networks/.gitignore 0 → 100644
View file @ 4a2e47ff
dual_region.cmp
dual_region.qip
dual_region.vhd
global_region.cmp
global_region.qip
global_region.vhd
single_region.cmp
single_region.qip
single_region.vhd
hdl/ip_cores/platform/altera/networks/Manifest.py 0 → 100644
View file @ 4a2e47ff
def __helper():
files = [ "altera_networks_pkg.vhd" ]
if syn_device[:1] == "5": files.extend(["arria5_networks.qip"])
if syn_device[:6] == "ep2agx": files.extend(["arria2gx_networks.qip"])
return files
files = __helper()
hdl/ip_cores/platform/altera/networks/altera_networks_pkg.vhd 0 → 100644
View file @ 4a2e47ff
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
package altera_networks_pkg is
component single_region is
port(
inclk : in std_logic;
outclk : out std_logic);
end component;
component dual_region is
port(
inclk : in std_logic;
outclk : out std_logic);
end component;
component global_region is
port(
inclk : in std_logic;
outclk : out std_logic);
end component;
end altera_networks_pkg;
hdl/ip_cores/platform/altera/networks/arria2gx.tcl 0 → 100644
View file @ 4a2e47ff
qmegawiz { arria2gx/dual_region arria2gx/single_region arria2gx/global_region }
hdl/ip_cores/platform/altera/networks/arria2gx/dual_region.txt 0 → 100644
View file @ 4a2e47ff
-- megafunction wizard: %ALTCLKCTRL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altclkctrl
--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Dual-Regional Clock" DEVICE_FAMILY="Arria II GX" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
--VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:03:33:SJ cbx_cycloneii 2013:06:12:18:03:33:SJ cbx_lpm_add_sub 2013:06:12:18:03:33:SJ cbx_lpm_compare 2013:06:12:18:03:33:SJ cbx_lpm_decode 2013:06:12:18:03:33:SJ cbx_lpm_mux 2013:06:12:18:03:33:SJ cbx_mgl 2013:06:12:18:33:59:SJ cbx_stratix 2013:06:12:18:03:33:SJ cbx_stratixii 2013:06:12:18:03:33:SJ cbx_stratixiii 2013:06:12:18:03:33:SJ cbx_stratixv 2013:06:12:18:03:33:SJ VERSION_END
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
-- Retrieval info: CONSTANT: clock_type STRING "Dual-Regional Clock"
-- Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
-- Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
-- Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
-- Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region_inst.vhd FALSE
-- Retrieval info: LIB_FILE: arriaii
hdl/ip_cores/platform/altera/networks/arria2gx/global_region.txt 0 → 100644
View file @ 4a2e47ff
-- megafunction wizard: %ALTCLKCTRL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altclkctrl
--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Arria II GX" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
--VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:03:33:SJ cbx_cycloneii 2013:06:12:18:03:33:SJ cbx_lpm_add_sub 2013:06:12:18:03:33:SJ cbx_lpm_compare 2013:06:12:18:03:33:SJ cbx_lpm_decode 2013:06:12:18:03:33:SJ cbx_lpm_mux 2013:06:12:18:03:33:SJ cbx_mgl 2013:06:12:18:33:59:SJ cbx_stratix 2013:06:12:18:03:33:SJ cbx_stratixii 2013:06:12:18:03:33:SJ cbx_stratixiii 2013:06:12:18:03:33:SJ cbx_stratixv 2013:06:12:18:03:33:SJ VERSION_END
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
-- Retrieval info: CONSTANT: clock_type STRING "Global Clock"
-- Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
-- Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
-- Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
-- Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL global_region.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL global_region.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL global_region.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL global_region.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL global_region_inst.vhd FALSE
-- Retrieval info: LIB_FILE: arriaii
hdl/ip_cores/platform/altera/networks/arria2gx/single_region.txt 0 → 100644
View file @ 4a2e47ff
-- megafunction wizard: %ALTCLKCTRL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altclkctrl
--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Regional Clock" DEVICE_FAMILY="Arria II GX" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
--VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:03:33:SJ cbx_cycloneii 2013:06:12:18:03:33:SJ cbx_lpm_add_sub 2013:06:12:18:03:33:SJ cbx_lpm_compare 2013:06:12:18:03:33:SJ cbx_lpm_decode 2013:06:12:18:03:33:SJ cbx_lpm_mux 2013:06:12:18:03:33:SJ cbx_mgl 2013:06:12:18:33:59:SJ cbx_stratix 2013:06:12:18:03:33:SJ cbx_stratixii 2013:06:12:18:03:33:SJ cbx_stratixiii 2013:06:12:18:03:33:SJ cbx_stratixv 2013:06:12:18:03:33:SJ VERSION_END
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
-- Retrieval info: CONSTANT: clock_type STRING "Regional Clock"
-- Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
-- Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
-- Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
-- Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL single_region.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL single_region.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL single_region.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL single_region.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL single_region_inst.vhd FALSE
-- Retrieval info: LIB_FILE: arriaii
hdl/ip_cores/platform/altera/networks/arria2gx_networks.qip 0 → 100644
View file @ 4a2e47ff
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2gx/dual_region.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2gx/single_region.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2gx/global_region.qip"]
hdl/ip_cores/platform/altera/networks/arria5.tcl 0 → 100644
View file @ 4a2e47ff
qmegawiz { arria5/dual_region arria5/single_region arria5/global_region }
hdl/ip_cores/platform/altera/networks/arria5/dual_region.txt 0 → 100644
View file @ 4a2e47ff
-- megafunction wizard: %ALTCLKCTRL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altclkctrl
--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Dual-Regional Clock" DEVICE_FAMILY="Arria V" ENA_REGISTER_MODE="always enabled" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
--VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:03:33:SJ cbx_cycloneii 2013:06:12:18:03:33:SJ cbx_lpm_add_sub 2013:06:12:18:03:33:SJ cbx_lpm_compare 2013:06:12:18:03:33:SJ cbx_lpm_decode 2013:06:12:18:03:33:SJ cbx_lpm_mux 2013:06:12:18:03:33:SJ cbx_mgl 2013:06:12:18:33:59:SJ cbx_stratix 2013:06:12:18:03:33:SJ cbx_stratixii 2013:06:12:18:03:33:SJ cbx_stratixiii 2013:06:12:18:03:33:SJ cbx_stratixv 2013:06:12:18:03:33:SJ VERSION_END
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
-- Retrieval info: CONSTANT: ENA_REGISTER_MODE STRING "always enabled"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria V"
-- Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
-- Retrieval info: CONSTANT: clock_type STRING "Dual-Regional Clock"
-- Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
-- Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
-- Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
-- Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region_inst.vhd FALSE
-- Retrieval info: LIB_FILE: arriav
hdl/ip_cores/platform/altera/networks/arria5/global_region.txt 0 → 100644
View file @ 4a2e47ff
-- megafunction wizard: %ALTCLKCTRL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altclkctrl
--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Arria V" ENA_REGISTER_MODE="always enabled" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
--VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:03:33:SJ cbx_cycloneii 2013:06:12:18:03:33:SJ cbx_lpm_add_sub 2013:06:12:18:03:33:SJ cbx_lpm_compare 2013:06:12:18:03:33:SJ cbx_lpm_decode 2013:06:12:18:03:33:SJ cbx_lpm_mux 2013:06:12:18:03:33:SJ cbx_mgl 2013:06:12:18:33:59:SJ cbx_stratix 2013:06:12:18:03:33:SJ cbx_stratixii 2013:06:12:18:03:33:SJ cbx_stratixiii 2013:06:12:18:03:33:SJ cbx_stratixv 2013:06:12:18:03:33:SJ VERSION_END
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
-- Retrieval info: CONSTANT: ENA_REGISTER_MODE STRING "always enabled"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria V"
-- Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
-- Retrieval info: CONSTANT: clock_type STRING "Global Clock"
-- Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
-- Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
-- Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
-- Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL global_region.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL global_region.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL global_region.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL global_region.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL global_region_inst.vhd FALSE
-- Retrieval info: LIB_FILE: arriav
hdl/ip_cores/platform/altera/networks/arria5/single_region.txt 0 → 100644
View file @ 4a2e47ff
-- megafunction wizard: %ALTCLKCTRL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altclkctrl
--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Regional Clock" DEVICE_FAMILY="Arria V" ENA_REGISTER_MODE="always enabled" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
--VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:03:33:SJ cbx_cycloneii 2013:06:12:18:03:33:SJ cbx_lpm_add_sub 2013:06:12:18:03:33:SJ cbx_lpm_compare 2013:06:12:18:03:33:SJ cbx_lpm_decode 2013:06:12:18:03:33:SJ cbx_lpm_mux 2013:06:12:18:03:33:SJ cbx_mgl 2013:06:12:18:33:59:SJ cbx_stratix 2013:06:12:18:03:33:SJ cbx_stratixii 2013:06:12:18:03:33:SJ cbx_stratixiii 2013:06:12:18:03:33:SJ cbx_stratixv 2013:06:12:18:03:33:SJ VERSION_END
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
-- Retrieval info: CONSTANT: ENA_REGISTER_MODE STRING "always enabled"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria V"
-- Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
-- Retrieval info: CONSTANT: clock_type STRING "Regional Clock"
-- Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
-- Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
-- Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
-- Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL single_region.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL single_region.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL single_region.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL single_region.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL single_region_inst.vhd FALSE
-- Retrieval info: LIB_FILE: arriav
hdl/ip_cores/platform/altera/networks/arria5_networks.qip 0 → 100644
View file @ 4a2e47ff
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria5/dual_region.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria5/single_region.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria5/global_region.qip"]
hdl/ip_cores/platform/altera/wb_pcie/.gitignore 0 → 100644
View file @ 4a2e47ff
# quartus droppings
db/
greybox_tmp/
# arria5 pcie reconfig core
arria5_pcie_reconf_sim/
arria5_pcie_reconf/
arria5_pcie_reconf.bsf
arria5_pcie_reconf.cmp
arria5_pcie_reconf.ppf
arria5_pcie_reconf.qip
arria5_pcie_reconf_sim
arria5_pcie_reconf.sip
arria5_pcie_reconf.spd
arria5_pcie_reconf.vhd
arria5_pcie_reconf_sim.f
# arria5 pcie hard ip core
arria5_pcie_hip_example_design/
arria5_pcie_hip_sim/
arria5_pcie_hip/
arria5_pcie_hip.bsf
arria5_pcie_hip.cmp
arria5_pcie_hip.ppf
arria5_pcie_hip.qip
arria5_pcie_hip_sim
arria5_pcie_hip.sip
arria5_pcie_hip.spd
arria5_pcie_hip.vhd
arria5_pcie_hip_sim.f
# arria2 pcie reconfig core
arria2_pcie_reconf.cmp
arria2_pcie_reconf.qip
arria2_pcie_reconf.vhd
# arria2 pcie hard ip core
ip_compiler_for_pci_express-library/
arria2_pcie_hip_examples/
arria2_pcie_hip.bsf
arria2_pcie_hip.ppf
arria2_pcie_hip.ppx
arria2_pcie_hip.qip
arria2_pcie_hip.sdc
arria2_pcie_hip.tcl
arria2_pcie_hip.vhd
arria2_pcie_hip_core.cmp
arria2_pcie_hip_core.vhd
arria2_pcie_hip_serdes.vhd
arria2_pcie_hip_serdes.cmp
hdl/ip_cores/platform/altera/wb_pcie/Manifest.py 0 → 100644
View file @ 4a2e47ff
def __helper():
files = [
"pcie_32to64.vhd",
"pcie_64to32.vhd",
"pcie_altera.vhd",
"pcie_tlp.vhd",
"pcie_wb.vhd",
"pcie_wb_pkg.vhd"]
if syn_device[:1] == "5": files.extend(["arria5_pcie.qip"])
if syn_device[:4] == "ep2a": files.extend(["arria2_pcie.qip"])
return files
files = __helper()
hdl/ip_cores/platform/altera/wb_pcie/arria2.tcl 0 → 100644
View file @ 4a2e47ff
qmegawiz { arria2_pcie_hip arria2_pcie_reconf }
# erase the broke SDC file that gets generated
set dir [file dirname [info script]]
open "$dir/arria2_pcie_hip.sdc" "w"
hdl/ip_cores/platform/altera/wb_pcie/arria2_pcie.qip 0 → 100644
View file @ 4a2e47ff
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2_pcie_hip.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2_pcie_reconf.qip"]
hdl/ip_cores/platform/altera/wb_pcie/arria2_pcie_hip.txt 0 → 100644
View file @ 4a2e47ff
This diff is collapsed.
hdl/ip_cores/platform/altera/wb_pcie/arria2_pcie_reconf.txt 0 → 100644
View file @ 4a2e47ff
-- megafunction wizard: %ALTGX_RECONFIG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: alt2gxb_reconfig
--alt2gxb_reconfig BASE_PORT_WIDTH=1 CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Arria II GX" ENABLE_BUF_CAL="TRUE" ENABLE_CHL_ADDR_FOR_ANALOG_CTRL="TRUE" NUMBER_OF_CHANNELS=1 NUMBER_OF_RECONFIG_PORTS=1 READ_BASE_PORT_WIDTH=1 RECONFIG_FROMGXB_WIDTH=17 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_mode_sel reconfig_togxb
--VERSION_BEGIN 13.1 cbx_alt2gxb_reconfig 2013:10:17:04:07:49:SJ cbx_alt_cal 2013:10:17:04:07:49:SJ cbx_alt_dprio 2013:10:17:04:07:49:SJ cbx_altsyncram 2013:10:17:04:07:49:SJ cbx_cycloneii 2013:10:17:04:07:49:SJ cbx_lpm_add_sub 2013:10:17:04:07:49:SJ cbx_lpm_compare 2013:10:17:04:07:49:SJ cbx_lpm_counter 2013:10:17:04:07:49:SJ cbx_lpm_decode 2013:10:17:04:07:49:SJ cbx_lpm_mux 2013:10:17:04:07:49:SJ cbx_lpm_shiftreg 2013:10:17:04:07:49:SJ cbx_mgl 2013:10:17:04:34:36:SJ cbx_stratix 2013:10:17:04:07:49:SJ cbx_stratixii 2013:10:17:04:07:49:SJ cbx_stratixiii 2013:10:17:04:07:49:SJ cbx_stratixv 2013:10:17:04:07:49:SJ cbx_util_mgl 2013:10:17:04:07:49:SJ VERSION_END
--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Arria II GX" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
--VERSION_BEGIN 13.1 cbx_alt_dprio 2013:10:17:04:07:49:SJ cbx_cycloneii 2013:10:17:04:07:49:SJ cbx_lpm_add_sub 2013:10:17:04:07:49:SJ cbx_lpm_compare 2013:10:17:04:07:49:SJ cbx_lpm_counter 2013:10:17:04:07:49:SJ cbx_lpm_decode 2013:10:17:04:07:49:SJ cbx_lpm_shiftreg 2013:10:17:04:07:49:SJ cbx_mgl 2013:10:17:04:34:36:SJ cbx_stratix 2013:10:17:04:07:49:SJ cbx_stratixii 2013:10:17:04:07:49:SJ VERSION_END
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: PRIVATE: PMA NUMERIC "1"
-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: CONSTANT: BASE_PORT_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
-- Retrieval info: CONSTANT: ENABLE_CHL_ADDR_FOR_ANALOG_CTRL STRING "TRUE"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "1"
-- Retrieval info: CONSTANT: READ_BASE_PORT_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "17"
-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 INPUT NODEFVAL "reconfig_fromgxb[16..0]"
-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 17 0 reconfig_fromgxb 0 0 17 0
-- Retrieval info: CONNECT: @reconfig_mode_sel 0 0 3 0 GND 0 0 3 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_pcie_reconf.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_pcie_reconf.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_pcie_reconf.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_pcie_reconf.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_pcie_reconf_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
hdl/ip_cores/platform/altera/wb_pcie/arria5.tcl 0 → 100644
View file @ 4a2e47ff
qmegawiz { arria5_pcie_hip arria5_pcie_reconf }
hdl/ip_cores/platform/altera/wb_pcie/arria5_pcie.qip 0 → 100644
View file @ 4a2e47ff
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria5_pcie_hip.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria5_pcie_reconf.qip"]
hdl/ip_cores/platform/altera/wb_pcie/arria5_pcie_hip.txt 0 → 100644
View file @ 4a2e47ff
This diff is collapsed.
hdl/ip_cores/platform/altera/wb_pcie/arria5_pcie_reconf.txt 0 → 100644
View file @ 4a2e47ff
-- megafunction wizard: %Transceiver Reconfiguration Controller v13.1%
-- Retrieval info: <instance entity-name="alt_xcvr_reconfig" version="13.1" >
-- Retrieval info: <generic name="device_family" value="Arria V" />
-- Retrieval info: <generic name="number_of_reconfig_interfaces" value="5" />
-- Retrieval info: <generic name="gui_split_sizes" value="" />
-- Retrieval info: <generic name="enable_offset" value="1" />
-- Retrieval info: <generic name="enable_dcd" value="0" />
-- Retrieval info: <generic name="enable_dcd_power_up" value="1" />
-- Retrieval info: <generic name="enable_analog" value="1" />
-- Retrieval info: <generic name="enable_eyemon" value="0" />
-- Retrieval info: <generic name="ber_en" value="0" />
-- Retrieval info: <generic name="enable_dfe" value="0" />
-- Retrieval info: <generic name="enable_adce" value="0" />
-- Retrieval info: <generic name="enable_mif" value="0" />
-- Retrieval info: <generic name="gui_enable_pll" value="0" />
-- Retrieval info: <generic name="gui_cal_status_port" value="false" />
-- Retrieval info: <generic name="AUTO_MGMT_CLK_CLK_CLOCK_RATE" value="-1" />
-- Retrieval info: </instance>
hdl/ip_cores/platform/altera/wb_pcie/pcie_32to64.vhd 0 → 100644
View file @ 4a2e47ff
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pcie_32to64 is
port(
clk_i : in std_logic;
rstn_i : in std_logic;
-- The 32-bit source
master32_stb_i : in std_logic;
master32_dat_i : in std_logic_vector(31 downto 0);
master32_stall_o : out std_logic;
-- The 64-bit sink
slave64_stb_o : out std_logic;
slave64_dat_o : out std_logic_vector(63 downto 0);
slave64_stall_i : in std_logic);
end pcie_32to64;
architecture rtl of pcie_32to64 is
signal low : std_logic_vector(31 downto 0);
signal full : std_logic;
signal stall32 : std_logic;
signal stb64 : std_logic;
begin
master32_stall_o <= stall32;
stall32 <= slave64_stall_i and full;
slave64_stb_o <= stb64;
slave64_dat_o <= master32_dat_i & low;
stb64 <= master32_stb_i and full;
main : process(clk_i)
begin
if rising_edge(clk_i) then
if rstn_i = '0' then
full <= '0';
else
if (master32_stb_i and not stall32) = '1' then
low <= master32_dat_i;
full <= '1';
end if;
if (stb64 and not slave64_stall_i) = '1' then
full <= '0';
end if;
end if;
end if;
end process;
end rtl;
hdl/ip_cores/platform/altera/wb_pcie/pcie_64to32.vhd 0 → 100644
View file @ 4a2e47ff
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pcie_64to32 is
port(
clk_i : in std_logic;
rstn_i : in std_logic;
-- The 64-bit source
master64_stb_i : in std_logic;
master64_dat_i : in std_logic_vector(63 downto 0);
master64_stall_o : out std_logic;
-- The 32-bit sink
slave32_stb_o : out std_logic;
slave32_dat_o : out std_logic_vector(31 downto 0);
slave32_stall_i : in std_logic);
end pcie_64to32;
architecture rtl of pcie_64to32 is
signal high : std_logic_vector(31 downto 0);
signal full : std_logic;
signal stall64 : std_logic;
signal stb32 : std_logic;
begin
master64_stall_o <= stall64;
stall64 <= full or slave32_stall_i;
slave32_stb_o <= stb32;
slave32_dat_o <= high when full = '1' else master64_dat_i(31 downto 0);
stb32 <= master64_stb_i or full;
main : process(clk_i)
begin
if rising_edge(clk_i) then
if rstn_i = '0' then
full <= '0';
else
if (stb32 and not slave32_stall_i) = '1' then
full <= '0';
end if;
if (master64_stb_i and not stall64) = '1' then
high <= master64_dat_i(63 downto 32);
full <= '1';
end if;
end if;
end if;
end process;
end rtl;
hdl/ip_cores/platform/altera/wb_pcie/pcie_altera.vhd 0 → 100644
View file @ 4a2e47ff
This diff is collapsed.
hdl/ip_cores/platform/altera/wb_pcie/pcie_tlp.vhd 0 → 100644
View file @ 4a2e47ff
This diff is collapsed.
hdl/ip_cores/platform/altera/wb_pcie/pcie_wb.vhd 0 → 100644
View file @ 4a2e47ff
This diff is collapsed.
hdl/ip_cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd 0 → 100644
View file @ 4a2e47ff
This diff is collapsed.
hdl/ip_cores/platform/xilinx/Manifest.py 0 → 100644
View file @ 4a2e47ff
modules = {
"local" : [
"wb_xilinx_fpga_loader",
"wb_xil_multiboot"
]
}
hdl/ip_cores/platform/xilinx/wb_xil_multiboot/Manifest.py 0 → 100644
View file @ 4a2e47ff
files = [
"spi_master.vhd",
"multiboot_fsm.vhd",
"multiboot_regs.vhd",
"wb_xil_multiboot.vhd"
]
hdl/ip_cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd 0 → 100644
View file @ 4a2e47ff
This diff is collapsed.
hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/Manifest.py 0 → 100644
View file @ 4a2e47ff
files = [
"wb_xilinx_fpga_loader.vhd",
"xwb_xilinx_fpga_loader.vhd",
"xloader_registers_pkg.vhd",
"xloader_wb.vhd"];
hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/build_wb.sh 0 → 100644
View file @ 4a2e47ff
#!/bin/bash
wbgen2 -V xloader_wb.vhd -H record -p xloader_registers_pkg.vhd -K ../../../sim/regs/xloader_regs.vh -s defines -C xloader_regs.h -D wb_xilinx_fpga_loader.html xloader_wb.wb
\ No newline at end of file
hdl/ip_cores/wishbone/wb_crossbar/Manifest.py
View file @ 4a2e47ff
files = [
"sdb_rom.vhd",
"xwb_crossbar.vhd",
"xwb_sdb_crossbar.vhd" ];
"xwb_sdb_crossbar.vhd",
"xwb_register_link.vhd",
]
hdl/ip_cores/wishbone/wb_crossbar/xwb_crossbar.vhd
View file @ 4a2e47ff
......@@ -81,7 +81,9 @@ architecture rtl of xwb_crossbar is
begin
for i in 0 to g_num_slaves-2 loop
for j in i+1 to g_num_slaves-1 loop
assert not (((c_mask(i) and c_mask(j)) and (c_address(i) xor c_address(j))) = zero)
assert not (((c_mask(i) and c_mask(j)) and (c_address(i) xor c_address(j))) = zero) or
((c_mask(i) or not c_address(i)) = zero) or -- disconnected slave?
((c_mask(j) or not c_address(j)) = zero) -- disconnected slave?
report "Address ranges must be distinct (slaves " &
Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
f_bits2string(c_mask(i)) & "] & " &
......
hdl/ip_cores/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
View file @ 4a2e47ff
......@@ -65,7 +65,7 @@ architecture rtl of xwb_sdb_crossbar is
result(c_wishbone_address_width-1 downto 0) := unsigned(g_sdb_addr);
result := result + to_unsigned(c_rom_bytes, 64) - 1;
for i in c_layout'range loop
for i in g_num_slaves-1 downto 0 loop
if c_layout(i)(7) /= '1' then -- Ignore meta-information
sdb_component := f_sdb_extract_component(c_layout(i)(447 downto 8));
if unsigned(sdb_component.addr_last) > result then
......@@ -89,8 +89,11 @@ architecture rtl of xwb_sdb_crossbar is
variable sdb_component : t_sdb_component;
variable extend : unsigned(63 downto 0) := (others => '0');
begin
for i in c_layout'range loop
if c_layout(i)(7) /= '1' then -- Ignore meta-information
for i in g_num_slaves-1 downto 0 loop
if c_layout(i)(7) = '1' then
-- ignore meta-data
result(i) := (others => '1');
else
sdb_component := f_sdb_extract_component(c_layout(i)(447 downto 8));
result(i) := sdb_component.addr_first(c_wishbone_address_width-1 downto 0);
......@@ -116,8 +119,11 @@ architecture rtl of xwb_sdb_crossbar is
variable size : unsigned(63 downto 0);
constant zero : unsigned(63 downto 0) := (others => '0');
begin
for i in c_layout'range loop
if c_layout(i)(7) /= '1' then -- Ignore meta-information
for i in g_num_slaves-1 downto 0 loop
if c_layout(i)(7) = '1' then
-- ignore meta-data
result(i) := (others => '0');
else
sdb_component := f_sdb_extract_component(c_layout(i)(447 downto 8));
size := unsigned(sdb_component.addr_last) - unsigned(sdb_component.addr_first);
......
hdl/ip_cores/wishbone/wishbone_pkg.vhd
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files = ["wr_fabric_pkg.vhd", "xwb_fabric_sink.vhd", "xwb_fabric_source.vhd", "xwrf_mux.vhd" ]
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files = ["dmtd_phase_meas.vhd",
"dmtd_with_deglitcher.vhd",
"multi_dmtd_with_deglitcher.vhd",
"hpll_period_detect.vhd",
"pulse_gen.vhd",
"pulse_stamper.vhd" ]
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hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_pcs_16bit.vhd 0 → 100644
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hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_pcs_8bit.vhd 0 → 100644
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hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_vlan_unit.vhd 0 → 100644
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hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_pcs_8bit.vhd 0 → 100644
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hdl/ip_cores/wrabbit/modules/wr_endpoint/pcs_regs.wb 0 → 100644
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hdl/ip_cores/wrabbit/modules/wr_endpoint/xwr_endpoint.vhd 0 → 100644
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hdl/ip_cores/wrabbit/modules/wr_mini_nic/Manifest.py 0 → 100644
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hdl/ip_cores/wrabbit/modules/wr_mini_nic/build_wb.sh 0 → 100644
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hdl/ip_cores/wrabbit/modules/wr_mini_nic/wr_mini_nic.vhd 0 → 100644
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hdl/ip_cores/wrabbit/modules/wr_mini_nic/xwr_mini_nic.vhd 0 → 100644
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hdl/ip_cores/wrabbit/modules/wr_pps_gen/Manifest.py 0 → 100644
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