ip_cores added some missing files:-/

git-svn-id: http://svn.ohwr.org/fmc-tdc@183 85dfdc96-de2c-444c-878d-45b388be74a9

ip_cores added some missing files:-/
git-svn-id: http://svn.ohwr.org/fmc-tdc@183 85dfdc96-de2c-444c-878d-45b388be74a9
4a2e47ff · egousiou · 11dd82b0 · 4a2e47ff · 4a2e47ff · 4a2e47ff
Commit 4a2e47ff authored Jul 07, 2014 by egousiou
267 changed files
--- a/hdl/ip_cores/gnum_core/dma_controller.vhd
+++ b/hdl/ip_cores/gnum_core/dma_controller.vhd
--- a/hdl/ip_cores/gnum_core/dma_controller_wb_slave.vhd
+++ b/hdl/ip_cores/gnum_core/dma_controller_wb_slave.vhd
--- a/hdl/ip_cores/gnum_core/l2p_arbiter.vhd
+++ b/hdl/ip_cores/gnum_core/l2p_arbiter.vhd
--- a/hdl/ip_cores/gnum_core/l2p_dma_master.vhd
+++ b/hdl/ip_cores/gnum_core/l2p_dma_master.vhd
--- a/hdl/ip_cores/gnum_core/p2l_dma_master.vhd
+++ b/hdl/ip_cores/gnum_core/p2l_dma_master.vhd
--- a/hdl/ip_cores/gnum_core/wbmaster32.vhd
+++ b/hdl/ip_cores/gnum_core/wbmaster32.vhd
--- a/hdl/ip_cores/gnum_core/xilinx_cores/coregen.cgc
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/coregen.cgc
--- a/hdl/ip_cores/gnum_core/xilinx_cores/coregen.cgp
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/coregen.cgp
-SET busformat = BusFormatAngleBracketNotRipped
-SET designentry = VHDL
-SET device = xc6slx45t
-SET devicefamily = spartan6
-SET flowvendor = Foundation_ISE
-SET package = fgg484
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = true
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.gise
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.gise
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_32x512.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_32x512.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="fifo_32x512.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_32x512.veo" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo_32x512.vho" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1390819957">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1391772794" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8777296749647723518" xil_pn:start_ts="1391772794">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1391772794" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="2104667735123416897" xil_pn:start_ts="1391772794">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1391772794" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1391772794">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1391772794" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1627810207069309888" xil_pn:start_ts="1391772794">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ncf
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ncf
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ndf
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ndf
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd
--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_32x512.vhd when simulating
-- the core, fifo_32x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
-Library XilinxCoreLib;
-- synthesis translate_on
-ENTITY fifo_32x512 IS
-	port (
-	rst: IN std_logic;
-	wr_clk: IN std_logic;
-	rd_clk: IN std_logic;
-	din: IN std_logic_VECTOR(31 downto 0);
-	wr_en: IN std_logic;
-	rd_en: IN std_logic;
-	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
-	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
-	dout: OUT std_logic_VECTOR(31 downto 0);
-	full: OUT std_logic;
-	empty: OUT std_logic;
-	valid: OUT std_logic;
-	prog_full: OUT std_logic);
-END fifo_32x512;
-
-ARCHITECTURE fifo_32x512_a OF fifo_32x512 IS
-- synthesis translate_off
-component wrapped_fifo_32x512
-	port (
-	rst: IN std_logic;
-	wr_clk: IN std_logic;
-	rd_clk: IN std_logic;
-	din: IN std_logic_VECTOR(31 downto 0);
-	wr_en: IN std_logic;
-	rd_en: IN std_logic;
-	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
-	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
-	dout: OUT std_logic_VECTOR(31 downto 0);
-	full: OUT std_logic;
-	empty: OUT std_logic;
-	valid: OUT std_logic;
-	prog_full: OUT std_logic);
-end component;
-
-- Configuration specification 
-	for all : wrapped_fifo_32x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
-		generic map(
-			c_has_int_clk => 0,
-			c_wr_response_latency => 1,
-			c_rd_freq => 1,
-			c_has_srst => 0,
-			c_enable_rst_sync => 1,
-			c_has_rd_data_count => 0,
-			c_din_width => 32,
-			c_has_wr_data_count => 0,
-			c_full_flags_rst_val => 1,
-			c_implementation_type => 2,
-			c_family => "spartan6",
-			c_use_embedded_reg => 0,
-			c_has_wr_rst => 0,
-			c_wr_freq => 1,
-			c_use_dout_rst => 1,
-			c_underflow_low => 0,
-			c_has_meminit_file => 0,
-			c_has_overflow => 0,
-			c_preload_latency => 1,
-			c_dout_width => 32,
-			c_msgon_val => 1,
-			c_rd_depth => 512,
-			c_default_value => "BlankString",
-			c_mif_file_name => "BlankString",
-			c_error_injection_type => 0,
-			c_has_underflow => 0,
-			c_has_rd_rst => 0,
-			c_has_almost_full => 0,
-			c_has_rst => 1,
-			c_data_count_width => 9,
-			c_has_wr_ack => 0,
-			c_use_ecc => 0,
-			c_wr_ack_low => 0,
-			c_common_clock => 0,
-			c_rd_pntr_width => 9,
-			c_use_fwft_data_count => 0,
-			c_has_almost_empty => 0,
-			c_rd_data_count_width => 9,
-			c_enable_rlocs => 0,
-			c_wr_pntr_width => 9,
-			c_overflow_low => 0,
-			c_prog_empty_type => 0,
-			c_optimization_mode => 0,
-			c_wr_data_count_width => 9,
-			c_preload_regs => 0,
-			c_dout_rst_val => "0",
-			c_has_data_count => 0,
-			c_prog_full_thresh_negate_val => 508,
-			c_wr_depth => 512,
-			c_prog_empty_thresh_negate_val => 3,
-			c_prog_empty_thresh_assert_val => 2,
-			c_has_valid => 1,
-			c_init_wr_pntr_val => 0,
-			c_prog_full_thresh_assert_val => 509,
-			c_use_fifo16_flags => 0,
-			c_has_backup => 0,
-			c_valid_low => 0,
-			c_prim_fifo_type => "512x36",
-			c_count_type => 0,
-			c_prog_full_type => 4,
-			c_memory_type => 1);
-- synthesis translate_on
-BEGIN
-- synthesis translate_off
-U0 : wrapped_fifo_32x512
-		port map (
-			rst => rst,
-			wr_clk => wr_clk,
-			rd_clk => rd_clk,
-			din => din,
-			wr_en => wr_en,
-			rd_en => rd_en,
-			prog_full_thresh_assert => prog_full_thresh_assert,
-			prog_full_thresh_negate => prog_full_thresh_negate,
-			dout => dout,
-			full => full,
-			empty => empty,
-			valid => valid,
-			prog_full => prog_full);
-- synthesis translate_on
-
-END fifo_32x512_a;
-
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vho
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vho
--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
-
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component fifo_32x512
-	port (
-	rst: IN std_logic;
-	wr_clk: IN std_logic;
-	rd_clk: IN std_logic;
-	din: IN std_logic_VECTOR(31 downto 0);
-	wr_en: IN std_logic;
-	rd_en: IN std_logic;
-	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
-	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
-	dout: OUT std_logic_VECTOR(31 downto 0);
-	full: OUT std_logic;
-	empty: OUT std_logic;
-	valid: OUT std_logic;
-	prog_full: OUT std_logic);
-end component;
-
-- Synplicity black box declaration
-attribute syn_black_box : boolean;
-attribute syn_black_box of fifo_32x512: component is true;
-
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
-
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : fifo_32x512
-		port map (
-			rst => rst,
-			wr_clk => wr_clk,
-			rd_clk => rd_clk,
-			din => din,
-			wr_en => wr_en,
-			rd_en => rd_en,
-			prog_full_thresh_assert => prog_full_thresh_assert,
-			prog_full_thresh_negate => prog_full_thresh_negate,
-			dout => dout,
-			full => full,
-			empty => empty,
-			valid => valid,
-			prog_full => prog_full);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-
-- You must compile the wrapper file fifo_32x512.vhd when simulating
-- the core, fifo_32x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.xco
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.xco
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.xise
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.xise
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.gise
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.gise
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ncf
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ncf
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ndf
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ndf
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vho
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vho
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.xco
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.xco
--- a/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.xise
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.xise
--- a/hdl/ip_cores/gnum_core/xilinx_cores/generic_async_fifo_wrapper.vhd
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/generic_async_fifo_wrapper.vhd
--- a/hdl/ip_cores/gnum_core/xilinx_cores/ngc2edif.log
+++ b/hdl/ip_cores/gnum_core/xilinx_cores/ngc2edif.log
--- a/hdl/ip_cores/platform/Manifest.py
+++ b/hdl/ip_cores/platform/Manifest.py
--- a/hdl/ip_cores/platform/altera/Manifest.py
+++ b/hdl/ip_cores/platform/altera/Manifest.py
--- a/hdl/ip_cores/platform/altera/flash/Manifest.py
+++ b/hdl/ip_cores/platform/altera/flash/Manifest.py
--- a/hdl/ip_cores/platform/altera/flash/altera_flash_pkg.vhd
+++ b/hdl/ip_cores/platform/altera/flash/altera_flash_pkg.vhd
--- a/hdl/ip_cores/platform/altera/flash/altera_spi.vhd
+++ b/hdl/ip_cores/platform/altera/flash/altera_spi.vhd
--- a/hdl/ip_cores/platform/altera/flash/flash_top.vhd
+++ b/hdl/ip_cores/platform/altera/flash/flash_top.vhd
--- a/hdl/ip_cores/platform/altera/networks/.gitignore
+++ b/hdl/ip_cores/platform/altera/networks/.gitignore
--- a/hdl/ip_cores/platform/altera/networks/Manifest.py
+++ b/hdl/ip_cores/platform/altera/networks/Manifest.py
--- a/hdl/ip_cores/platform/altera/networks/altera_networks_pkg.vhd
+++ b/hdl/ip_cores/platform/altera/networks/altera_networks_pkg.vhd
--- a/hdl/ip_cores/platform/altera/networks/arria2gx.tcl
+++ b/hdl/ip_cores/platform/altera/networks/arria2gx.tcl
+qmegawiz { arria2gx/dual_region arria2gx/single_region arria2gx/global_region }
--- a/hdl/ip_cores/platform/altera/networks/arria2gx/dual_region.txt
+++ b/hdl/ip_cores/platform/altera/networks/arria2gx/dual_region.txt
--- a/hdl/ip_cores/platform/altera/networks/arria2gx/global_region.txt
+++ b/hdl/ip_cores/platform/altera/networks/arria2gx/global_region.txt
--- a/hdl/ip_cores/platform/altera/networks/arria2gx/single_region.txt
+++ b/hdl/ip_cores/platform/altera/networks/arria2gx/single_region.txt
--- a/hdl/ip_cores/platform/altera/networks/arria2gx_networks.qip
+++ b/hdl/ip_cores/platform/altera/networks/arria2gx_networks.qip
--- a/hdl/ip_cores/platform/altera/networks/arria5.tcl
+++ b/hdl/ip_cores/platform/altera/networks/arria5.tcl
+qmegawiz { arria5/dual_region arria5/single_region arria5/global_region }
--- a/hdl/ip_cores/platform/altera/networks/arria5/dual_region.txt
+++ b/hdl/ip_cores/platform/altera/networks/arria5/dual_region.txt
--- a/hdl/ip_cores/platform/altera/networks/arria5/global_region.txt
+++ b/hdl/ip_cores/platform/altera/networks/arria5/global_region.txt
--- a/hdl/ip_cores/platform/altera/networks/arria5/single_region.txt
+++ b/hdl/ip_cores/platform/altera/networks/arria5/single_region.txt
--- a/hdl/ip_cores/platform/altera/networks/arria5_networks.qip
+++ b/hdl/ip_cores/platform/altera/networks/arria5_networks.qip
--- a/hdl/ip_cores/platform/altera/wb_pcie/.gitignore
+++ b/hdl/ip_cores/platform/altera/wb_pcie/.gitignore
--- a/hdl/ip_cores/platform/altera/wb_pcie/Manifest.py
+++ b/hdl/ip_cores/platform/altera/wb_pcie/Manifest.py
--- a/hdl/ip_cores/platform/altera/wb_pcie/arria2.tcl
+++ b/hdl/ip_cores/platform/altera/wb_pcie/arria2.tcl
--- a/hdl/ip_cores/platform/altera/wb_pcie/arria2_pcie.qip
+++ b/hdl/ip_cores/platform/altera/wb_pcie/arria2_pcie.qip
--- a/hdl/ip_cores/platform/altera/wb_pcie/arria2_pcie_hip.txt
+++ b/hdl/ip_cores/platform/altera/wb_pcie/arria2_pcie_hip.txt
--- a/hdl/ip_cores/platform/altera/wb_pcie/arria2_pcie_reconf.txt
+++ b/hdl/ip_cores/platform/altera/wb_pcie/arria2_pcie_reconf.txt
--- a/hdl/ip_cores/platform/altera/wb_pcie/arria5.tcl
+++ b/hdl/ip_cores/platform/altera/wb_pcie/arria5.tcl
+qmegawiz { arria5_pcie_hip arria5_pcie_reconf }
--- a/hdl/ip_cores/platform/altera/wb_pcie/arria5_pcie.qip
+++ b/hdl/ip_cores/platform/altera/wb_pcie/arria5_pcie.qip
--- a/hdl/ip_cores/platform/altera/wb_pcie/arria5_pcie_hip.txt
+++ b/hdl/ip_cores/platform/altera/wb_pcie/arria5_pcie_hip.txt
--- a/hdl/ip_cores/platform/altera/wb_pcie/arria5_pcie_reconf.txt
+++ b/hdl/ip_cores/platform/altera/wb_pcie/arria5_pcie_reconf.txt
--- a/hdl/ip_cores/platform/altera/wb_pcie/pcie_32to64.vhd
+++ b/hdl/ip_cores/platform/altera/wb_pcie/pcie_32to64.vhd
--- a/hdl/ip_cores/platform/altera/wb_pcie/pcie_64to32.vhd
+++ b/hdl/ip_cores/platform/altera/wb_pcie/pcie_64to32.vhd
--- a/hdl/ip_cores/platform/altera/wb_pcie/pcie_altera.vhd
+++ b/hdl/ip_cores/platform/altera/wb_pcie/pcie_altera.vhd
--- a/hdl/ip_cores/platform/altera/wb_pcie/pcie_tlp.vhd
+++ b/hdl/ip_cores/platform/altera/wb_pcie/pcie_tlp.vhd
--- a/hdl/ip_cores/platform/altera/wb_pcie/pcie_wb.vhd
+++ b/hdl/ip_cores/platform/altera/wb_pcie/pcie_wb.vhd
--- a/hdl/ip_cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd
+++ b/hdl/ip_cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd
--- a/hdl/ip_cores/platform/xilinx/Manifest.py
+++ b/hdl/ip_cores/platform/xilinx/Manifest.py
--- a/hdl/ip_cores/platform/xilinx/wb_xil_multiboot/Manifest.py
+++ b/hdl/ip_cores/platform/xilinx/wb_xil_multiboot/Manifest.py
--- a/hdl/ip_cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd
+++ b/hdl/ip_cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd
--- a/hdl/ip_cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd
+++ b/hdl/ip_cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd
--- a/hdl/ip_cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.wb
+++ b/hdl/ip_cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.wb
--- a/hdl/ip_cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd
+++ b/hdl/ip_cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd
--- a/hdl/ip_cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd
+++ b/hdl/ip_cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd
--- a/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/Manifest.py
+++ b/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/Manifest.py
--- a/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/build_wb.sh
+++ b/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/build_wb.sh
--- a/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
+++ b/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
--- a/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
+++ b/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
--- a/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
+++ b/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
--- a/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.wb
+++ b/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.wb
--- a/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
+++ b/hdl/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
--- a/hdl/ip_cores/wishbone/wb_crossbar/Manifest.py
+++ b/hdl/ip_cores/wishbone/wb_crossbar/Manifest.py
--- a/hdl/ip_cores/wishbone/wb_crossbar/xwb_crossbar.vhd
+++ b/hdl/ip_cores/wishbone/wb_crossbar/xwb_crossbar.vhd
--- a/hdl/ip_cores/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
+++ b/hdl/ip_cores/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
--- a/hdl/ip_cores/wishbone/wishbone_pkg.vhd
+++ b/hdl/ip_cores/wishbone/wishbone_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/fabric/Manifest.py
+++ b/hdl/ip_cores/wrabbit/modules/fabric/Manifest.py
--- a/hdl/ip_cores/wrabbit/modules/fabric/wr_fabric_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/modules/fabric/wr_fabric_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/fabric/xwb_fabric_sink.vhd
+++ b/hdl/ip_cores/wrabbit/modules/fabric/xwb_fabric_sink.vhd
--- a/hdl/ip_cores/wrabbit/modules/fabric/xwb_fabric_source.vhd
+++ b/hdl/ip_cores/wrabbit/modules/fabric/xwb_fabric_source.vhd
--- a/hdl/ip_cores/wrabbit/modules/fabric/xwrf_mux.vhd
+++ b/hdl/ip_cores/wrabbit/modules/fabric/xwrf_mux.vhd
--- a/hdl/ip_cores/wrabbit/modules/timing/Manifest.py
+++ b/hdl/ip_cores/wrabbit/modules/timing/Manifest.py
--- a/hdl/ip_cores/wrabbit/modules/timing/dmtd_phase_meas.vhd
+++ b/hdl/ip_cores/wrabbit/modules/timing/dmtd_phase_meas.vhd
--- a/hdl/ip_cores/wrabbit/modules/timing/dmtd_with_deglitcher.vhd
+++ b/hdl/ip_cores/wrabbit/modules/timing/dmtd_with_deglitcher.vhd
--- a/hdl/ip_cores/wrabbit/modules/timing/hpll_period_detect.vhd
+++ b/hdl/ip_cores/wrabbit/modules/timing/hpll_period_detect.vhd
--- a/hdl/ip_cores/wrabbit/modules/timing/multi_dmtd_with_deglitcher.vhd
+++ b/hdl/ip_cores/wrabbit/modules/timing/multi_dmtd_with_deglitcher.vhd
--- a/hdl/ip_cores/wrabbit/modules/timing/pulse_gen.vhd
+++ b/hdl/ip_cores/wrabbit/modules/timing/pulse_gen.vhd
--- a/hdl/ip_cores/wrabbit/modules/timing/pulse_stamper.vhd
+++ b/hdl/ip_cores/wrabbit/modules/timing/pulse_stamper.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_dacs/Manifest.py
+++ b/hdl/ip_cores/wrabbit/modules/wr_dacs/Manifest.py
--- a/hdl/ip_cores/wrabbit/modules/wr_dacs/spec_serial_dac.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_dacs/spec_serial_dac.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_dacs/spec_serial_dac_arb.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_dacs/spec_serial_dac_arb.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/.gitignore
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/.gitignore
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/Makefile
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/Makefile
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/Manifest.py
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/Manifest.py
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca-ctl.cpp
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca-ctl.cpp
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca-table.cpp
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca-table.cpp
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca.h
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca.h
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca_adder.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca_adder.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca_channel.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca_channel.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca_flags.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca_flags.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca_gpio_channel.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca_gpio_channel.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca_offset.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca_offset.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca_queue_channel.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca_queue_channel.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca_sdp.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca_sdp.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca_search.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca_search.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca_walker.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca_walker.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca_wb_channel.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca_wb_channel.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca_wb_event.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca_wb_event.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/eca_wr_time.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/eca_wr_time.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/lib/hw-channel.cpp
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/lib/hw-channel.cpp
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/lib/hw-eca.cpp
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/lib/hw-eca.cpp
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/lib/hw-eca.h
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/lib/hw-eca.h
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/lib/hw-stream.cpp
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/lib/hw-stream.cpp
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/lib/load-table.cpp
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/lib/load-table.cpp
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/lib/probe-eca.cpp
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/lib/probe-eca.cpp
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/lib/store-table.cpp
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/lib/store-table.cpp
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/lib/table.cpp
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/lib/table.cpp
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/lib/version.h.in
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/lib/version.h.in
--- a/hdl/ip_cores/wrabbit/modules/wr_eca/wr_eca.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_eca/wr_eca.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/Manifest.py
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/Manifest.py
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/build_wb.sh
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/build_wb.sh
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/endpoint_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/endpoint_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/endpoint_private_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/endpoint_private_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_1000basex_pcs.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_1000basex_pcs.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_autonegotiation.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_autonegotiation.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_crc32_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_crc32_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_flow_control.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_flow_control.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_leds_controller.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_leds_controller.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_packet_filter.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_packet_filter.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_registers_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_registers_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rmon_counters.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rmon_counters.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rtu_header_extract.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rtu_header_extract.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_buffer.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_buffer.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_bypass_queue.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_bypass_queue.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_crc_size_check.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_crc_size_check.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_early_address_match.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_early_address_match.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_oob_insert.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_oob_insert.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_path.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_path.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_vlan_unit.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_vlan_unit.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_wb_master.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_wb_master.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_sync_detect.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_sync_detect.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_sync_detect_16bit.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_sync_detect_16bit.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_timestamping_unit.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_timestamping_unit.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_ts_counter.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_ts_counter.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_framer.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_framer.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_header_processor.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_header_processor.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_wishbone_controller.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_wishbone_controller.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_wishbone_controller.wb
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/ep_wishbone_controller.wb
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/pcs_regs.wb
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/pcs_regs.wb
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/wr_endpoint.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/wr_endpoint.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_endpoint/xwr_endpoint.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_endpoint/xwr_endpoint.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_mini_nic/Manifest.py
+++ b/hdl/ip_cores/wrabbit/modules/wr_mini_nic/Manifest.py
--- a/hdl/ip_cores/wrabbit/modules/wr_mini_nic/build_wb.sh
+++ b/hdl/ip_cores/wrabbit/modules/wr_mini_nic/build_wb.sh
--- a/hdl/ip_cores/wrabbit/modules/wr_mini_nic/mini_nic.wb
+++ b/hdl/ip_cores/wrabbit/modules/wr_mini_nic/mini_nic.wb
--- a/hdl/ip_cores/wrabbit/modules/wr_mini_nic/minic_packet_buffer.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_mini_nic/minic_packet_buffer.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_mini_nic/minic_wb_slave.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_mini_nic/minic_wb_slave.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_mini_nic/wr_mini_nic.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_mini_nic/wr_mini_nic.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_mini_nic/xwr_mini_nic.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_mini_nic/xwr_mini_nic.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_pps_gen/Manifest.py
+++ b/hdl/ip_cores/wrabbit/modules/wr_pps_gen/Manifest.py
--- a/hdl/ip_cores/wrabbit/modules/wr_pps_gen/build_wb.sh
+++ b/hdl/ip_cores/wrabbit/modules/wr_pps_gen/build_wb.sh
--- a/hdl/ip_cores/wrabbit/modules/wr_pps_gen/pps_gen_regs.h
+++ b/hdl/ip_cores/wrabbit/modules/wr_pps_gen/pps_gen_regs.h
--- a/hdl/ip_cores/wrabbit/modules/wr_pps_gen/pps_gen_wb.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_pps_gen/pps_gen_wb.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_pps_gen/pps_gen_wb.wb
+++ b/hdl/ip_cores/wrabbit/modules/wr_pps_gen/pps_gen_wb.wb
--- a/hdl/ip_cores/wrabbit/modules/wr_pps_gen/wr_pps_gen.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_pps_gen/wr_pps_gen.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_pps_gen/xwr_pps_gen.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_pps_gen/xwr_pps_gen.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_si57x_interface/Manifest.py
+++ b/hdl/ip_cores/wrabbit/modules/wr_si57x_interface/Manifest.py
--- a/hdl/ip_cores/wrabbit/modules/wr_si57x_interface/si570_if_wb.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_si57x_interface/si570_if_wb.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_si57x_interface/si570_if_wb.wb
+++ b/hdl/ip_cores/wrabbit/modules/wr_si57x_interface/si570_if_wb.wb
--- a/hdl/ip_cores/wrabbit/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_si57x_interface/wr_si57x_interface.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_si57x_interface/wr_si57x_interface.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_si57x_interface/xwr_si57x_interface.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_si57x_interface/xwr_si57x_interface.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/Manifest.py
+++ b/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/Manifest.py
--- a/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/build_wb.sh
+++ b/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/build_wb.sh
--- a/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/softpll_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/softpll_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/spll_bangbang_pd.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/spll_bangbang_pd.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/spll_period_detect.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/spll_period_detect.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/spll_wb_slave.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/spll_wb_slave.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/spll_wb_slave.wb
+++ b/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/spll_wb_slave.wb
--- a/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/wr_softpll_ng.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/wr_softpll_ng.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/xwr_softpll_ng.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_softpll_ng/xwr_softpll_ng.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_tbi_phy/Manifest.py
+++ b/hdl/ip_cores/wrabbit/modules/wr_tbi_phy/Manifest.py
--- a/hdl/ip_cores/wrabbit/modules/wr_tbi_phy/dec_8b10b.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_tbi_phy/dec_8b10b.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_tbi_phy/disparity_gen_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_tbi_phy/disparity_gen_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_tbi_phy/enc_8b10b.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_tbi_phy/enc_8b10b.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_tbi_phy/wr_tbi_phy.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_tbi_phy/wr_tbi_phy.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_tlu/Manifest.py
+++ b/hdl/ip_cores/wrabbit/modules/wr_tlu/Manifest.py
--- a/hdl/ip_cores/wrabbit/modules/wr_tlu/fake_timestamp.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_tlu/fake_timestamp.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_tlu/wb_cores_pkg_gsi.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_tlu/wb_cores_pkg_gsi.vhd
--- a/hdl/ip_cores/wrabbit/modules/wr_tlu/wb_timestamp_latch.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wr_tlu/wb_timestamp_latch.vhd
--- a/hdl/ip_cores/wrabbit/modules/wrc_core/Manifest.py
+++ b/hdl/ip_cores/wrabbit/modules/wrc_core/Manifest.py
--- a/hdl/ip_cores/wrabbit/modules/wrc_core/build_wb.sh
+++ b/hdl/ip_cores/wrabbit/modules/wrc_core/build_wb.sh
--- a/hdl/ip_cores/wrabbit/modules/wrc_core/wb_reset.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wrc_core/wb_reset.vhd
--- a/hdl/ip_cores/wrabbit/modules/wrc_core/wr_core.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wrc_core/wr_core.vhd
--- a/hdl/ip_cores/wrabbit/modules/wrc_core/wrc_dpram.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wrc_core/wrc_dpram.vhd
--- a/hdl/ip_cores/wrabbit/modules/wrc_core/wrc_periph.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wrc_core/wrc_periph.vhd
--- a/hdl/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_regs.h
+++ b/hdl/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_regs.h
--- a/hdl/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_wb.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_wb.vhd
--- a/hdl/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_wb.wb
+++ b/hdl/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_wb.wb
--- a/hdl/ip_cores/wrabbit/modules/wrc_core/wrcore_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wrc_core/wrcore_pkg.vhd
--- a/hdl/ip_cores/wrabbit/modules/wrc_core/xwr_core.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wrc_core/xwr_core.vhd
--- a/hdl/ip_cores/wrabbit/modules/wrc_core/xwr_syscon_wb.vhd
+++ b/hdl/ip_cores/wrabbit/modules/wrc_core/xwr_syscon_wb.vhd
--- a/hdl/ip_cores/wrabbit/platform/Manifest.py
+++ b/hdl/ip_cores/wrabbit/platform/Manifest.py
--- a/hdl/ip_cores/wrabbit/platform/altera/Manifest.py
+++ b/hdl/ip_cores/wrabbit/platform/altera/Manifest.py
--- a/hdl/ip_cores/wrabbit/platform/altera/altera_butis.vhd
+++ b/hdl/ip_cores/wrabbit/platform/altera/altera_butis.vhd
--- a/hdl/ip_cores/wrabbit/platform/altera/altera_phase.vhd
+++ b/hdl/ip_cores/wrabbit/platform/altera/altera_phase.vhd
--- a/hdl/ip_cores/wrabbit/platform/altera/altera_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/platform/altera/altera_pkg.vhd
--- a/hdl/ip_cores/wrabbit/platform/altera/altera_reset.vhd
+++ b/hdl/ip_cores/wrabbit/platform/altera/altera_reset.vhd
--- a/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/.gitignore
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/.gitignore
--- a/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/Manifest.py
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/Manifest.py
--- a/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/arria2_pll.qip
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/arria2_pll.qip
--- a/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/arria2_pll.tcl
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/arria2_pll.tcl
--- a/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/dmtd_pll.txt
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/dmtd_pll.txt
--- a/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/ref_pll.txt
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/ref_pll.txt
--- a/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/sys_pll.txt
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria2_pll/sys_pll.txt
--- a/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/.gitignore
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/.gitignore
--- a/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/Manifest.py
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/Manifest.py
--- a/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/arria5_pll.qip
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/arria5_pll.qip
--- a/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/arria5_pll.tcl
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/arria5_pll.tcl
--- a/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/dmtd_pll5.txt
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/dmtd_pll5.txt
--- a/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/ref_pll5.txt
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/ref_pll5.txt
--- a/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/sys_pll5.txt
+++ b/hdl/ip_cores/wrabbit/platform/altera/arria5_pll/sys_pll5.txt
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/.gitignore
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/.gitignore
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/Manifest.py
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/Manifest.py
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/arria2_phy.txt
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/arria2_phy.txt
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/arria2_phy_reconf.txt
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/arria2_phy_reconf.txt
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/wr_arria2_phy.qip
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/wr_arria2_phy.qip
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/wr_arria2_phy.tcl
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/wr_arria2_phy.tcl
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/.gitignore
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/.gitignore
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/Manifest.py
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/Manifest.py
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/arria5_phy.txt
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/arria5_phy.txt
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/arria5_phy_reconf.txt
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/arria5_phy_reconf.txt
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/wr_arria5_phy.qip
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/wr_arria5_phy.qip
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/wr_arria5_phy.tcl
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/wr_arria5_phy.tcl
--- a/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd
+++ b/hdl/ip_cores/wrabbit/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd
--- a/hdl/ip_cores/wrabbit/platform/xilinx/Manifest.py
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/Manifest.py
--- a/hdl/ip_cores/wrabbit/platform/xilinx/chipscope/Manifest.py
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/chipscope/Manifest.py
--- a/hdl/ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_icon.ngc
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_icon.ngc
--- a/hdl/ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_ila.ngc
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_ila.ngc
--- a/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/Manifest.py
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/Manifest.py
--- a/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
--- a/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
--- a/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd
--- a/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtx_reset.vhd
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtx_reset.vhd
--- a/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd
--- a/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
--- a/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile_spartan6.vhd
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile_spartan6.vhd
--- a/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd
--- a/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
--- a/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spec.vhd
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spec.vhd
--- a/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
--- a/hdl/ip_cores/wrabbit/platform/xilinx/wr_xilinx_pkg.vhd
+++ b/hdl/ip_cores/wrabbit/platform/xilinx/wr_xilinx_pkg.vhd