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FMC TDC 1ns 5cha - Gateware
Commit 4d5b3487 authored by egousiou's avatar egousiou
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folders restructuring; one core for both spec and svec 

git-svn-id: http://svn.ohwr.org/fmc-tdc@123 85dfdc96-de2c-444c-878d-45b388be74a9
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hdl/spec/syn/blk_mem_circ_buff_v6_4.ngc deleted 100644 → 0
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#
# Constraints generated by Synplify Premier maprc, Build 943R
# Product Version "F-2012.03"
#
# Location Constraints
NET "rst_n_a_i" LOC="N20" ;
NET "p2l_clk_p_i" LOC="M20" ;
NET "p2l_clk_n_i" LOC="M19" ;
NET "p2l_data_i(0)" LOC="K20" ;
NET "p2l_data_i(1)" LOC="H22" ;
NET "p2l_data_i(2)" LOC="H21" ;
NET "p2l_data_i(3)" LOC="L17" ;
NET "p2l_data_i(4)" LOC="K17" ;
NET "p2l_data_i(5)" LOC="G22" ;
NET "p2l_data_i(6)" LOC="G20" ;
NET "p2l_data_i(7)" LOC="K18" ;
NET "p2l_data_i(8)" LOC="K19" ;
NET "p2l_data_i(9)" LOC="H20" ;
NET "p2l_data_i(10)" LOC="J19" ;
NET "p2l_data_i(11)" LOC="E22" ;
NET "p2l_data_i(12)" LOC="E20" ;
NET "p2l_data_i(13)" LOC="F22" ;
NET "p2l_data_i(14)" LOC="F21" ;
NET "p2l_data_i(15)" LOC="H19" ;
NET "p2l_dframe_i" LOC="J22" ;
NET "p2l_valid_i" LOC="L19" ;
NET "p2l_rdy_o" LOC="J16" ;
NET "p_wr_req_i(0)" LOC="M22" ;
NET "p_wr_req_i(1)" LOC="M21" ;
NET "p_wr_rdy_o(0)" LOC="L15" ;
NET "p_wr_rdy_o(1)" LOC="K16" ;
NET "rx_error_o" LOC="J17" ;
NET "vc_rdy_i(0)" LOC="B21" ;
NET "vc_rdy_i(1)" LOC="B22" ;
NET "l2p_clk_p_o" LOC="K21" ;
NET "l2p_clk_n_o" LOC="K22" ;
NET "l2p_data_o(0)" LOC="P16" ;
NET "l2p_data_o(1)" LOC="P21" ;
NET "l2p_data_o(2)" LOC="P18" ;
NET "l2p_data_o(3)" LOC="T20" ;
NET "l2p_data_o(4)" LOC="V21" ;
NET "l2p_data_o(5)" LOC="V19" ;
NET "l2p_data_o(6)" LOC="W22" ;
NET "l2p_data_o(7)" LOC="Y22" ;
NET "l2p_data_o(8)" LOC="P22" ;
NET "l2p_data_o(9)" LOC="R22" ;
NET "l2p_data_o(10)" LOC="T21" ;
NET "l2p_data_o(11)" LOC="T19" ;
NET "l2p_data_o(12)" LOC="V22" ;
NET "l2p_data_o(13)" LOC="V20" ;
NET "l2p_data_o(14)" LOC="W20" ;
NET "l2p_data_o(15)" LOC="Y21" ;
NET "l2p_dframe_o" LOC="U22" ;
NET "l2p_valid_o" LOC="T18" ;
NET "l2p_edb_o" LOC="U20" ;
NET "l2p_rdy_i" LOC="U19" ;
NET "l_wr_rdy_i(0)" LOC="R20" ;
NET "l_wr_rdy_i(1)" LOC="T22" ;
NET "p_rd_d_rdy_i(0)" LOC="N16" ;
NET "p_rd_d_rdy_i(1)" LOC="P19" ;
NET "tx_error_i" LOC="M17" ;
NET "irq_p_o" LOC="U16" ;
NET "pll_sclk_o" LOC="AA16" ;
NET "pll_sdi_o" LOC="AA18" ;
NET "pll_cs_o" LOC="Y17" ;
NET "pll_dac_sync_o" LOC="AB16" ;
NET "pll_sdo_i" LOC="AB18" ;
NET "pll_status_i" LOC="Y18" ;
NET "tdc_clk_p_i" LOC="L20" ;
NET "tdc_clk_n_i" LOC="L22" ;
NET "acam_refclk_p_i" LOC="E16" ;
NET "acam_refclk_n_i" LOC="F16" ;
NET "start_from_fpga_o" LOC="W17" ;
NET "err_flag_i" LOC="V11" ;
NET "int_flag_i" LOC="W11" ;
NET "start_dis_o" LOC="T15" ;
NET "stop_dis_o" LOC="U15" ;
NET "data_bus_io(0)" LOC="W6" ;
NET "data_bus_io(1)" LOC="Y6" ;
NET "data_bus_io(2)" LOC="V7" ;
NET "data_bus_io(3)" LOC="W8" ;
NET "data_bus_io(4)" LOC="T8" ;
NET "data_bus_io(5)" LOC="AA12" ;
NET "data_bus_io(6)" LOC="U8" ;
NET "data_bus_io(7)" LOC="AB12" ;
NET "data_bus_io(8)" LOC="Y5" ;
NET "data_bus_io(9)" LOC="AB5" ;
NET "data_bus_io(10)" LOC="R9" ;
NET "data_bus_io(11)" LOC="R8" ;
NET "data_bus_io(12)" LOC="AA6" ;
NET "data_bus_io(13)" LOC="AB6" ;
NET "data_bus_io(14)" LOC="U9" ;
NET "data_bus_io(15)" LOC="V9" ;
NET "data_bus_io(16)" LOC="Y7" ;
NET "data_bus_io(17)" LOC="AB7" ;
NET "data_bus_io(18)" LOC="AA8" ;
NET "data_bus_io(19)" LOC="AB8" ;
NET "data_bus_io(20)" LOC="T10" ;
NET "data_bus_io(21)" LOC="U10" ;
NET "data_bus_io(22)" LOC="W10" ;
NET "data_bus_io(23)" LOC="Y10" ;
NET "data_bus_io(24)" LOC="Y9" ;
NET "data_bus_io(25)" LOC="AB9" ;
NET "data_bus_io(26)" LOC="AA4" ;
NET "data_bus_io(27)" LOC="AB4" ;
NET "address_o(0)" LOC="T12" ;
NET "address_o(1)" LOC="U12" ;
NET "address_o(2)" LOC="Y15" ;
NET "address_o(3)" LOC="AB15" ;
NET "cs_n_o" LOC="AB17" ;
NET "oe_n_o" LOC="V13" ;
NET "rd_n_o" LOC="AB13" ;
NET "wr_n_o" LOC="Y13" ;
NET "ef1_i" LOC="W12" ;
NET "ef2_i" LOC="Y12" ;
NET "enable_inputs_o" LOC="C19" ;
NET "term_en_1_o" LOC="Y11" ;
NET "term_en_2_o" LOC="AB11" ;
NET "term_en_3_o" LOC="R11" ;
NET "term_en_4_o" LOC="T11" ;
NET "term_en_5_o" LOC="R13" ;
NET "tdc_led_status_o" LOC="T14" ;
NET "tdc_led_trig1_o" LOC="W18" ;
NET "tdc_led_trig2_o" LOC="B20" ;
NET "tdc_led_trig3_o" LOC="A20" ;
NET "tdc_led_trig4_o" LOC="D17" ;
NET "tdc_led_trig5_o" LOC="C18" ;
NET "spec_clk_i" LOC="H12" ;
NET "carrier_one_wire_b" LOC="D4" ;
NET "sys_scl_b" LOC="F7" ;
NET "sys_sda_b" LOC="F8" ;
NET "mezz_one_wire_b" LOC="A19" ;
NET "pcb_ver_i(0)" LOC="P5" ;
NET "pcb_ver_i(1)" LOC="P4" ;
NET "pcb_ver_i(2)" LOC="AA2" ;
NET "pcb_ver_i(3)" LOC="AA1" ;
NET "prsnt_m2c_n_i" LOC="AB14" ;
NET "spec_led_green_o" LOC="E5" ;
NET "spec_led_red_o" LOC="D5" ;
NET "spec_aux0_i" LOC="C22" ;
NET "spec_aux1_i" LOC="D21" ;
NET "spec_aux2_o" LOC="G19" ;
NET "spec_aux3_o" LOC="F20" ;
NET "spec_aux4_o" LOC="F18" ;
NET "spec_aux5_o" LOC="C20" ;
# End of generated constraints
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#
# Constraints generated by Synplify Premier maprc, Build 943R
# Product Version "F-2012.03"
#
# Period Constraints
#Begin clock constraints
# 1003 : define_clock {p:acam_refclk_p_i} -name {acam_refclk31_25} -freq {31.25} -clockgroup {default_clkgroup30__3}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "acam_refclk_p_i" TNM_NET = "acam_refclk_p_i";
TIMESPEC "TS_acam_refclk_p_i" = PERIOD "acam_refclk_p_i" 32.000 ns HIGH 50.00%;
# 1004 : define_clock {n:gnum_interface_block.cmp_clk_in.rx_bufg_pll_x1} -name {gnum_clk200} -freq {200} -clockgroup {default_clkgroup31__4}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "gnum_interface_block.sys_clk" TNM_NET = "gnum_interface_block_sys_clk";
TIMESPEC "TS_gnum_interface_block_sys_clk" = PERIOD "gnum_interface_block_sys_clk" 5.000 ns HIGH 50.00%;
# 1002 : define_clock {p:spec_clk_i} -name {spec_clk20} -freq {20} -clockgroup {default_clkgroup29__2}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "spec_clk_i" TNM_NET = "spec_clk_i";
TIMESPEC "TS_spec_clk_i" = PERIOD "spec_clk_i" 50.000 ns HIGH 50.00%;
# 1001 : define_clock {p:tdc_clk_p_i} -name {tdc_clk125p} -freq {125} -clockgroup {default_clkgroup28__1}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "tdc_clk_p_i" TNM_NET = "tdc_clk_p_i";
TIMESPEC "TS_tdc_clk_p_i" = PERIOD "tdc_clk_p_i" 8.000 ns HIGH 50.00%;
#End clock constraints
# 1008 : define_false_path -from {p:spec_aux0_i}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "spec_aux0_i" TNM = "from_1008_0";
TIMESPEC "TS_1008_0" = FROM "from_1008_0" TIG;
# 1009 : define_false_path -from {p:spec_aux1_i}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "spec_aux1_i" TNM = "from_1009_0";
TIMESPEC "TS_1009_0" = FROM "from_1009_0" TIG;
# 1010 : define_false_path -to {p:spec_aux2_o}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "spec_aux2_o" TNM = "to_1010_0";
TIMESPEC "TS_1010_0" = TO "to_1010_0" TIG;
# 1011 : define_false_path -to {p:spec_aux3_o}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "spec_aux3_o" TNM = "to_1011_0";
TIMESPEC "TS_1011_0" = TO "to_1011_0" TIG;
# 1012 : define_false_path -to {p:spec_aux4_o}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "spec_aux4_o" TNM = "to_1012_0";
TIMESPEC "TS_1012_0" = TO "to_1012_0" TIG;
# 1013 : define_false_path -to {p:spec_aux5_o}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "spec_aux5_o" TNM = "to_1013_0";
TIMESPEC "TS_1013_0" = TO "to_1013_0" TIG;
# 1014 : define_false_path -to {p:spec_led_green_o}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "spec_led_green_o" TNM = "to_1014_0";
TIMESPEC "TS_1014_0" = TO "to_1014_0" TIG;
# 1015 : define_false_path -to {p:spec_led_red_o}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "spec_led_red_o" TNM = "to_1015_0";
TIMESPEC "TS_1015_0" = TO "to_1015_0" TIG;
# 1016 : define_false_path -to {p:tdc_led_status_o}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "tdc_led_status_o" TNM = "to_1016_0";
TIMESPEC "TS_1016_0" = TO "to_1016_0" TIG;
# 1017 : define_false_path -to {p:tdc_led_trig1_o}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "tdc_led_trig1_o" TNM = "to_1017_0";
TIMESPEC "TS_1017_0" = TO "to_1017_0" TIG;
# 1018 : define_false_path -to {p:tdc_led_trig2_o}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "tdc_led_trig2_o" TNM = "to_1018_0";
TIMESPEC "TS_1018_0" = TO "to_1018_0" TIG;
# 1019 : define_false_path -to {p:tdc_led_trig3_o}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "tdc_led_trig3_o" TNM = "to_1019_0";
TIMESPEC "TS_1019_0" = TO "to_1019_0" TIG;
# 1020 : define_false_path -to {p:tdc_led_trig4_o}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "tdc_led_trig4_o" TNM = "to_1020_0";
TIMESPEC "TS_1020_0" = TO "to_1020_0" TIG;
# 1021 : define_false_path -to {p:tdc_led_trig5_o}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "tdc_led_trig5_o" TNM = "to_1021_0";
TIMESPEC "TS_1021_0" = TO "to_1021_0" TIG;
# 1022 : define_false_path -from {p:rst_n_a_i}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
NET "rst_n_a_i" TNM = "from_1022_0";
TIMESPEC "TS_1022_0" = FROM "from_1022_0" TIG;
# 1023 : define_false_path -from {i:gnum_interface_block.rst_reg}
# c:\fmc_tdc\evas_fmc_tdc\syn\tdc_syn_constraints.sdc
INST "gnum_interface_block.rst_reg" TNM = "from_1023_0";
TIMESPEC "TS_1023_0" = FROM "from_1023_0" TIG;
# Unused constraints (intentionally commented out)
# define_multicycle_path -from { p:data_bus_io[27:0] } { 3 }
# define_multicycle_path -to { p:data_bus_io[27:0] } { 3 }
# define_multicycle_path -to { p:address_o[3:0] } { 3 }
# Location Constraints
PIN "tdc_core.clks_rsts_mgment.spec_clk_gbuf.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "tdc_core.clks_rsts_mgment.tdc_clk125_gbuf.O" CLOCK_DEDICATED_ROUTE = FALSE;
# End of generated constraints
hdl/spec/syn/tdc_par_script.tcl deleted 100644 → 0
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cd C:/FMC_TDC/evas_fmc_tdc/syn
ngdbuild -uc synplicity.ucf syn_tdc.edf
map -detail -w -timing -ol high syn_tdc.ngd
par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf
trce -v 32 -u par_tdc.ncd syn_tdc.pcf -o timing_report
bitgen -w par_tdc.ncd tdc
#bitgen -w -g Binary:Yes par_tdc.ncd tdc
cd C:/FMC_TDC/evas_fmc_tdc/syn;ngdbuild -uc synplicity.ucf syn_tdc.edf;map -detail -w -timing -ol high syn_tdc.ngd;par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf;bitgen -w par_tdc.ncd tdc
\ No newline at end of file
hdl/spec/syn/tdc_syn.prj deleted 100644 → 0
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#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn.prj
#-- Written on Fri Jul 4 10:00:00 2011
#project files
add_file -include "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
add_file -include "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ndf"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/genram_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/wishbone_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/gencores_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/sdb_meta_pkg.vhd"
add_file -vhdl -lib work "../src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/generic_async_fifo_wrapper.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_ser.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_des.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/pulse_sync_rtl.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core.vhd"
add_file -vhdl -lib work "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_crossbar/sdb_rom.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_crossbar/xwb_crossbar.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_crossbar/xwb_sdb_crossbar.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_slave_adapter/wb_slave_adapter.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/i2c_master_bit_ctrl.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/i2c_master_byte_ctrl.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/i2c_master_top.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/wb_i2c_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/xwb_i2c_master.vhd"
add_file -verilog -lib work "../src/ip_cores/wb_onewire_master/sockit_owm.v"
add_file -vhdl -lib work "../src/ip_cores/wb_onewire_master/wb_onewire_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_onewire_master/xwb_onewire_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_irq_controller/irq_controller_regs.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_irq_controller/irq_controller.vhd"
add_file -vhdl -lib work "../src/ip_cores/carrier_csr.vhd"
add_file -vhdl -lib work "../src/rtl/fmc_tdc_core.vhd"
add_file -vhdl -lib work "../src/rtl/free_counter.vhd"
add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/decr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clks_rsts_manager.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_retrig_ctrl.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "../src/rtl/circular_buffer.vhd"
add_file -vhdl -lib work "../src/rtl/irq_generator.vhd"
add_file -vhdl -lib work "../src/rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "../src/rtl/leds_manager.vhd"
add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
add_file -constraint -lib work "./tdc_syn_constraints.sdc"
#implementation attributes (Verilog)
set_option -vlog_std v2001
set_option -project_relative_includes 1
#implementation: "syn"
impl -add syn -type fpga
impl -active "syn"
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -3
set_option -part_companion ""
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
set_option -synthesis_onoff_pragma 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
set_option -no_sequential_opt 0
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -num_critical_paths 5
# Xilinx options
set_option -run_prop_extract 1
set_option -maxfan 500
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -enable_prepacking 1
set_option -enhance_optimization 1
# NFilter (Netlist restructure)
set_option -enable_nfilter 1
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./syn_tdc.edf"
#project -result_file "./test_tdc_pll/syn_tdc.edf"
#project -result_file "./test_tdc_acam/syn_tdc.edf"
#project -run -fg synthesis
#project -run -fg timing
\ No newline at end of file
hdl/spec/syn/tdc_syn_constraints.sdc deleted 100644 → 0
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hdl/spec/syn/tdc_syn_script.prj deleted 100644 → 0
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#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn_script.prj
#-- Written on Fri Jul 4 10:00:00 2011
#project files
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -include "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_ser_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_des_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "../src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../src/rtl/free_counter.vhd"
add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_retrigger_control.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "../src/rtl/circular_buffer.vhd"
add_file -vhdl -lib work "../src/rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
#add_file -vhdl -lib work "../src/rtl/test_tdc_pll/top_test_pll.vhd"
#add_file -vhdl -lib work "../src/rtl/test_tdc_acam/top_test_acam.vhd"
add_file -constraint -lib work "./tdc_syn_constraints.sdc"
#implementation attributes (Verilog)
set_option -vlog_std v2001
set_option -project_relative_includes 1
#implementation: "syn"
impl -add syn -type fpga
impl -active "syn"
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -3
set_option -part_companion ""
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
set_option -synthesis_onoff_pragma 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
set_option -no_sequential_opt 0
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -num_critical_paths 5
# Xilinx options
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -enable_prepacking 1
set_option -enhance_optimization 1
# NFilter (Netlist restructure)
set_option -enable_nfilter 1
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./syn_tdc.edf"
#project -result_file "./test_tdc_pll/syn_tdc.edf"
#project -result_file "./test_tdc_acam/syn_tdc.edf"
#project -run -fg synthesis
#project -run -fg timing
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