Skip to content

F
FMC TDC 1ns 5cha - Gateware
Commit 5765c94d authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

hdl: SPEC top level with refurbished TDC core

parent caaf87ad
Hide whitespace changes
Inline Side-by-side
Showing with 3429 additions and 73855 deletions
gn4124-core @ ffea5479
Subproject commit e0dcb3f9a3e6804f64c544743bdf46b5fcbbefab
Subproject commit ffea5479190c09938cbba9b7076953c5c41645f3
vme64x-core @ d8ae9867
Subproject commit e98eb58ca8757be8fdf4117d0d1d1c8bb2e238bc
Subproject commit d8ae98675b15a5dc6bf5cc9e7e3fcbdd266187f7
hdl/syn/spec/Manifest.py 0 → 100644
View file @ 5765c94d
target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "wr_spec_tdc"
syn_project = "wr_spec_tdc.xise"
syn_tool = "ise"
top_module = "wr_spec_tdc"
modules = { "local" : [ "../../top/spec" ] }
hdl/syn/spec/no_wrabbit/spec_tdc.par deleted 100644 → 0
View file @ caaf87ad
Release 13.4 par O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
PCBE13136:: Tue Jul 08 10:29:26 2014
par -w -intstyle ise -ol high -xe c -mt off spec_tdc_map.ncd spec_tdc.ncd
spec_tdc.pcf
Constraints file: spec_tdc.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\EDA\Xilinx\v13_4\ISE_DS\ISE\.
"spec_tdc" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
INFO:Par:338 -
Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is intended to be used for designs that are
not meeting timing but where the designer wants the tools to continue iterating on the design until no further design
speed improvements are possible. This can result in very long runtimes since the tools will continue improving the
design even if the time specs can not be met. If you are looking for the best possible design speed available from a
long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design
speed improvements have shrunk to the point that the time specs are not expected to be met.
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.21 2012-01-07".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 3,584 out of 54,576 6%
Number used as Flip Flops: 3,559
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,881 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251
Number using O5 output only: 328
Number using O5 and O6: 1,202
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 2
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 98
Number with same-slice register load: 53
Number with same-slice carry load: 45
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,510 out of 6,822 22%
Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,827
Number with an unused Flip Flop: 1,538 out of 4,827 31%
Number with an unused LUT: 946 out of 4,827 19%
Number of fully used LUT-FF pairs: 2,343 out of 4,827 48%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 134 out of 296 45%
Number of LOCed IOBs: 134 out of 134 100%
IOB Flip Flops: 55
Specific Feature Utilization:
Number of RAMB16BWERs: 11 out of 116 9%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 60 out of 376 15%
Number used as ILOGIC2s: 40
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
Number used as IODELAY2s: 2
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 35 out of 376 9%
Number used as OLOGIC2s: 15
Number used as OSERDES2s: 20
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 11 secs
Finished initial Timing Analysis. REAL time: 11 secs
WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p_wr_req_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p_wr_req_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 24084 unrouted; REAL time: 13 secs
Phase 2 : 20731 unrouted; REAL time: 16 secs
Phase 3 : 8906 unrouted; REAL time: 27 secs
Phase 4 : 8912 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 30 secs
Updating file: spec_tdc.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 47 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Total REAL time to Router completion: 49 secs
Total CPU time to Router completion: 46 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_125m | BUFGMUX_X3Y7| No | 944 | 0.551 | 1.762 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X3Y13| No | 235 | 0.518 | 1.729 |
+---------------------+--------------+------+------+------------+-------------+
|clk_20m_vcxo_buf_BUF | | | | | |
| G | BUFGMUX_X2Y3| No | 26 | 0.519 | 1.737 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/io_c | | | | | |
| lk | Local| | 41 | 0.064 | 1.562 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc_mezz/cmp_tdc | | | | | |
|_core/data_engine_bl | | | | | |
|ock/engine_st[3]_PWR | | | | | |
| _227_o_Mux_41_o | Local| | 2 | 0.000 | 0.469 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 8
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc | SETUP | 0.051ns| 7.949ns| 0| 0
_clk_125m_n_i" 8 ns HIGH 50% | HOLD | 0.395ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.248ns| 4.752ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.043ns| | 0| 0
core_cmp_clk_in_rx_pllout_x1_0" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
PERIOD TIMEGRP "cmp_gn4124_core_ | | | | |
cmp_clk_in_buf_P_clk" TS_p2l_clk_p_i HIGH | | | | |
50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
= PERIOD TIMEGRP "cmp_gn4124_cor | | | | |
e_cmp_clk_in_buf_P_clk_0" TS_p2l_clk_n_i | | | | |
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | MINPERIOD | 1.876ns| 3.124ns| 0| 0
1 = PERIOD TIMEGRP "cmp_gn4124_co | | | | |
re_cmp_clk_in_rx_pllout_x1" TS_cm | | | | |
p_gn4124_core_cmp_clk_in_buf_P_clk PHASE | | | | |
1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clk_p_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p_i" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clk_n_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
n_i" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TStdc_clk_125m_p_i = PERIOD TIMEGRP "tdc_ | MINPERIOD | 4.876ns| 3.124ns| 0| 0
clk_125m_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_2 | SETUP | 44.742ns| 5.258ns| 0| 0
0m_vcxo_i" 50 ns HIGH 50% | HOLD | 0.369ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
s_int = PERIOD TIMEGRP "cmp_gn412 | | | | |
4_core_cmp_clk_in_rx_pllout_xs_int" | | | | |
TS_cmp_gn4124_core_cmp_clk_in_buf_P_cl | | | | |
k / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
s_int_0 = PERIOD TIMEGRP "cmp_gn4 | | | | |
124_core_cmp_clk_in_rx_pllout_xs_int_0" | | | | |
TS_cmp_gn4124_core_cmp_clk_in_buf_ | | | | |
P_clk_0 / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_p2l_clk_p_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clk_p_i | 5.000ns| 0.925ns| 3.124ns| 0| 0| 0| 0|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 3.124ns| 0| 0| 0| 0|
| buf_P_clk | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 3.124ns| N/A| 0| 0| 0| 0|
| _rx_pllout_x1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_p2l_clk_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clk_n_i | 5.000ns| 0.925ns| 4.752ns| 0| 0| 0| 5842|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.752ns| 0| 0| 0| 5842|
| buf_P_clk_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.752ns| N/A| 0| 0| 5842| 0|
| _rx_pllout_x1_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 53 secs
Total CPU time to PAR completion: 48 secs
Peak Memory Usage: 333 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 7
Number of info messages: 2
Writing design to file spec_tdc.ncd
PAR done!
hdl/syn/spec/no_wrabbit/spec_tdc.twr deleted 100644 → 0
View file @ caaf87ad
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/no_wrabbit/spec_tdc.xise deleted 100644 → 0
View file @ caaf87ad
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/no_wrabbit/spec_tdc_map.map deleted 100644 → 0
View file @ caaf87ad
Release 13.4 Map O.87xd (nt)
Xilinx Map Application Log File for Design 'spec_tdc'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
off -pr b -lc off -power off -o spec_tdc_map.ncd spec_tdc.ngd spec_tdc.pcf
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jul 08 10:27:13 2014
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 21 secs
Total CPU time at the beginning of Placer: 17 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:de9a1ea9) REAL time: 37 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:de9a1ea9) REAL time: 38 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:de9a1ea9) REAL time: 38 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:46e77852) REAL time: 1 mins 9 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 9 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:46e77852) REAL time: 1 mins 9 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 10 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 10 secs
Phase 9.8 Global Placement
..................................
........................................................
........................................................
..........................
Phase 9.8 Global Placement (Checksum:a3a2a52d) REAL time: 1 mins 42 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:a3a2a52d) REAL time: 1 mins 42 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:8078f7ee) REAL time: 1 mins 58 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:8078f7ee) REAL time: 1 mins 58 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:d7bfac99) REAL time: 1 mins 59 secs
Total REAL time to Placer completion: 2 mins 6 secs
Total CPU time to Placer completion: 1 mins 47 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_227_o_Mux_41_o
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 1
Slice Logic Utilization:
Number of Slice Registers: 3,584 out of 54,576 6%
Number used as Flip Flops: 3,559
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,881 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251
Number using O5 output only: 328
Number using O5 and O6: 1,202
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 2
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 98
Number with same-slice register load: 53
Number with same-slice carry load: 45
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,510 out of 6,822 22%
Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,827
Number with an unused Flip Flop: 1,538 out of 4,827 31%
Number with an unused LUT: 946 out of 4,827 19%
Number of fully used LUT-FF pairs: 2,343 out of 4,827 48%
Number of unique control sets: 129
Number of slice register sites lost
to control set restrictions: 309 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 134 out of 296 45%
Number of LOCed IOBs: 134 out of 134 100%
IOB Flip Flops: 55
Specific Feature Utilization:
Number of RAMB16BWERs: 11 out of 116 9%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 60 out of 376 15%
Number used as ILOGIC2s: 40
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
Number used as IODELAY2s: 2
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 35 out of 376 9%
Number used as OLOGIC2s: 15
Number used as OSERDES2s: 20
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.70
Peak Memory Usage: 355 MB
Total REAL time to MAP completion: 2 mins 11 secs
Total CPU time to MAP completion: 1 mins 52 secs
Mapping completed.
See MAP report file "spec_tdc_map.mrp" for details.
hdl/syn/spec/no_wrabbit/spec_tdc_map.mrp deleted 100644 → 0
View file @ caaf87ad
Release 13.4 Map O.87xd (nt)
Xilinx Mapping Report File for Design 'spec_tdc'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
off -pr b -lc off -power off -o spec_tdc_map.ncd spec_tdc.ngd spec_tdc.pcf
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jul 08 10:27:13 2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 1
Slice Logic Utilization:
Number of Slice Registers: 3,584 out of 54,576 6%
Number used as Flip Flops: 3,559
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,881 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251
Number using O5 output only: 328
Number using O5 and O6: 1,202
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 2
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 98
Number with same-slice register load: 53
Number with same-slice carry load: 45
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,510 out of 6,822 22%
Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,827
Number with an unused Flip Flop: 1,538 out of 4,827 31%
Number with an unused LUT: 946 out of 4,827 19%
Number of fully used LUT-FF pairs: 2,343 out of 4,827 48%
Number of unique control sets: 129
Number of slice register sites lost
to control set restrictions: 309 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 134 out of 296 45%
Number of LOCed IOBs: 134 out of 134 100%
IOB Flip Flops: 55
Specific Feature Utilization:
Number of RAMB16BWERs: 11 out of 116 9%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 60 out of 376 15%
Number used as ILOGIC2s: 40
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
Number used as IODELAY2s: 2
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 35 out of 376 9%
Number used as OLOGIC2s: 15
Number used as OSERDES2s: 20
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.70
Peak Memory Usage: 355 MB
Total REAL time to MAP completion: 2 mins 11 secs
Total CPU time to MAP completion: 1 mins 52 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_227_o_Mux_41_o
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network button1_i has no load.
INFO:LIT:395 - The above info message is repeated 142 more times for the
following (max. 5 shown):
button2_i,
tdc_in_fpga_1_i,
tdc_in_fpga_2_i,
tdc_in_fpga_3_i,
tdc_in_fpga_4_i
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
60 block(s) removed
3 block(s) optimized away
169 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" (FF)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" is loadless and has
been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" (ROM)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<5>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_5" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter5" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<5>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv1_INV_0"
(BUF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_8" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter8" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<8>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<6>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_6" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter6" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<6>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<7>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_7" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter7" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<7>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<0>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_0" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<0>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<1>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_1" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter1" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<1>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<2>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_2" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter2" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<2>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<3>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_3" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter3" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<3>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<4>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_4" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter4" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<4>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" (FF)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4-In" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/_n0364_inv1" (ROM)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[10].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[11].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[12].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[13].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[14].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[15].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[1].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[2].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[3].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[4].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[5].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[6].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[7].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[8].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[9].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd25"
(ROM) removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(127)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(126)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(125)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(124)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(123)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(122)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(121)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(120)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(119)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(118)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(117)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(116)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(115)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(114)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(113)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(112)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(111)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(110)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(109)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(108)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(107)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(106)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(105)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(104)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(103)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(102)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(101)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(100)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(99)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(98)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(97)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(96)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(95)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(94)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(93)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(92)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(91)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(90)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(89)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(88)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(87)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(86)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(85)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(84)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(83)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(82)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(81)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(80)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(79)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(78)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(77)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(76)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(75)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(74)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(73)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(72)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(71)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(70)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(69)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(68)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(67)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(66)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(65)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(64)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(63)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(62)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(61)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(60)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(59)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(58)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(57)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(56)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(55)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(54)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(53)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(52)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(51)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(50)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(49)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(48)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(47)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(46)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(45)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(44)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(43)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(42)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(41)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(40)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(39)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(38)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(37)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(36)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(35)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(34)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(33)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(32)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(31)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(30)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(29)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(28)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(27)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(26)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(25)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(24)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(23)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(22)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(21)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(20)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(19)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(18)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(17)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(16)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(15)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(14)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(13)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(12)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(11)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(10)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(9)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(8)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(7)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(6)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(5)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(4)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(3)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(2)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(1)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(0)" is
sourceless and has been removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
GND cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/XST_GND
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| acam_refclk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| acam_refclk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | IFF | | |
| address_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| address_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| address_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| address_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| carrier_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| clk_20m_vcxo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| data_bus_io<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<16> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<17> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<18> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<19> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<20> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<21> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<22> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<23> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<24> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<25> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<26> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<27> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| ef1_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| ef2_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| enable_inputs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| err_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| int_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| irq_p_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| l2p_clk_n_o | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
| l2p_clk_p_o | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
| l2p_data_o<0> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<1> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<2> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<3> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<4> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<5> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<6> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<7> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<8> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<9> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<10> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<11> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<12> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<13> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<14> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<15> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_dframe_o | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_edb_o | IOB | OUTPUT | SSTL18_I | | | | OFF | | |
| l2p_rdy_i | IOB | INPUT | SSTL18_I | | | | IFF | | |
| l2p_valid_o | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l_wr_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| l_wr_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| led_green_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_red_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| mezz_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| mezz_sys_scl_b | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| mezz_sys_sda_b | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| oe_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| p2l_clk_n_i | IOB | INPUT | DIFF_SSTL18_I | | | | | | |
| p2l_clk_p_i | IOB | INPUT | DIFF_SSTL18_I | | | | ISERDES | | VARIABLE |
| p2l_data_i<0> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<1> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<2> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<3> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<4> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<5> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<6> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<7> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<8> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<9> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<10> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<11> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<12> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<13> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<14> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<15> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_dframe_i | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_rdy_o | IOB | OUTPUT | SSTL18_I | | | | | | |
| p2l_valid_i | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p_rd_d_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| p_rd_d_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| p_wr_rdy_o<0> | IOB | OUTPUT | SSTL18_I | | | | | | |
| p_wr_rdy_o<1> | IOB | OUTPUT | SSTL18_I | | | | | | |
| p_wr_req_i<0> | IOB | INPUT | SSTL18_I | | | | | | |
| p_wr_req_i<1> | IOB | INPUT | SSTL18_I | | | | | | |
| pcb_ver_i<0> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<1> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<2> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<3> | IOB | INPUT | LVCMOS15 | | | | | | |
| pll_cs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_dac_sync_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_sdi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_sdo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| prsnt_m2c_n_i | IOB | INPUT | LVCMOS25 | | | | | | |
| rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| rst_n_a_i | IOB | INPUT | LVCMOS18 | | | | | | |
| rx_error_o | IOB | OUTPUT | SSTL18_I | | | | | | |
| start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc_clk_125m_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc_clk_125m_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc_led_status_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc_led_trig1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tx_error_i | IOB | INPUT | SSTL18_I | | | | IFF | | |
| vc_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | | | |
| vc_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | | | |
| wr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
hdl/syn/spec/no_wrabbit/wrc.ram deleted 100644 → 0
View file @ caaf87ad
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/with_wrabbit/wr_spec_tdc.par deleted 100644 → 0
View file @ caaf87ad
Release 13.4 par O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
PCBE13136:: Tue Jul 08 11:06:17 2014
par -w -intstyle ise -ol high -xe c -mt off wr_spec_tdc_map.ncd wr_spec_tdc.ncd
wr_spec_tdc.pcf
Constraints file: wr_spec_tdc.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\EDA\Xilinx\v13_4\ISE_DS\ISE\.
"wr_spec_tdc" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
INFO:Par:338 -
Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is intended to be used for designs that are
not meeting timing but where the designer wants the tools to continue iterating on the design until no further design
speed improvements are possible. This can result in very long runtimes since the tools will continue improving the
design even if the time specs can not be met. If you are looking for the best possible design speed available from a
long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design
speed improvements have shrunk to the point that the time specs are not expected to be met.
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.21 2012-01-07".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 8,192 out of 54,576 15%
Number used as Flip Flops: 8,166
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 24
Number of Slice LUTs: 10,646 out of 27,288 39%
Number used as logic: 10,382 out of 27,288 38%
Number using O6 output only: 7,374
Number using O5 output only: 777
Number using O5 and O6: 2,231
Number used as ROM: 0
Number used as Memory: 67 out of 6,408 1%
Number used as Dual Port RAM: 24
Number using O6 output only: 24
Number using O5 output only: 0
Number using O5 and O6: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 43
Number using O6 output only: 22
Number using O5 output only: 0
Number using O5 and O6: 21
Number used exclusively as route-thrus: 197
Number with same-slice register load: 122
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 4,050 out of 6,822 59%
Nummber of MUXCYs used: 2,388 out of 13,644 17%
Number of LUT Flip Flop pairs used: 12,451
Number with an unused Flip Flop: 4,848 out of 12,451 38%
Number with an unused LUT: 1,805 out of 12,451 14%
Number of fully used LUT-FF pairs: 5,798 out of 12,451 46%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 152 out of 296 51%
Number of LOCed IOBs: 152 out of 152 100%
IOB Flip Flops: 57
Number of bonded IPADs: 4 out of 16 25%
Number of LOCed IPADs: 4 out of 4 100%
Number of bonded OPADs: 2 out of 8 25%
Number of LOCed OPADs: 2 out of 2 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 62 out of 116 53%
Number of RAMB8BWERs: 9 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 7 out of 16 43%
Number used as BUFGs: 7
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 61 out of 376 16%
Number used as ILOGIC2s: 41
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
Number used as IODELAY2s: 2
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 36 out of 376 9%
Number used as OLOGIC2s: 16
Number used as OSERDES2s: 20
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 58 5%
Number of GTPA1_DUALs: 1 out of 2 50%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 3 out of 4 75%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 20 secs
Finished initial Timing Analysis. REAL time: 20 secs
WARNING:Par:288 - The signal sfp_rate_select_b_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal sfp_tx_fault_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal tdc_in_fpga_1_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal button2_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p_wr_req_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p_wr_req_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal sfp_los_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O has no load.
PAR will not attempt to route this signal.
Starting Router
Phase 1 : 70638 unrouted; REAL time: 22 secs
Phase 2 : 62023 unrouted; REAL time: 26 secs
Phase 3 : 32684 unrouted; REAL time: 54 secs
Phase 4 : 32741 unrouted; (Setup:0, Hold:72789, Component Switching Limit:0) REAL time: 58 secs
Updating file: wr_spec_tdc.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 3 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 7 secs
Total REAL time to Router completion: 2 mins 7 secs
Total CPU time to Router completion: 2 mins 11 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_62m5_sys | BUFGMUX_X3Y13| No | 1643 | 0.529 | 1.740 |
+---------------------+--------------+------+------+------------+-------------+
| clk_125m_mezz | BUFGMUX_X3Y7| No | 727 | 0.551 | 1.762 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X2Y4| No | 247 | 0.522 | 1.733 |
+---------------------+--------------+------+------+------------+-------------+
| phy_rx_rbclk | BUFGMUX_X3Y8| No | 153 | 0.077 | 1.290 |
+---------------------+--------------+------+------+------------+-------------+
|clk_125m_pllref_BUFG | | | | | |
| | BUFGMUX_X2Y1| No | 152 | 0.065 | 1.281 |
+---------------------+--------------+------+------+------------+-------------+
| clk_dmtd | BUFGMUX_X2Y2| No | 88 | 0.032 | 1.245 |
+---------------------+--------------+------+------+------------+-------------+
|U_WR_CORE/WRPC/LM32_ | | | | | |
|CORE/gen_profile_med | | | | | |
|ium_icache_debug.U_W | | | | | |
| rapped_LM32/jtck | Local| | 9 | 3.112 | 6.373 |
+---------------------+--------------+------+------+------------+-------------+
|U_Buf_CLK_GTP_ML_IBU | | | | | |
| F2 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|U_Buf_CLK_GTP_ML_IBU | | | | | |
| F1 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/io_c | | | | | |
| lk | Local| | 41 | 0.064 | 1.562 |
+---------------------+--------------+------+------+------------+-------------+
| clk_125m_gtp | Local| | 1 | 0.000 | 1.256 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc_mezz/cmp_tdc | | | | | |
|_core/data_engine_bl | | | | | |
|ock/engine_st[3]_PWR | | | | | |
| _441_o_Mux_41_o | Local| | 1 | 0.000 | 0.972 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 17
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.050ns| 4.950ns| 0| 0
1_1 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.115ns| | 0| 0
core_cmp_clk_in_rx_pllout_x1_1" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc | SETUP | 0.051ns| 7.949ns| 0| 0
_clk_125m_n_i" 8 ns HIGH 50% | HOLD | 0.421ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_U_GTP_ch1_rx_divclk = PERIOD TIMEGRP " | SETUP | 0.169ns| 7.831ns| 0| 0
U_GTP_ch1_rx_divclk" TS_U_GTP_ch1 | HOLD | 0.322ns| | 0| 0
_gtp_clkout_int_1_ HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_RXTS = MAXDELAY FROM TIMEGRP "rx_ts_tr | SETUP | 0.169ns| 1.831ns| 0| 0
ig" TO TIMEGRP "FFS" 2 ns DATAPAT | HOLD | 0.704ns| | 0| 0
HONLY | | | | |
----------------------------------------------------------------------------------------------------------
ts_x3 = MAXDELAY FROM TIMEGRP "clk_62m5_s | SETUP | 0.181ns| 9.819ns| 0| 0
ys" TO TIMEGRP "U_GTP_ch1_rx_divclk" | HOLD | 0.448ns| | 0| 0
10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_ = MAXDELAY FROM TIMEGRP "skew_limit" | SETUP | 0.557ns| 1.443ns| 0| 0
TO TIMEGRP "FFS" 2 ns DATAPATHONLY | HOLD | 0.434ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_n_i = PERIOD TIMEGRP " | SETUP | 0.774ns| 6.711ns| 0| 0
clk_125m_pllref_n_i" 8 ns HIGH 50% | HOLD | 0.393ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_x4 = MAXDELAY FROM TIMEGRP "U_GTP_ch1_ | SETUP | 0.861ns| 9.139ns| 0| 0
rx_divclk" TO TIMEGRP "clk_62m5_sys" | HOLD | 0.344ns| | 0| 0
10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_pllout_clk_sys = PERIOD TIMEGRP "pllou | SETUP | 1.200ns| 14.800ns| 0| 0
t_clk_sys" TS_clk_20m_vcxo_i / 3.125 | HOLD | 0.039ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
= PERIOD TIMEGRP "cmp_gn4124_cor | | | | |
e_cmp_clk_in_buf_P_clk_1" TS_cmp_ | | | | |
gn4124_core_cmp_clk_in_P_clk HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
= PERIOD TIMEGRP "cmp_gn4124_cor | | | | |
e_cmp_clk_in_buf_P_clk_0" TS_p2l_clk_n_i | | | | |
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
PERIOD TIMEGRP "cmp_gn4124_core_ | | | | |
cmp_clk_in_buf_P_clk" TS_p2l_clk_p_i HIGH | | | | |
50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_p_i = PERIOD TIMEGRP " | MINPERIOD | 1.750ns| 6.250ns| 0| 0
clk_125m_pllref_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | MINPERIOD | 1.876ns| 3.124ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | | | | |
core_cmp_clk_in_rx_pllout_x1_0" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | MINPERIOD | 1.876ns| 3.124ns| 0| 0
1 = PERIOD TIMEGRP "cmp_gn4124_co | | | | |
re_cmp_clk_in_rx_pllout_x1" TS_cm | | | | |
p_gn4124_core_cmp_clk_in_buf_P_clk PHASE | | | | |
1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_2 | MINLOWPULSE | 30.000ns| 20.000ns| 0| 0
0m_vcxo_i" 50 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP | SETUP | 3.332ns| 6.668ns| 0| 0
"clk_62m5_sys" TO TIMEGRP "clk_1 | HOLD | 0.491ns| | 0| 0
25m_pllref_n_i" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clk_p_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p_i" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_P_clk = PER | MINPERIOD | 4.075ns| 0.925ns| 0| 0
IOD TIMEGRP "cmp_gn4124_core/cmp_ | | | | |
clk_in/P_clk" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clk_n_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
n_i" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_crossclock = MAXDELAY FROM TIME | SETUP | 4.274ns| 5.726ns| 0| 0
GRP "clk_62m5_sys" TO TIMEGRP "td | HOLD | 0.456ns| | 0| 0
c_clk_125m_p_i" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_gtp_p_i = PERIOD TIMEGRP "clk | MINPERIOD | 4.875ns| 3.125ns| 0| 0
_125m_gtp_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_gtp_n_i = PERIOD TIMEGRP "clk | MINPERIOD | 4.875ns| 3.125ns| 0| 0
_125m_gtp_n_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TStdc_clk_125m_p_i = PERIOD TIMEGRP "tdc_ | MINPERIOD | 4.876ns| 3.124ns| 0| 0
clk_125m_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_pllout_clk_dmtd = PERIOD TIMEGRP "pllo | SETUP | 5.919ns| 10.081ns| 0| 0
ut_clk_dmtd" TS_clk_20m_vcxo_i / | HOLD | 0.014ns| | 0| 0
3.125 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP | SETUP | 6.013ns| 3.987ns| 0| 0
"clk_125m_pllref_p_i" TO TIMEGRP | HOLD | 0.448ns| | 0| 0
"clk_62m5_sys" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_crossclock2 = MAXDELAY FROM TIM | SETUP | 6.783ns| 3.217ns| 0| 0
EGRP "tdc_clk_125m_p_i" TO TIMEGRP | HOLD | 0.367ns| | 0| 0
"clk_62m5_sys" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD T | MINPERIOD | 7.075ns| 0.925ns| 0| 0
IMEGRP "U_GTP/ch1_gtp_clkout_int<1>" | | | | |
125 MHz HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
s_int = PERIOD TIMEGRP "cmp_gn412 | | | | |
4_core_cmp_clk_in_rx_pllout_xs_int" | | | | |
TS_cmp_gn4124_core_cmp_clk_in_buf_P_cl | | | | |
k / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
s_int_0 = PERIOD TIMEGRP "cmp_gn4 | | | | |
124_core_cmp_clk_in_rx_pllout_xs_int_0" | | | | |
TS_cmp_gn4124_core_cmp_clk_in_buf_ | | | | |
P_clk_0 / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
s_int_1 = PERIOD TIMEGRP "cmp_gn4 | | | | |
124_core_cmp_clk_in_rx_pllout_xs_int_1" | | | | |
TS_cmp_gn4124_core_cmp_clk_in_buf_ | | | | |
P_clk_1 / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_clk_20m_vcxo_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_20m_vcxo_i | 50.000ns| 20.000ns| 46.250ns| 0| 0| 0| 1682593|
| TS_pllout_clk_dmtd | 16.000ns| 10.081ns| N/A| 0| 0| 9425| 0|
| TS_pllout_clk_sys | 16.000ns| 14.800ns| N/A| 0| 0| 1673168| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_p2l_clk_p_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clk_p_i | 5.000ns| 0.925ns| 3.124ns| 0| 0| 0| 0|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 3.124ns| 0| 0| 0| 0|
| buf_P_clk | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 3.124ns| N/A| 0| 0| 0| 0|
| _rx_pllout_x1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_p2l_clk_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clk_n_i | 5.000ns| 0.925ns| 3.124ns| 0| 0| 0| 0|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 3.124ns| 0| 0| 0| 0|
| buf_P_clk_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 3.124ns| N/A| 0| 0| 0| 0|
| _rx_pllout_x1_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_cmp_gn4124_core_cmp_clk_in_P_clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_cmp_gn4124_core_cmp_clk_in_P| 5.000ns| 0.925ns| 4.950ns| 0| 0| 0| 5838|
|_clk | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.950ns| 0| 0| 0| 5838|
| buf_P_clk_1 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_1 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.950ns| N/A| 0| 0| 5838| 0|
| _rx_pllout_x1_1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_U_GTP_ch1_gtp_clkout_int_1_
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_U_GTP_ch1_gtp_clkout_int_1_ | 8.000ns| 0.925ns| 7.831ns| 0| 0| 0| 20096|
| TS_U_GTP_ch1_rx_divclk | 8.000ns| 7.831ns| N/A| 0| 0| 20096| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 16 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 2 mins 13 secs
Total CPU time to PAR completion: 2 mins 17 secs
Peak Memory Usage: 458 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 18
Number of info messages: 2
Writing design to file wr_spec_tdc.ncd
PAR done!
hdl/syn/spec/with_wrabbit/wr_spec_tdc.twr deleted 100644 → 0
View file @ caaf87ad
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.map deleted 100644 → 0
View file @ caaf87ad
Release 13.4 Map O.87xd (nt)
Xilinx Map Application Log File for Design 'wr_spec_tdc'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
off -pr b -lc off -power off -o wr_spec_tdc_map.ncd wr_spec_tdc.ngd
wr_spec_tdc.pcf
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jul 08 10:59:56 2014
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 44 secs
Total CPU time at the beginning of Placer: 39 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:2f07b54b) REAL time: 48 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:2f07b54b) REAL time: 49 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:ed3fb313) REAL time: 49 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 9.8 Global Placement
........................
..................................................................................................
.................................................................................
..................................................................................................................................
..............................
Phase 9.8 Global Placement (Checksum:9fd444c4) REAL time: 5 mins
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:9fd444c4) REAL time: 5 mins 1 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:887f371b) REAL time: 5 mins 47 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:887f371b) REAL time: 5 mins 48 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:27e1a814) REAL time: 5 mins 48 secs
Total REAL time to Placer completion: 6 mins 7 secs
Total CPU time to Placer completion: 6 mins 1 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_441_o_Mux_41_o
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
.U_packet_filter/U_microcode_ram/gen_dual_clk.U_RAM_DC/Mram_ram) port(s) with
READ_FIRST mode has certain restrictions. Make sure that there is no address
collision. A read/write on one port and a write operation from the other port
at the same address is not allowed. RAMB16BWER, when both ports are 18 bits
wide or smaller, A13-6 including A4 cannot be same. When any one port is 36
bits wide, A13-7 including A5 cannot be the same. Violating this restriction
may result in the incorrect operation of the BRAM.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 9
Slice Logic Utilization:
Number of Slice Registers: 8,192 out of 54,576 15%
Number used as Flip Flops: 8,166
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 24
Number of Slice LUTs: 10,646 out of 27,288 39%
Number used as logic: 10,382 out of 27,288 38%
Number using O6 output only: 7,374
Number using O5 output only: 777
Number using O5 and O6: 2,231
Number used as ROM: 0
Number used as Memory: 67 out of 6,408 1%
Number used as Dual Port RAM: 24
Number using O6 output only: 24
Number using O5 output only: 0
Number using O5 and O6: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 43
Number using O6 output only: 22
Number using O5 output only: 0
Number using O5 and O6: 21
Number used exclusively as route-thrus: 197
Number with same-slice register load: 122
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 4,050 out of 6,822 59%
Nummber of MUXCYs used: 2,388 out of 13,644 17%
Number of LUT Flip Flop pairs used: 12,451
Number with an unused Flip Flop: 4,848 out of 12,451 38%
Number with an unused LUT: 1,805 out of 12,451 14%
Number of fully used LUT-FF pairs: 5,798 out of 12,451 46%
Number of unique control sets: 372
Number of slice register sites lost
to control set restrictions: 992 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 152 out of 296 51%
Number of LOCed IOBs: 152 out of 152 100%
IOB Flip Flops: 57
Number of bonded IPADs: 4 out of 16 25%
Number of LOCed IPADs: 4 out of 4 100%
Number of bonded OPADs: 2 out of 8 25%
Number of LOCed OPADs: 2 out of 2 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 62 out of 116 53%
Number of RAMB8BWERs: 9 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 7 out of 16 43%
Number used as BUFGs: 7
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 61 out of 376 16%
Number used as ILOGIC2s: 41
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
Number used as IODELAY2s: 2
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 36 out of 376 9%
Number used as OLOGIC2s: 16
Number used as OSERDES2s: 20
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 58 5%
Number of GTPA1_DUALs: 1 out of 2 50%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 3 out of 4 75%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 476 MB
Total REAL time to MAP completion: 6 mins 19 secs
Total CPU time to MAP completion: 6 mins 12 secs
Mapping completed.
See MAP report file "wr_spec_tdc_map.mrp" for details.
hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.mrp deleted 100644 → 0
View file @ caaf87ad
Release 13.4 Map O.87xd (nt)
Xilinx Mapping Report File for Design 'wr_spec_tdc'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
off -pr b -lc off -power off -o wr_spec_tdc_map.ncd wr_spec_tdc.ngd
wr_spec_tdc.pcf
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jul 08 10:59:56 2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 9
Slice Logic Utilization:
Number of Slice Registers: 8,192 out of 54,576 15%
Number used as Flip Flops: 8,166
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 24
Number of Slice LUTs: 10,646 out of 27,288 39%
Number used as logic: 10,382 out of 27,288 38%
Number using O6 output only: 7,374
Number using O5 output only: 777
Number using O5 and O6: 2,231
Number used as ROM: 0
Number used as Memory: 67 out of 6,408 1%
Number used as Dual Port RAM: 24
Number using O6 output only: 24
Number using O5 output only: 0
Number using O5 and O6: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 43
Number using O6 output only: 22
Number using O5 output only: 0
Number using O5 and O6: 21
Number used exclusively as route-thrus: 197
Number with same-slice register load: 122
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 4,050 out of 6,822 59%
Nummber of MUXCYs used: 2,388 out of 13,644 17%
Number of LUT Flip Flop pairs used: 12,451
Number with an unused Flip Flop: 4,848 out of 12,451 38%
Number with an unused LUT: 1,805 out of 12,451 14%
Number of fully used LUT-FF pairs: 5,798 out of 12,451 46%
Number of unique control sets: 372
Number of slice register sites lost
to control set restrictions: 992 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 152 out of 296 51%
Number of LOCed IOBs: 152 out of 152 100%
IOB Flip Flops: 57
Number of bonded IPADs: 4 out of 16 25%
Number of LOCed IPADs: 4 out of 4 100%
Number of bonded OPADs: 2 out of 8 25%
Number of LOCed OPADs: 2 out of 2 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 62 out of 116 53%
Number of RAMB8BWERs: 9 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 7 out of 16 43%
Number used as BUFGs: 7
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 61 out of 376 16%
Number used as ILOGIC2s: 41
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
Number used as IODELAY2s: 2
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 36 out of 376 9%
Number used as OLOGIC2s: 16
Number used as OSERDES2s: 20
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 58 5%
Number of GTPA1_DUALs: 1 out of 2 50%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 3 out of 4 75%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 476 MB
Total REAL time to MAP completion: 6 mins 19 secs
Total CPU time to MAP completion: 6 mins 12 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_441_o_Mux_41_o
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
.U_packet_filter/U_microcode_ram/gen_dual_clk.U_RAM_DC/Mram_ram) port(s) with
READ_FIRST mode has certain restrictions. Make sure that there is no address
collision. A read/write on one port and a write operation from the other port
at the same address is not allowed. RAMB16BWER, when both ports are 18 bits
wide or smaller, A13-6 including A4 cannot be same. When any one port is 36
bits wide, A13-7 including A5 cannot be the same. Violating this restriction
may result in the incorrect operation of the BRAM.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network tdc_in_fpga_2_i has no load.
INFO:LIT:395 - The above info message is repeated 144 more times for the
following (max. 5 shown):
tdc_in_fpga_3_i,
tdc_in_fpga_4_i,
tdc_in_fpga_5_i,
carrier_scl_b,
carrier_sda_b
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
60 block(s) removed
3 block(s) optimized away
169 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" (FF)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" is loadless and has
been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" (ROM)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<5>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_5" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter5" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<5>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv1_INV_0"
(BUF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_8" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter8" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<8>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<6>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_6" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter6" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<6>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<7>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_7" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter7" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<7>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<0>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_0" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<0>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<1>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_1" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter1" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<1>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<2>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_2" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter2" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<2>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<3>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_3" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter3" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<3>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<4>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_4" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter4" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<4>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" (FF)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4-In" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/_n0363_inv1" (ROM)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[10].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[11].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[12].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[13].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[14].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[15].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[1].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[2].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[3].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[4].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[5].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[6].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[7].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[8].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[9].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd25"
(ROM) removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(127)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(126)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(125)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(124)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(123)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(122)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(121)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(120)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(119)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(118)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(117)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(116)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(115)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(114)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(113)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(112)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(111)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(110)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(109)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(108)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(107)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(106)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(105)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(104)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(103)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(102)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(101)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(100)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(99)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(98)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(97)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(96)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(95)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(94)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(93)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(92)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(91)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(90)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(89)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(88)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(87)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(86)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(85)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(84)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(83)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(82)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(81)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(80)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(79)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(78)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(77)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(76)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(75)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(74)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(73)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(72)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(71)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(70)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(69)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(68)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(67)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(66)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(65)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(64)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(63)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(62)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(61)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(60)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(59)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(58)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(57)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(56)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(55)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(54)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(53)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(52)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(51)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(50)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(49)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(48)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(47)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(46)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(45)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(44)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(43)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(42)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(41)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(40)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(39)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(38)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(37)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(36)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(35)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(34)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(33)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(32)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(31)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(30)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(29)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(28)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(27)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(26)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(25)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(24)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(23)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(22)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(21)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(20)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(19)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(18)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(17)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(16)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(15)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(14)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(13)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(12)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(11)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(10)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(9)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(8)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(7)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(6)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(5)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(4)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(3)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(2)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(1)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(0)" is
sourceless and has been removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
GND cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/XST_GND
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| acam_refclk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| acam_refclk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | IFF | | |
| address_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| address_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| address_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| address_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| button1_i | IOB | INPUT | LVCMOS18 | | | | | | |
| button2_i | IOB | INPUT | LVCMOS18 | | | | | | |
| carrier_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| clk_125m_gtp_n_i | IPAD | INPUT | | | | | | | |
| clk_125m_gtp_p_i | IPAD | INPUT | | | | | | | |
| clk_125m_pllref_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| clk_125m_pllref_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| clk_20m_vcxo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| dac_cs1_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dac_cs2_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dac_din_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dac_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| data_bus_io<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<16> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<17> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<18> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<19> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<20> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<21> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<22> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<23> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<24> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<25> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<26> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<27> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| ef1_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| ef2_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| enable_inputs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| err_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| int_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| irq_p_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| l2p_clk_n_o | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
| l2p_clk_p_o | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
| l2p_data_o<0> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<1> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<2> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<3> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<4> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<5> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<6> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<7> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<8> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<9> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<10> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<11> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<12> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<13> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<14> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<15> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_dframe_o | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_edb_o | IOB | OUTPUT | SSTL18_I | | | | OFF | | |
| l2p_rdy_i | IOB | INPUT | SSTL18_I | | | | IFF | | |
| l2p_valid_o | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l_wr_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| l_wr_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| led_green | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_red | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| mezz_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| mezz_sys_scl_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| mezz_sys_sda_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| oe_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| p2l_clk_n_i | IOB | INPUT | DIFF_SSTL18_I | | | | | | |
| p2l_clk_p_i | IOB | INPUT | DIFF_SSTL18_I | | | | ISERDES | | VARIABLE |
| p2l_data_i<0> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<1> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<2> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<3> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<4> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<5> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<6> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<7> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<8> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<9> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<10> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<11> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<12> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<13> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<14> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<15> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_dframe_i | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_rdy_o | IOB | OUTPUT | SSTL18_I | | | | | | |
| p2l_valid_i | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p_rd_d_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| p_rd_d_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| p_wr_rdy_o<0> | IOB | OUTPUT | SSTL18_I | | | | | | |
| p_wr_rdy_o<1> | IOB | OUTPUT | SSTL18_I | | | | | | |
| p_wr_req_i<0> | IOB | INPUT | SSTL18_I | | | | | | |
| p_wr_req_i<1> | IOB | INPUT | SSTL18_I | | | | | | |
| pcb_ver_i<0> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<1> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<2> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<3> | IOB | INPUT | LVCMOS15 | | | | | | |
| pll_cs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_dac_sync_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_sdi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_sdo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| prsnt_m2c_n_i | IOB | INPUT | LVCMOS25 | | | | | | |
| rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| rst_n_a_i | IOB | INPUT | LVCMOS18 | | | | | | |
| rx_error_o | IOB | OUTPUT | SSTL18_I | | | | | | |
| sfp_los_i | IOB | INPUT | LVCMOS25 | | | | | | |
| sfp_mod_def0_b | IOB | INPUT | LVCMOS25 | | | | | | |
| sfp_mod_def1_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| sfp_mod_def2_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| sfp_rate_select_b | IOB | INPUT | LVCMOS25 | | | | | | |
| sfp_rxn_i | IPAD | INPUT | | | | | | | |
| sfp_rxp_i | IPAD | INPUT | | | | | | | |
| sfp_tx_disable_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| sfp_tx_fault_i | IOB | INPUT | LVCMOS25 | | | | | | |
| sfp_txn_o | OPAD | OUTPUT | | | | | | | |
| sfp_txp_o | OPAD | OUTPUT | | | | | | | |
| start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc_clk_125m_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc_clk_125m_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc_in_fpga_1_i | IOB | INPUT | LVCMOS25 | | | | | | |
| tdc_led_status_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc_led_trig1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tx_error_i | IOB | INPUT | SSTL18_I | | | | IFF | | |
| uart_rxd_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| uart_txd_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| vc_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | | | |
| vc_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | | | |
| wr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
hdl/syn/spec/with_wrabbit/wrc.ram deleted 100644 → 0
View file @ caaf87ad
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/with_wrabbit/wr_spec_tdc.xise → hdl/syn/spec/wr_spec_tdc.xise
View file @ 5765c94d
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.xise deleted 100644 → 0
View file @ caaf87ad
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/xilinx/spec_top_fmc_tdc/wrc.ram deleted 100644 → 0
View file @ caaf87ad
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/testbench/spec/Manifest.py 0 → 100644
View file @ 5765c94d
sim_tool = "modelsim"
top_module="main"
syn_device="xc6slx45t"
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
include_dirs=[ "../../sim", "../include", "../../ip_cores/gn4124-core/hdl/gn4124core/sim/gn4124_bfm" ]
files = [ "main.sv" ]
modules = { "local" : [ "../../top/spec", "../../ip_cores/gn4124-core/hdl/gn4124core/sim/gn4124_bfm" ] }
hdl/testbench/spec/main.sv 0 → 100644
View file @ 5765c94d
`include "simdrv_defs.svh"
`include "gn4124_bfm.svh"
`include "timestamp_fifo_regs.vh"
module fake_acam(
input [3:0] addr,
output reg [27:0] data,
input wr,
input rd,
output reg ef1,
output reg ef2
);
typedef struct {
int channel;
time ts;
} acam_fifo_entry;
acam_fifo_entry fifo1[$], fifo2[$];
task pulse(int channel, time ts);
acam_fifo_entry ent;
ent.channel = channel % 4;
ent.ts = ts;
if (channel >= 0 && channel <= 3)
fifo1.push_back(ent);
else
fifo2.push_back(ent);
#100ns;
if(fifo1.size())
ef1 = 0;
if(fifo2.size())
ef2 = 0;
endtask // pulse
initial begin
ef1 = 1;
ef2 = 1;
data = 28'bz;
end
always@(negedge rd) begin
if (addr == 8) begin
acam_fifo_entry ent;
ent=fifo1.pop_front();
data <= ent.ts | (ent.channel << 26) | (1<<17);
end else if (addr == 9) begin
acam_fifo_entry ent;
ent=fifo2.pop_front();
data <= ent.ts | (ent.channel << 26) | (1<<17);
end else
data <= 28'bz;
#10ns;
ef1 <= (fifo1.size() ? 0 : 1);
ef2 <= (fifo2.size() ? 0 : 1);
end
endmodule
module main;
reg rst_n = 0;
reg clk_125m = 0, clk_20m = 0;
always #4ns clk_125m <= ~clk_125m;
always #25ns clk_20m <= ~clk_20m;
initial begin
repeat(20) @(posedge clk_125m);
rst_n = 1;
end
reg clk_acam = 0;
reg clk_62m5 = 0;
always@(posedge clk_125m)
clk_62m5 <= ~clk_62m5;
always@(posedge clk_62m5)
clk_acam <= ~clk_acam;
wire [3:0] tdc_addr;
wire [27:0] tdc_data;
IGN4124PCIMaster I_Gennum ();
wr_spec_tdc #(
.g_with_wr_phy(0),
.g_simulation(1)
) DUT (
.clk_125m_pllref_p_i(clk_125m),
.clk_125m_pllref_n_i(~clk_125m),
.clk_125m_gtp_p_i(clk_125m),
.clk_125m_gtp_n_i(~clk_125m),
.tdc_clk_125m_p_i(clk_125m),
.tdc_clk_125m_n_i(~clk_125m),
.acam_refclk_p_i(clk_acam),
.acam_refclk_n_i(~clk_acam),
.clk_20m_vcxo_i(clk_20m),
.pll_status_i(1'b1),
.ef1_i(tdc_ef1),
.ef2_i(tdc_ef2),
.err_flag_i(1'b0),
.int_flag_i(1'b0),
.rd_n_o(tdc_rd_n),
.data_bus_io(tdc_data),
.address_o(tdc_addr),
`GENNUM_WIRE_SPEC_PINS(I_Gennum)
);
fake_acam ACAM(
.addr(tdc_addr),
.data(tdc_data),
.wr(1'b0),
.rd(tdc_rd_n),
.ef1(tdc_ef1),
.ef2(tdc_ef2)
);
reg force_irq = 0;
initial begin
CBusAccessor acc;
const uint64_t tdc1_base = 'h40000;
uint64_t d;
acc = I_Gennum.get_accessor();
#100us;
$display("Accessor: %x", acc);
$display("Un-reset FMCs...");
acc.write('h02000c, 'h3);
#500us;
acc.read('h040000, d);
$display("TDC SDB ID : %x", d);
acc.write('h420a0, 1234); // set UTC
acc.write('h420fc, 1<<9); // load UTC
acc.write('h43004, 'hf); // enable EIC irq
acc.write('h42084, 'h1f0000); // enable all ACAM inputs
acc.write('h420fc, (1<<0)); // start acquisition
acc.write('h420fc, (1<<0)); // start acquisition
acc.write('h42090, 2); // thr = 2 ts
acc.write('h42094, 10); // thr = 10 ms
#300us;
fork
forever begin
acc.read('h45000 + `ADDR_TSF_CSR, d);
$display("TSF CSR %x", d);
if(d&1) begin
uint64_t t0,t1,t2,t3;
acc.write('h45000 + `ADDR_TSF_CSR, 0);
acc.read('h45000 + `ADDR_TSF_LTS0, t0);
acc.read('h45000 + `ADDR_TSF_LTS1, t1);
acc.read('h45000 + `ADDR_TSF_LTS2, t2);
acc.read('h45000 + `ADDR_TSF_LTS3, t3);
$display("Last: %08x %08x %08x %08x",t0,t1,t2,t3);
end
acc.read('h45000 + `ADDR_TSF_FIFO_CSR, d);
// $display("FIFO CSR %x", d);
/* -----\/----- EXCLUDED -----\/-----
if(!(d&`TSF_FIFO_CSR_EMPTY)) begin
uint64_t t0,t1,t2,t3;
acc.read('hc15000 + `ADDR_TSF_FIFO_R0, t0);
acc.read('hc15000 + `ADDR_TSF_FIFO_R1, t1);
acc.read('hc15000 + `ADDR_TSF_FIFO_R2, t2);
acc.read('hc15000 + `ADDR_TSF_FIFO_R3, t3);
$display("Fifo: %08x %08x %08x %08x",t0,t1,t2,t3);
end
-----/\----- EXCLUDED -----/\----- */
end
forever begin
$display("Pulse!");
ACAM.pulse(0, 0);
ACAM.pulse(1, 0);
ACAM.pulse(2, 0);
#10us;
end
join
end
endmodule // main
hdl/testbench/spec/run.do 0 → 100644
View file @ 5765c94d
vsim -t 1ps -L unisim work.main -voptargs=+acc
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 1ms
\ No newline at end of file
hdl/testbench/spec/wave.do 0 → 100644
View file @ 5765c94d
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst_n_a_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/status_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_clk_p_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_clk_n_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_data_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dframe_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_valid_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_rdy_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_wr_req_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_wr_rdy_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rx_error_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/vc_rdy_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_clk_p_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_clk_n_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_data_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dframe_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_valid_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_irq_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/irq_p_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/irq_p_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_clk_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_adr_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_dat_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_sel_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_stb_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_we_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_cyc_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_dat_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_ack_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_stall_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_clk_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_adr_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_dat_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_sel_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_stb_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_we_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_cyc_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_dat_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_ack_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_stall_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_err_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_rty_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_int_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_clk_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_adr_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_dat_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_sel_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_stb_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_we_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_cyc_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_dat_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ack_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_stall_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_err_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_rty_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_int_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/sys_clk
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/io_clk
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/serdes_strobe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_pll_locked
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst_reg
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst_n
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/des_pd_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/des_pd_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/des_pd_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_wr_rdy
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_rdy_wbm
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_rdy_pdm
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_start
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_length
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_cid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_last
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_stat
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_target_mrd
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_target_mwr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_master_cpld
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_master_cpln
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_d_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_d_last
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_d
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_be
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_addr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_addr_start
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ser_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ser_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ser_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_req
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_wbm_gnt
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_req
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ldm_gnt
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_req
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_pdm_gnt
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_carrier_addr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_host_addr_h
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_host_addr_l
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_len
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_start_l2p
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_start_p2l
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_start_next
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_done
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_error
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_l2p_done
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_l2p_error
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_p2l_done
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_p2l_error
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_byte_swap
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_abort
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_carrier_addr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_host_addr_h
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_host_addr_l
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_len
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_next_l
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_next_h
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_attrib
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_irq
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_adr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_adr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_dat_s2m
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_dat_m2s
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_sel
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_cyc
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_stb
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_we
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_ack
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_stall
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_adr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_dat_s2m
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_dat_m2s
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_sel
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_cyc
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_stb
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_we
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_ack
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_stall
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/clk_sys_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rst_sys_n_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/clk_tdc_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rst_tdc_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/acam_refclk_r_edge_p_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/send_dac_word_p_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/dac_word_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/start_from_fpga_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/err_flag_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/int_flag_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/start_dis_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/stop_dis_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/data_bus_io
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/address_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cs_n_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/oe_n_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rd_n_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wr_n_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/ef1_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/ef2_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/enable_inputs_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_1_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_2_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_3_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_4_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_5_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_status_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig1_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig2_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig3_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig4_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig5_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_1_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_2_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_3_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_4_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_5_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_link_up_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_time_valid_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_cycles_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_utc_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_aux_lock_en_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_aux_locked_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_dmtd_locked_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_value_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_wr_p_i
add wave -noupdate -expand -group Mezz -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/slave_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/slave_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wb_irq_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_oen_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_oen_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/onewire_b
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/direct_timestamp_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/direct_timestamp_stb_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/general_rst_n
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rst_ref_0_n
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cnx_master_out
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cnx_master_in
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_core_wb_adr
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_mem_wb_adr
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/mezz_owr_en
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/mezz_owr_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_scl_in
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_scl_out
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_scl_oe_n
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_sda_in
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_sda_out
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_sda_oe_n
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_tstamp
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/reg_to_wr
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/reg_from_wr
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_utc_p
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_synched
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_channel
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/timestamp
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/timestamp_stb
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/channel_enable
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_threshold
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_timeout
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tick_1ms
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/counter_1ms
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/clk_sys_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_n_sys_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/clk_tdc_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_tdc_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_refclk_r_edge_p_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/send_dac_word_p_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/dac_word_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/err_flag_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/int_flag_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/start_dis_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/stop_dis_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_bus_io
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/address_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/cs_n_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/oe_n_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rd_n_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wr_n_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/ef1_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/ef2_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/enable_inputs_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/term_en_1_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/term_en_2_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/term_en_3_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/term_en_4_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/term_en_5_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_status_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig1_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig2_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig3_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig4_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig5_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_status_reg_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_synched_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_p_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_stb_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/channel_enable_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/irq_threshold_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/irq_timeout_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_adr
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_cyc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_stb
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_we
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_ack
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_dat_r
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_dat_w
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_ef1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_ef2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_ef1_meta
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_ef2_meta
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_f_edge_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_r_edge_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_intflag_f_edge_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1_ok_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2_ok_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/activate_acq_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/deactivate_acq_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/load_acam_config
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/read_acam_config
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/read_acam_status
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/read_ififo1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/read_ififo2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/read_start01
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reset_acam
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/load_utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/roll_over_incr_recent
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/deactivate_chan
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/pulse_delay
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/window_delay
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/clk_period
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/starting_utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_inputs_en
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_ififo1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_ififo2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_start01
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/irq_tstamp_threshold
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/irq_time_threshold
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/local_utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_config
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_config_rdbk
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/state_active_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/clk_i_cycles_offset
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/roll_over_nb
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/retrig_nb_offset
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/local_utc_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/current_retrig_nb
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/utc_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_channel
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp_channel
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_sys
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_valid
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_sys_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_tdc_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_n_sys_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_tdc_i
add wave -noupdate -expand -group FIFO0 -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_o
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_o
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/enable_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tick_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_threshold_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_timeout_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_valid_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tmr_timeout
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_irq_int
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_count
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/last_ts
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_in
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_out
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/channel_id
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/ts_match
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/seq_counter
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_with_seq
add wave -noupdate /main/DUT/clk_125m_pllref_p_i
add wave -noupdate /main/DUT/clk_125m_pllref_n_i
add wave -noupdate /main/DUT/clk_125m_gtp_n_i
add wave -noupdate /main/DUT/clk_125m_gtp_p_i
add wave -noupdate /main/DUT/clk_20m_vcxo_i
add wave -noupdate /main/DUT/dac_sclk_o
add wave -noupdate /main/DUT/dac_din_o
add wave -noupdate /main/DUT/dac_cs1_n_o
add wave -noupdate /main/DUT/dac_cs2_n_o
add wave -noupdate /main/DUT/sfp_txp_o
add wave -noupdate /main/DUT/sfp_txn_o
add wave -noupdate /main/DUT/sfp_rxp_i
add wave -noupdate /main/DUT/sfp_rxn_i
add wave -noupdate /main/DUT/sfp_mod_def0_b
add wave -noupdate /main/DUT/sfp_mod_def1_b
add wave -noupdate /main/DUT/sfp_mod_def2_b
add wave -noupdate /main/DUT/sfp_rate_select_b
add wave -noupdate /main/DUT/sfp_tx_fault_i
add wave -noupdate /main/DUT/sfp_tx_disable_o
add wave -noupdate /main/DUT/sfp_los_i
add wave -noupdate /main/DUT/uart_rxd_i
add wave -noupdate /main/DUT/uart_txd_o
add wave -noupdate /main/DUT/carrier_scl_b
add wave -noupdate /main/DUT/carrier_sda_b
add wave -noupdate /main/DUT/carrier_onewire_b
add wave -noupdate /main/DUT/button1_i
add wave -noupdate /main/DUT/button2_i
add wave -noupdate /main/DUT/l_rst_n
add wave -noupdate /main/DUT/gpio
add wave -noupdate /main/DUT/p2l_rdy
add wave -noupdate /main/DUT/p2l_clkn
add wave -noupdate /main/DUT/p2l_clkp
add wave -noupdate /main/DUT/p2l_data
add wave -noupdate /main/DUT/p2l_dframe
add wave -noupdate /main/DUT/p2l_valid
add wave -noupdate /main/DUT/p_wr_req
add wave -noupdate /main/DUT/p_wr_rdy
add wave -noupdate /main/DUT/rx_error
add wave -noupdate /main/DUT/l2p_data
add wave -noupdate /main/DUT/l2p_dframe
add wave -noupdate /main/DUT/l2p_valid
add wave -noupdate /main/DUT/l2p_clkn
add wave -noupdate /main/DUT/l2p_clkp
add wave -noupdate /main/DUT/l2p_edb
add wave -noupdate /main/DUT/l2p_rdy
add wave -noupdate /main/DUT/l_wr_rdy
add wave -noupdate /main/DUT/p_rd_d_rdy
add wave -noupdate /main/DUT/tx_error
add wave -noupdate /main/DUT/vc_rdy
add wave -noupdate /main/DUT/pll_sclk_o
add wave -noupdate /main/DUT/pll_sdi_o
add wave -noupdate /main/DUT/pll_cs_o
add wave -noupdate /main/DUT/pll_dac_sync_o
add wave -noupdate /main/DUT/pll_sdo_i
add wave -noupdate /main/DUT/pll_status_i
add wave -noupdate /main/DUT/tdc_clk_125m_p_i
add wave -noupdate /main/DUT/tdc_clk_125m_n_i
add wave -noupdate /main/DUT/acam_refclk_p_i
add wave -noupdate /main/DUT/acam_refclk_n_i
add wave -noupdate /main/DUT/start_from_fpga_o
add wave -noupdate /main/DUT/err_flag_i
add wave -noupdate /main/DUT/int_flag_i
add wave -noupdate /main/DUT/start_dis_o
add wave -noupdate /main/DUT/stop_dis_o
add wave -noupdate /main/DUT/data_bus_io
add wave -noupdate /main/DUT/address_o
add wave -noupdate /main/DUT/cs_n_o
add wave -noupdate /main/DUT/oe_n_o
add wave -noupdate /main/DUT/rd_n_o
add wave -noupdate /main/DUT/wr_n_o
add wave -noupdate /main/DUT/ef1_i
add wave -noupdate /main/DUT/ef2_i
add wave -noupdate /main/DUT/enable_inputs_o
add wave -noupdate /main/DUT/term_en_2_o
add wave -noupdate /main/DUT/term_en_3_o
add wave -noupdate /main/DUT/term_en_4_o
add wave -noupdate /main/DUT/term_en_5_o
add wave -noupdate /main/DUT/tdc_led_status_o
add wave -noupdate /main/DUT/tdc_led_trig1_o
add wave -noupdate /main/DUT/tdc_led_trig2_o
add wave -noupdate /main/DUT/tdc_led_trig3_o
add wave -noupdate /main/DUT/tdc_led_trig4_o
add wave -noupdate /main/DUT/tdc_led_trig5_o
add wave -noupdate /main/DUT/tdc_in_fpga_1_i
add wave -noupdate /main/DUT/tdc_in_fpga_2_i
add wave -noupdate /main/DUT/tdc_in_fpga_3_i
add wave -noupdate /main/DUT/tdc_in_fpga_4_i
add wave -noupdate /main/DUT/tdc_in_fpga_5_i
add wave -noupdate /main/DUT/mezz_sys_scl_b
add wave -noupdate /main/DUT/mezz_sys_sda_b
add wave -noupdate /main/DUT/mezz_onewire_b
add wave -noupdate /main/DUT/led_red
add wave -noupdate /main/DUT/led_green
add wave -noupdate /main/DUT/pcb_ver_i
add wave -noupdate /main/DUT/prsnt_m2c_n_i
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/pllout_clk_dmtd
add wave -noupdate /main/DUT/pllout_clk_fb_pllref
add wave -noupdate /main/DUT/pllout_clk_fb_dmtd
add wave -noupdate /main/DUT/clk_125m_pllref
add wave -noupdate /main/DUT/clk_125m_gtp
add wave -noupdate /main/DUT/clk_dmtd
add wave -noupdate /main/DUT/clk_20m_vcxo
add wave -noupdate /main/DUT/clk_20m_vcxo_buf
add wave -noupdate /main/DUT/clk_62m5_sys
add wave -noupdate /main/DUT/sys_locked
add wave -noupdate /main/DUT/rst_n_sys
add wave -noupdate /main/DUT/cnx_master_out
add wave -noupdate /main/DUT/cnx_master_in
add wave -noupdate /main/DUT/cnx_slave_out
add wave -noupdate /main/DUT/cnx_slave_in
add wave -noupdate /main/DUT/gn_wb_adr
add wave -noupdate /main/DUT/gn4124_status
add wave -noupdate /main/DUT/carrier_owr_en
add wave -noupdate /main/DUT/carrier_owr_i
add wave -noupdate /main/DUT/irq_to_gn4124
add wave -noupdate /main/DUT/tm_link_up
add wave -noupdate /main/DUT/tm_time_valid
add wave -noupdate /main/DUT/tm_dac_wr_p
add wave -noupdate /main/DUT/tm_tai
add wave -noupdate /main/DUT/tm_cycles
add wave -noupdate /main/DUT/tm_dac_value
add wave -noupdate /main/DUT/tm_dac_value_reg
add wave -noupdate /main/DUT/tm_clk_aux_lock_en
add wave -noupdate /main/DUT/tm_clk_aux_locked
add wave -noupdate /main/DUT/phy_tx_data
add wave -noupdate /main/DUT/phy_rx_data
add wave -noupdate /main/DUT/phy_tx_k
add wave -noupdate /main/DUT/phy_tx_disparity
add wave -noupdate /main/DUT/phy_rx_k
add wave -noupdate /main/DUT/phy_tx_enc_err
add wave -noupdate /main/DUT/phy_rx_rbclk
add wave -noupdate /main/DUT/phy_rx_enc_err
add wave -noupdate /main/DUT/phy_rst
add wave -noupdate /main/DUT/phy_loopen
add wave -noupdate /main/DUT/phy_rx_bitslide
add wave -noupdate /main/DUT/dac_hpll_load_p1
add wave -noupdate /main/DUT/dac_dpll_load_p1
add wave -noupdate /main/DUT/dac_hpll_data
add wave -noupdate /main/DUT/dac_dpll_data
add wave -noupdate /main/DUT/wrc_scl_out
add wave -noupdate /main/DUT/wrc_scl_in
add wave -noupdate /main/DUT/wrc_sda_out
add wave -noupdate /main/DUT/wrc_sda_in
add wave -noupdate /main/DUT/tdc_scl_out
add wave -noupdate /main/DUT/tdc_scl_in
add wave -noupdate /main/DUT/tdc_sda_out
add wave -noupdate /main/DUT/tdc_sda_in
add wave -noupdate /main/DUT/tdc_scl_oen
add wave -noupdate /main/DUT/tdc_sda_oen
add wave -noupdate /main/DUT/sfp_scl_out
add wave -noupdate /main/DUT/sfp_scl_in
add wave -noupdate /main/DUT/sfp_sda_out
add wave -noupdate /main/DUT/sfp_sda_in
add wave -noupdate /main/DUT/wrc_owr_en
add wave -noupdate /main/DUT/wrc_owr_in
add wave -noupdate /main/DUT/tdc0_irq
add wave -noupdate /main/DUT/tdc0_clk_125m
add wave -noupdate /main/DUT/tdc0_soft_rst_n
add wave -noupdate /main/DUT/powerup_rst_cnt
add wave -noupdate /main/DUT/carrier_info_fmc_rst
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {916212143 ps} 0}
configure wave -namecolwidth 177
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {3698688 ns}
hdl/testbench/spec/wrc-simulation.ram 0 → 100644
View file @ 5765c94d
write 0 98000000
write 1 D0000000
write 2 D0200000
write 3 78010000
write 4 38210000
write 5 D0E10000
write 6 98000000
write 7 781C0000
write 8 3B9C0FFC
write 9 F80000F4
write a 78020000
write b 38420578
write c 28420000
write d 2021FFFF
write e 78038000
write f B8230800
write 10 5841002C
write 11 28410030
write 12 4C20FFFF
write 13 C3A00000
write 14 78030000
write 15 386304D8
write 16 28610000
write 17 3802C49C
write 18 58220004
write 19 C3A00000
write 1a 78030000
write 1b 386304D8
write 1c 28620000
write 1d 28430000
write 1e 20630001
write 1f 5C60FFFE
write 20 78030000
write 21 386304D8
write 22 28620000
write 23 58410008
write 24 C3A00000
write 25 379CFFF8
write 26 5B8B0008
write 27 5B9D0004
write 28 B8205800
write 29 E0000002
write 2a FBFFFFF0
write 2b 41610000
write 2c 356B0001
write 2d 5C20FFFD
write 2e 2B9D0004
write 2f 2B8B0008
write 30 379C0008
write 31 C3A00000
write 32 379CFFFC
write 33 5B9D0004
write 34 78010000
write 35 38210578
write 36 28210000
write 37 78030000
write 38 386304DC
write 39 28620000
write 3a 58200014
write 3b 58200018
write 3c 78040000
write 3d 58220014
write 3e 388404E0
write 3f 3402000B
write 40 58220018
write 41 28820000
write 42 78030000
write 43 386304E4
write 44 58220014
write 45 34020088
write 46 58220018
write 47 28620000
write 48 78040000
write 49 388404E8
write 4a 58220014
write 4b 34020108
write 4c 58220018
write 4d 28820000
write 4e 78030000
write 4f 386304EC
write 50 58220014
write 51 34020013
write 52 58220018
write 53 28620000
write 54 78040000
write 55 388404F0
write 56 58220014
write 57 34020090
write 58 58220018
write 59 28820000
write 5a 78030000
write 5b 386304F4
write 5c 58220014
write 5d 34020110
write 5e 58220018
write 5f 28620000
write 60 78040000
write 61 388404F8
write 62 58220014
write 63 3402001B
write 64 58220018
write 65 28820000
write 66 78030000
write 67 386304FC
write 68 58220014
write 69 34020098
write 6a 58220018
write 6b 28620000
write 6c 78040000
write 6d 38840500
write 6e 58220014
write 6f 34020118
write 70 58220018
write 71 28820000
write 72 78030000
write 73 38630504
write 74 58220014
write 75 34020323
write 76 58220018
write 77 28620000
write 78 78040000
write 79 38840508
write 7a 58220014
write 7b 3402032B
write 7c 58220018
write 7d 28820000
write 7e 78030000
write 7f 3863050C
write 80 58220014
write 81 34020333
write 82 58220018
write 83 28620000
write 84 78040000
write 85 38840510
write 86 58220014
write 87 3402034B
write 88 58220018
write 89 28820000
write 8a 78030000
write 8b 38630514
write 8c 58220014
write 8d 340205BB
write 8e 58220018
write 8f 28620000
write 90 78040000
write 91 38840518
write 92 58220014
write 93 340205C3
write 94 58220018
write 95 28820000
write 96 78030000
write 97 3863051C
write 98 58220014
write 99 34020351
write 9a 58220018
write 9b 28620000
write 9c 78040000
write 9d 38840520
write 9e 58220014
write 9f 34020159
write a0 58220018
write a1 28820000
write a2 78030000
write a3 38630524
write a4 58220014
write a5 34020170
write a6 58220018
write a7 28620000
write a8 78040000
write a9 38840528
write aa 58220014
write ab 34020A78
write ac 58220018
write ad 28820000
write ae 78030000
write af 3863052C
write b0 58220014
write b1 34020973
write b2 58220018
write b3 28620000
write b4 78040000
write b5 38840530
write b6 58220014
write b7 34020E70
write b8 58220018
write b9 28820000
write ba 78030000
write bb 38630534
write bc 58220014
write bd 34020E79
write be 58220018
write bf 28620000
write c0 78040000
write c1 38840538
write c2 58220014
write c3 34020BA0
write c4 58220018
write c5 28820000
write c6 78030000
write c7 3863053C
write c8 58220014
write c9 340204B9
write ca 58220018
write cb 28620000
write cc 78040000
write cd 38840540
write ce 58220014
write cf 34020BF8
write d0 58220018
write d1 28820000
write d2 78030000
write d3 38630544
write d4 58220014
write d5 340201F0
write d6 58220018
write d7 28620000
write d8 78040000
write d9 38840548
write da 58220014
write db 34020FC3
write dc 58220018
write dd 28820000
write de 78030000
write df 3863054C
write e0 58220014
write e1 28620000
write e2 58200018
write e3 78040000
write e4 58220014
write e5 38840550
write e6 34020080
write e7 58220014
write e8 28830000
write e9 58200000
write ea 34020003
write eb 5822000C
write ec 58230008
write ed 78030000
write ee 38630554
write ef 58220004
write f0 28620000
write f1 58220028
write f2 34021122
write f3 58220024
write f4 340200E0
write f5 58220000
write f6 34010800
write f7 FBFFFF13
write f8 34011200
write f9 FBFFFF11
write fa 2B9D0004
write fb 379C0004
write fc C3A00000
write fd 379CFFEC
write fe 5B8B0014
write ff 5B8C0010
write 100 5B8D000C
write 101 5B8E0008
write 102 5B9D0004
write 103 78020000
write 104 38420558
write 105 78040000
write 106 28410000
write 107 3884055C
write 108 28830000
write 109 34020012
write 10a 78040000
write 10b 58220000
write 10c 38840560
write 10d 58600000
write 10e 28830000
write 10f 78040000
write 110 38840564
write 111 58600000
write 112 28830000
write 113 780B0000
write 114 340C0032
write 115 58600000
write 116 3403001A
write 117 58230000
write 118 78030000
write 119 38630568
write 11a 58220000
write 11b 28610000
write 11c 34020004
write 11d 396B056C
write 11e 58220000
write 11f FBFFFF13
write 120 78040000
write 121 388404D8
write 122 28810000
write 123 3802C49C
write 124 58220004
write 125 B9600800
write 126 358CFFFF
write 127 FBFFFEFE
write 128 5D80FFFD
write 129 780B0000
write 12a 780C0000
write 12b 340D0032
write 12c 396B057C
write 12d 780E0001
write 12e 398C0574
write 12f 29620000
write 130 B9AE0800
write 131 35AD0001
write 132 58410044
write 133 B9800800
write 134 FBFFFEF1
write 135 E3FFFFFA
write 136 00020500
write 137 40000040
write 138 1FFFFE41
write 139 1FFFFE42
write 13a 1FFFFE43
write 13b 1E023644
write 13c 1E320045
write 13d 1E000046
write 13e 1E224447
write 13f 1E668848
write 140 1EAACC49
write 141 1E10004A
write 142 1F11EE4B
write 143 1E100C4C
write 144 1FB7FE4D
write 145 0600024E
write 146 0600224F
write 147 40010050
write 148 40010651
write 149 40094C52
write 14a 400B8E53
write 14b 1E008854
write 14c 4002D055
write 14d 40181E56
write 14e 400BD057
write 14f 40381358
write 150 40181059
write 151 4018125A
write 152 4018005B
write 153 8000005C
write 154 005EE000
write 155 33445566
write 156 00020300
write 157 00020314
write 158 00020318
write 159 00020310
write 15a 0002031C
write 15b 48656C6C
write 15c 6F210A00
write 15d 20000000
write 15e 00020100
write 15f 00020200
write 160 00020200
write 161 00000000
write 162 00000000
write 163 00000000
write 164 00000000
write 165 00000000
write 166 00000000
write 167 00000000
write 168 00000000
write 169 00000000
write 16a 00000000
write 16b 00000000
write 16c 00000000
write 16d 00000000
write 16e 00000000
write 16f 00000000
write 170 00000000
write 171 00000000
write 172 00000000
write 173 00000000
write 174 00000000
write 175 00000000
write 176 00000000
write 177 00000000
write 178 00000000
write 179 00000000
write 17a 00000000
write 17b 00000000
write 17c 00000000
write 17d 00000000
write 17e 00000000
write 17f 00000000
write 180 00000000
write 181 00000000
write 182 00000000
write 183 00000000
write 184 00000000
write 185 00000000
write 186 00000000
write 187 00000000
write 188 00000000
write 189 00000000
write 18a 00000000
write 18b 00000000
write 18c 00000000
write 18d 00000000
write 18e 00000000
write 18f 00000000
write 190 00000000
write 191 00000000
write 192 00000000
write 193 00000000
write 194 00000000
write 195 00000000
write 196 00000000
write 197 00000000
write 198 00000000
write 199 00000000
write 19a 00000000
write 19b 00000000
write 19c 00000000
write 19d 00000000
write 19e 00000000
write 19f 00000000
write 1a0 00000000
write 1a1 00000000
write 1a2 00000000
write 1a3 00000000
write 1a4 00000000
write 1a5 00000000
write 1a6 00000000
write 1a7 00000000
write 1a8 00000000
write 1a9 00000000
write 1aa 00000000
write 1ab 00000000
write 1ac 00000000
write 1ad 00000000
write 1ae 00000000
write 1af 00000000
write 1b0 00000000
write 1b1 00000000
write 1b2 00000000
write 1b3 00000000
write 1b4 00000000
write 1b5 00000000
write 1b6 00000000
write 1b7 00000000
write 1b8 00000000
write 1b9 00000000
write 1ba 00000000
write 1bb 00000000
write 1bc 00000000
write 1bd 00000000
write 1be 00000000
write 1bf 00000000
write 1c0 00000000
write 1c1 00000000
write 1c2 00000000
write 1c3 00000000
write 1c4 00000000
write 1c5 00000000
write 1c6 00000000
write 1c7 00000000
write 1c8 00000000
write 1c9 00000000
write 1ca 00000000
write 1cb 00000000
write 1cc 00000000
write 1cd 00000000
write 1ce 00000000
write 1cf 00000000
write 1d0 00000000
write 1d1 00000000
write 1d2 00000000
write 1d3 00000000
write 1d4 00000000
write 1d5 00000000
write 1d6 00000000
write 1d7 00000000
write 1d8 00000000
write 1d9 00000000
write 1da 00000000
write 1db 00000000
write 1dc 00000000
write 1dd 00000000
write 1de 00000000
write 1df 00000000
write 1e0 00000000
write 1e1 00000000
write 1e2 00000000
write 1e3 00000000
write 1e4 00000000
write 1e5 00000000
write 1e6 00000000
write 1e7 00000000
write 1e8 00000000
write 1e9 00000000
write 1ea 00000000
write 1eb 00000000
write 1ec 00000000
write 1ed 00000000
write 1ee 00000000
write 1ef 00000000
write 1f0 00000000
write 1f1 00000000
write 1f2 00000000
write 1f3 00000000
write 1f4 00000000
write 1f5 00000000
write 1f6 00000000
write 1f7 00000000
write 1f8 00000000
write 1f9 00000000
write 1fa 00000000
write 1fb 00000000
write 1fc 00000000
write 1fd 00000000
write 1fe 00000000
write 1ff 00000000
write 200 00000000
write 201 00000000
write 202 00000000
write 203 00000000
write 204 00000000
write 205 00000000
write 206 00000000
write 207 00000000
write 208 00000000
write 209 00000000
write 20a 00000000
write 20b 00000000
write 20c 00000000
write 20d 00000000
write 20e 00000000
write 20f 00000000
write 210 00000000
write 211 00000000
write 212 00000000
write 213 00000000
write 214 00000000
write 215 00000000
write 216 00000000
write 217 00000000
write 218 00000000
write 219 00000000
write 21a 00000000
write 21b 00000000
write 21c 00000000
write 21d 00000000
write 21e 00000000
write 21f 00000000
write 220 00000000
write 221 00000000
write 222 00000000
write 223 00000000
write 224 00000000
write 225 00000000
write 226 00000000
write 227 00000000
write 228 00000000
write 229 00000000
write 22a 00000000
write 22b 00000000
write 22c 00000000
write 22d 00000000
write 22e 00000000
write 22f 00000000
write 230 00000000
write 231 00000000
write 232 00000000
write 233 00000000
write 234 00000000
write 235 00000000
write 236 00000000
write 237 00000000
write 238 00000000
write 239 00000000
write 23a 00000000
write 23b 00000000
write 23c 00000000
write 23d 00000000
write 23e 00000000
write 23f 00000000
write 240 00000000
write 241 00000000
write 242 00000000
write 243 00000000
write 244 00000000
write 245 00000000
write 246 00000000
write 247 00000000
write 248 00000000
write 249 00000000
write 24a 00000000
write 24b 00000000
write 24c 00000000
write 24d 00000000
write 24e 00000000
write 24f 00000000
write 250 00000000
write 251 00000000
write 252 00000000
write 253 00000000
write 254 00000000
write 255 00000000
write 256 00000000
write 257 00000000
write 258 00000000
write 259 00000000
write 25a 00000000
write 25b 00000000
write 25c 00000000
write 25d 00000000
write 25e 00000000
write 25f 00000000
write 260 00000000
write 261 00000000
write 262 00000000
write 263 00000000
write 264 00000000
write 265 00000000
write 266 00000000
write 267 00000000
write 268 00000000
write 269 00000000
write 26a 00000000
write 26b 00000000
write 26c 00000000
write 26d 00000000
write 26e 00000000
write 26f 00000000
write 270 00000000
write 271 00000000
write 272 00000000
write 273 00000000
write 274 00000000
write 275 00000000
write 276 00000000
write 277 00000000
write 278 00000000
write 279 00000000
write 27a 00000000
write 27b 00000000
write 27c 00000000
write 27d 00000000
write 27e 00000000
write 27f 00000000
write 280 00000000
write 281 00000000
write 282 00000000
write 283 00000000
write 284 00000000
write 285 00000000
write 286 00000000
write 287 00000000
write 288 00000000
write 289 00000000
write 28a 00000000
write 28b 00000000
write 28c 00000000
write 28d 00000000
write 28e 00000000
write 28f 00000000
write 290 00000000
write 291 00000000
write 292 00000000
write 293 00000000
write 294 00000000
write 295 00000000
write 296 00000000
write 297 00000000
write 298 00000000
write 299 00000000
write 29a 00000000
write 29b 00000000
write 29c 00000000
write 29d 00000000
write 29e 00000000
write 29f 00000000
write 2a0 00000000
write 2a1 00000000
write 2a2 00000000
write 2a3 00000000
write 2a4 00000000
write 2a5 00000000
write 2a6 00000000
write 2a7 00000000
write 2a8 00000000
write 2a9 00000000
write 2aa 00000000
write 2ab 00000000
write 2ac 00000000
write 2ad 00000000
write 2ae 00000000
write 2af 00000000
write 2b0 00000000
write 2b1 00000000
write 2b2 00000000
write 2b3 00000000
write 2b4 00000000
write 2b5 00000000
write 2b6 00000000
write 2b7 00000000
write 2b8 00000000
write 2b9 00000000
write 2ba 00000000
write 2bb 00000000
write 2bc 00000000
write 2bd 00000000
write 2be 00000000
write 2bf 00000000
write 2c0 00000000
write 2c1 00000000
write 2c2 00000000
write 2c3 00000000
write 2c4 00000000
write 2c5 00000000
write 2c6 00000000
write 2c7 00000000
write 2c8 00000000
write 2c9 00000000
write 2ca 00000000
write 2cb 00000000
write 2cc 00000000
write 2cd 00000000
write 2ce 00000000
write 2cf 00000000
write 2d0 00000000
write 2d1 00000000
write 2d2 00000000
write 2d3 00000000
write 2d4 00000000
write 2d5 00000000
write 2d6 00000000
write 2d7 00000000
write 2d8 00000000
write 2d9 00000000
write 2da 00000000
write 2db 00000000
write 2dc 00000000
write 2dd 00000000
write 2de 00000000
write 2df 00000000
write 2e0 00000000
write 2e1 00000000
write 2e2 00000000
write 2e3 00000000
write 2e4 00000000
write 2e5 00000000
write 2e6 00000000
write 2e7 00000000
write 2e8 00000000
write 2e9 00000000
write 2ea 00000000
write 2eb 00000000
write 2ec 00000000
write 2ed 00000000
write 2ee 00000000
write 2ef 00000000
write 2f0 00000000
write 2f1 00000000
write 2f2 00000000
write 2f3 00000000
write 2f4 00000000
write 2f5 00000000
write 2f6 00000000
write 2f7 00000000
write 2f8 00000000
write 2f9 00000000
write 2fa 00000000
write 2fb 00000000
write 2fc 00000000
write 2fd 00000000
write 2fe 00000000
write 2ff 00000000
write 300 00000000
write 301 00000000
write 302 00000000
write 303 00000000
write 304 00000000
write 305 00000000
write 306 00000000
write 307 00000000
write 308 00000000
write 309 00000000
write 30a 00000000
write 30b 00000000
write 30c 00000000
write 30d 00000000
write 30e 00000000
write 30f 00000000
write 310 00000000
write 311 00000000
write 312 00000000
write 313 00000000
write 314 00000000
write 315 00000000
write 316 00000000
write 317 00000000
write 318 00000000
write 319 00000000
write 31a 00000000
write 31b 00000000
write 31c 00000000
write 31d 00000000
write 31e 00000000
write 31f 00000000
write 320 00000000
write 321 00000000
write 322 00000000
write 323 00000000
write 324 00000000
write 325 00000000
write 326 00000000
write 327 00000000
write 328 00000000
write 329 00000000
write 32a 00000000
write 32b 00000000
write 32c 00000000
write 32d 00000000
write 32e 00000000
write 32f 00000000
write 330 00000000
write 331 00000000
write 332 00000000
write 333 00000000
write 334 00000000
write 335 00000000
write 336 00000000
write 337 00000000
write 338 00000000
write 339 00000000
write 33a 00000000
write 33b 00000000
write 33c 00000000
write 33d 00000000
write 33e 00000000
write 33f 00000000
write 340 00000000
write 341 00000000
write 342 00000000
write 343 00000000
write 344 00000000
write 345 00000000
write 346 00000000
write 347 00000000
write 348 00000000
write 349 00000000
write 34a 00000000
write 34b 00000000
write 34c 00000000
write 34d 00000000
write 34e 00000000
write 34f 00000000
write 350 00000000
write 351 00000000
write 352 00000000
write 353 00000000
write 354 00000000
write 355 00000000
write 356 00000000
write 357 00000000
write 358 00000000
write 359 00000000
write 35a 00000000
write 35b 00000000
write 35c 00000000
write 35d 00000000
write 35e 00000000
write 35f 00000000
write 360 00000000
write 361 00000000
write 362 00000000
write 363 00000000
write 364 00000000
write 365 00000000
write 366 00000000
write 367 00000000
write 368 00000000
write 369 00000000
write 36a 00000000
write 36b 00000000
write 36c 00000000
write 36d 00000000
write 36e 00000000
write 36f 00000000
write 370 00000000
write 371 00000000
write 372 00000000
write 373 00000000
write 374 00000000
write 375 00000000
write 376 00000000
write 377 00000000
write 378 00000000
write 379 00000000
write 37a 00000000
write 37b 00000000
write 37c 00000000
write 37d 00000000
write 37e 00000000
write 37f 00000000
write 380 00000000
write 381 00000000
write 382 00000000
write 383 00000000
write 384 00000000
write 385 00000000
write 386 00000000
write 387 00000000
write 388 00000000
write 389 00000000
write 38a 00000000
write 38b 00000000
write 38c 00000000
write 38d 00000000
write 38e 00000000
write 38f 00000000
write 390 00000000
write 391 00000000
write 392 00000000
write 393 00000000
write 394 00000000
write 395 00000000
write 396 00000000
write 397 00000000
write 398 00000000
write 399 00000000
write 39a 00000000
write 39b 00000000
write 39c 00000000
write 39d 00000000
write 39e 00000000
write 39f 00000000
write 3a0 00000000
write 3a1 00000000
write 3a2 00000000
write 3a3 00000000
write 3a4 00000000
write 3a5 00000000
write 3a6 00000000
write 3a7 00000000
write 3a8 00000000
write 3a9 00000000
write 3aa 00000000
write 3ab 00000000
write 3ac 00000000
write 3ad 00000000
write 3ae 00000000
write 3af 00000000
write 3b0 00000000
write 3b1 00000000
write 3b2 00000000
write 3b3 00000000
write 3b4 00000000
write 3b5 00000000
write 3b6 00000000
write 3b7 00000000
write 3b8 00000000
write 3b9 00000000
write 3ba 00000000
write 3bb 00000000
write 3bc 00000000
write 3bd 00000000
write 3be 00000000
write 3bf 00000000
write 3c0 00000000
write 3c1 00000000
write 3c2 00000000
write 3c3 00000000
write 3c4 00000000
write 3c5 00000000
write 3c6 00000000
write 3c7 00000000
write 3c8 00000000
write 3c9 00000000
write 3ca 00000000
write 3cb 00000000
write 3cc 00000000
write 3cd 00000000
write 3ce 00000000
write 3cf 00000000
write 3d0 00000000
write 3d1 00000000
write 3d2 00000000
write 3d3 00000000
write 3d4 00000000
write 3d5 00000000
write 3d6 00000000
write 3d7 00000000
write 3d8 00000000
write 3d9 00000000
write 3da 00000000
write 3db 00000000
write 3dc 00000000
write 3dd 00000000
write 3de 00000000
write 3df 00000000
write 3e0 00000000
write 3e1 00000000
write 3e2 00000000
write 3e3 00000000
write 3e4 00000000
write 3e5 00000000
write 3e6 00000000
write 3e7 00000000
hdl/testbench/svec/Manifest.py
View file @ 5765c94d
sim_tool = "modelsim"
top_module="main"
syn_device="xc6slx150t"
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim +incdir+../include/vme64x_bfm +incdir+../include "
include_dirs=[ "../../sim", "../include", "../../ip_cores/vme64x-core/hdl/vme64x-core/sim/vme64x_bfm" ]
files = [ "main.sv" ]
......
hdl/top/spec/Manifest.py 0 → 100644
View file @ 5765c94d
files = ["synthesis_descriptor.vhd",
"wr_spec_tdc.ucf",
"wr_spec_tdc.vhd"];
fetchto = "../../ip_cores"
modules = {
"local" : [ "../../rtl/",
"../../ip_cores/gn4124-core",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores"
]
}
hdl/top/spec/build_wb.sh deleted 100755 → 0
View file @ caaf87ad
#!/bin/bash
wbgen2 -D 1.html -V fmc_tdc_direct_readout_slave.vhd -H record -p fmc_tdc_direct_readout_slave_pkg.vhd -K regs.vh -s defines -C fmctdc-direct.h fmc_tdc_direct_readout_slave.wb
hdl/top/spec/spec_reset_gen.vhd deleted 100644 → 0
View file @ caaf87ad
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
hdl/top/spec/tdc_core_pkg.vhd deleted 100644 → 0
View file @ caaf87ad
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- tdc_core_pkg |
-- |
---------------------------------------------------------------------------------------------------
-- File tdc_core_pkg.vhd |
-- |
-- Description Package containing core wide constants and components |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 07/2011 v0.1 GP First version |
-- 04/2012 v0.2 EG Revamping; Gathering of all the constants, declarations of all the |
-- units; Comments added, signals renamed |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
--=================================================================================================
-- Package declaration for tdc_core_pkg
--=================================================================================================
package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
-- Constant regarding the Mezzanine DAC configuration --
---------------------------------------------------------------------------------------------------
-- Vout = Vref (DAC_WORD/ 65536); for Vout = 1.65V, with Vref = 2.5V the DAC_WORD = xA8F5
constant c_DEFAULT_DAC_WORD : std_logic_vector(23 downto 0) := x"00A8F5";
---------------------------------------------------------------------------------------------------
-- Constants regarding the SDB Devices Definitions --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Devices sdb description
constant c_ONEWIRE_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"0000000000000007",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000602", -- "WB-Onewire.Control " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-Onewire.Control ")));
constant c_SPEC_INFO_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000603", -- "WB-SPEC.CSR " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-SPEC.CSR ")));
constant c_TDC_EIC_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000605", -- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-FMC-TDC.EIC ")));
constant c_I2C_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000606", -- "WB-I2C.Control " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-I2C.Control ")));
constant c_TDC_EIC_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"26ec6086", -- "WB-FMC-TDC.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20131204",
name => "WB-FMC-TDC.EIC ")));
constant c_TDC_CONFIG_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000604", -- "WB-TDC-Core-Config " | md5sum | cut -c1-8
version => x"00000001",
date => x"20130429",
name => "WB-TDC-Core-Config ")));
constant c_TDC_MEM_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"0000000000000FFF",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000601", -- "WB-TDC-Mem " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-TDC-Mem ")));
---------------------------------------------------------------------------------------------------
-- Constants regarding 1 Hz pulse generation --
---------------------------------------------------------------------------------------------------
-- for synthesis: 1 sec = x"07735940" clk_i cycles (1 clk_i cycle = 8ns)
constant c_SYN_CLK_PERIOD : std_logic_vector(31 downto 0) := x"07735940";
-- for simulation: 1 msec = x"0001E848" clk_i cycles (1 clk_i cycle = 8ns)
constant c_SIM_CLK_PERIOD : std_logic_vector(31 downto 0) := x"0001E848";
---------------------------------------------------------------------------------------------------
-- Vector with the 11 ACAM Configuration Registers --
---------------------------------------------------------------------------------------------------
subtype config_register is std_logic_vector(31 downto 0);
type config_vector is array (10 downto 0) of config_register;
---------------------------------------------------------------------------------------------------
-- Constants regarding addressing of the ACAM registers --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Addresses of ACAM configuration registers to be written by the PCIe host
-- corresponds to:
constant c_ACAM_REG0_ADR : std_logic_vector(7 downto 0) := x"00"; -- address 0x51000 of GN4124 BAR 0
constant c_ACAM_REG1_ADR : std_logic_vector(7 downto 0) := x"01"; -- address 0x51004 of GN4124 BAR 0
constant c_ACAM_REG2_ADR : std_logic_vector(7 downto 0) := x"02"; -- address 0x51008 of GN4124 BAR 0
constant c_ACAM_REG3_ADR : std_logic_vector(7 downto 0) := x"03"; -- address 0x5100C of GN4124 BAR 0
constant c_ACAM_REG4_ADR : std_logic_vector(7 downto 0) := x"04"; -- address 0x51010 of GN4124 BAR 0
constant c_ACAM_REG5_ADR : std_logic_vector(7 downto 0) := x"05"; -- address 0x51014 of GN4124 BAR 0
constant c_ACAM_REG6_ADR : std_logic_vector(7 downto 0) := x"06"; -- address 0x51018 of GN4124 BAR 0
constant c_ACAM_REG7_ADR : std_logic_vector(7 downto 0) := x"07"; -- address 0x5101C of GN4124 BAR 0
constant c_ACAM_REG11_ADR : std_logic_vector(7 downto 0) := x"0B"; -- address 0x5102C of GN4124 BAR 0
constant c_ACAM_REG12_ADR : std_logic_vector(7 downto 0) := x"0C"; -- address 0x51030 of GN4124 BAR 0
constant c_ACAM_REG14_ADR : std_logic_vector(7 downto 0) := x"0E"; -- address 0x51038 of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Addresses of ACAM read-only registers, to be written by the ACAM and used within the core to access ACAM timestamps
constant c_ACAM_REG8_ADR : std_logic_vector(7 downto 0) := x"08"; -- not accessible for writing from PCI-e
constant c_ACAM_REG9_ADR : std_logic_vector(7 downto 0) := x"09"; -- not accessible for writing from PCI-e
constant c_ACAM_REG10_ADR : std_logic_vector(7 downto 0) := x"0A"; -- not accessible for writing from PCI-e
---------------------------------------------------------------------------------------------------
-- Addresses of ACAM configuration readback registers, to be written by the ACAM
-- corresponds to:
constant c_ACAM_REG0_RDBK_ADR : std_logic_vector(7 downto 0) := x"10"; -- address 0x51040 of the GN4124 BAR 0
constant c_ACAM_REG1_RDBK_ADR : std_logic_vector(7 downto 0) := x"11"; -- address 0x51044 of the GN4124 BAR 0
constant c_ACAM_REG2_RDBK_ADR : std_logic_vector(7 downto 0) := x"12"; -- address 0x51048 of the GN4124 BAR 0
constant c_ACAM_REG3_RDBK_ADR : std_logic_vector(7 downto 0) := x"13"; -- address 0x5104C of the GN4124 BAR 0
constant c_ACAM_REG4_RDBK_ADR : std_logic_vector(7 downto 0) := x"14"; -- address 0x51050 of the GN4124 BAR 0
constant c_ACAM_REG5_RDBK_ADR : std_logic_vector(7 downto 0) := x"15"; -- address 0x51054 of the GN4124 BAR 0
constant c_ACAM_REG6_RDBK_ADR : std_logic_vector(7 downto 0) := x"16"; -- address 0x51058 of the GN4124 BAR 0
constant c_ACAM_REG7_RDBK_ADR : std_logic_vector(7 downto 0) := x"17"; -- address 0x5105C of the GN4124 BAR 0
constant c_ACAM_REG8_RDBK_ADR : std_logic_vector(7 downto 0) := x"18"; -- address 0x51060 of the GN4124 BAR 0
constant c_ACAM_REG9_RDBK_ADR : std_logic_vector(7 downto 0) := x"19"; -- address 0x51064 of the GN4124 BAR 0
constant c_ACAM_REG10_RDBK_ADR : std_logic_vector(7 downto 0) := x"1A"; -- address 0x51068 of the GN4124 BAR 0
constant c_ACAM_REG11_RDBK_ADR : std_logic_vector(7 downto 0) := x"1B"; -- address 0x5106C of the GN4124 BAR 0
constant c_ACAM_REG12_RDBK_ADR : std_logic_vector(7 downto 0) := x"1C"; -- address 0x51070 of the GN4124 BAR 0
constant c_ACAM_REG14_RDBK_ADR : std_logic_vector(7 downto 0) := x"1E"; -- address 0x51078 of the GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Constants regarding addressing of the TDC core registers --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Addresses of TDC core Configuration registers to be written by the PCIe host
-- corresponds to:
constant c_STARTING_UTC_ADR : std_logic_vector(7 downto 0) := x"20"; -- address 0x51080 of GN4124 BAR 0
constant c_ACAM_INPUTS_EN_ADR : std_logic_vector(7 downto 0) := x"21"; -- address 0x51084 of GN4124 BAR 0
constant c_START_PHASE_ADR : std_logic_vector(7 downto 0) := x"22"; -- address 0x51088 of GN4124 BAR 0
constant c_ONE_HZ_PHASE_ADR : std_logic_vector(7 downto 0) := x"23"; -- address 0x5108C of GN4124 BAR 0
constant c_IRQ_TSTAMP_THRESH_ADR: std_logic_vector(7 downto 0) := x"24"; -- address 0x51090 of GN4124 BAR 0
constant c_IRQ_TIME_THRESH_ADR : std_logic_vector(7 downto 0) := x"25"; -- address 0x51094 of GN4124 BAR 0
constant c_DAC_WORD_ADR : std_logic_vector(7 downto 0) := x"26"; -- address 0x51098 of GN4124 BAR 0
constant c_DEACT_CHAN_ADR : std_logic_vector(7 downto 0) := x"27"; -- address 0x5109C of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Addresses of TDC core Status registers to be written by the different core units
-- corresponds to:
constant c_LOCAL_UTC_ADR : std_logic_vector(7 downto 0) := x"28"; -- address 0x510A0 of GN4124 BAR 0
constant c_IRQ_CODE_ADR : std_logic_vector(7 downto 0) := x"29"; -- address 0x510A4 of GN4124 BAR 0
constant c_WR_INDEX_ADR : std_logic_vector(7 downto 0) := x"2A"; -- address 0x510A8 of GN4124 BAR 0
constant c_CORE_STATUS_ADR : std_logic_vector(7 downto 0) := x"2B"; -- address 0x510AC of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Addresses of the White Rabbit control and status registers
constant c_WRABBIT_STATUS_ADR : std_logic_vector(7 downto 0) := x"2C"; -- address 0x510B0 of GN4124 BAR 0
constant c_WRABBIT_CTRL_ADR : std_logic_vector(7 downto 0) := x"2D"; -- address 0x510B4 of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Address of TDC core Control register
-- corresponds to:
constant c_CTRL_REG_ADR : std_logic_vector(7 downto 0) := x"3F"; -- address 0x510FC of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Constants regarding ACAM retriggers --
---------------------------------------------------------------------------------------------------
-- Number of clk_i cycles corresponding to the Acam retrigger period;
-- through Acam Reg 4 StartTimer the chip is programmed to retrigger every:
-- (15+1) * acam_ref_clk = (15+1) * 32 ns
-- x"00000040" * clk_i = 64 * 8 ns
-- 512 ns
constant c_ACAM_RETRIG_PERIOD : std_logic_vector(31 downto 0) := x"00000040";
-- Used to multiply by 64, which is the retrigger period in clk_i cycles
constant c_ACAM_RETRIG_PERIOD_SHIFT : integer := 6;
---------------------------------------------------------------------------------------------------
-- Constants regarding TDC & SPEC LEDs --
---------------------------------------------------------------------------------------------------
constant c_SPEC_LED_PERIOD_SIM : std_logic_vector(31 downto 0) := x"00004E20"; -- 1 ms at 20 MHz
constant c_SPEC_LED_PERIOD_SYN : std_logic_vector(31 downto 0) := x"01312D00"; -- 1 s at 20 MHz
constant c_BLINK_LGTH_SYN : std_logic_vector(31 downto 0) := x"00BEBC20"; -- 100 ms at 125 MHz
constant c_BLINK_LGTH_SIM : std_logic_vector(31 downto 0) := x"000004E2"; -- 10 us at 125 MHz
--c_RESET_WORD
---------------------------------------------------------------------------------------------------
-- Constants regarding the Circular Buffer --
---------------------------------------------------------------------------------------------------
constant c_CIRCULAR_BUFF_SIZE : unsigned(31 downto 0) := x"00000100";
---------------------------------------------------------------------------------------------------
-- Constants regarding the One-Wire interface --
---------------------------------------------------------------------------------------------------
constant c_FMC_ONEWIRE_NB : integer := 1;
---------------------------------------------------------------------------------------------------
-- Constants regarding the Carrier CSR info --
---------------------------------------------------------------------------------------------------
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
---------------------------------------------------------------------------------------------------
-- Components Declarations --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
component fmc_tdc_mezzanine is
generic
(g_with_wrabbit_core : boolean := FALSE;
g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := FALSE);
port
-- 62.5MHz clock and synchronous reset
(clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
-- Signals from the clks_rsts_manager unit
clk_ref_0_i : in std_logic;
rst_ref_0_i : in std_logic;
-- TDC core
acam_refclk_r_edge_p_i : in std_logic;
send_dac_word_p_o : out std_logic;
dac_word_o : out std_logic_vector(23 downto 0);
start_from_fpga_o : out std_logic;
err_flag_i : in std_logic;
int_flag_i : in std_logic;
start_dis_o : out std_logic;
stop_dis_o : out std_logic;
data_bus_io : inout std_logic_vector(27 downto 0);
address_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic;
oe_n_o : out std_logic;
rd_n_o : out std_logic;
wr_n_o : out std_logic;
ef1_i : in std_logic;
ef2_i : in std_logic;
tdc_in_fpga_1_i : in std_logic;
tdc_in_fpga_2_i : in std_logic;
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
enable_inputs_o : out std_logic;
term_en_1_o : out std_logic;
term_en_2_o : out std_logic;
term_en_3_o : out std_logic;
term_en_4_o : out std_logic;
term_en_5_o : out std_logic;
tdc_led_status_o : out std_logic;
tdc_led_trig1_o : out std_logic;
tdc_led_trig2_o : out std_logic;
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
-- White Rabbit core
wrabbit_link_up_i : in std_logic;
wrabbit_time_valid_i : in std_logic;
wrabbit_cycles_i : in std_logic_vector(27 downto 0);
wrabbit_utc_i : in std_logic_vector(31 downto 0);
wrabbit_clk_aux_lock_en_o : out std_logic;
wrabbit_clk_aux_locked_i : in std_logic;
wrabbit_clk_dmtd_locked_i : in std_logic;
wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
wrabbit_dac_wr_p_i : in std_logic;
-- WISHBONE interface with the GN4124/VME_core
-- for the core configuration | timestamps retrieval | core interrupts | 1Wire | I2C
wb_tdc_csr_adr_i : in std_logic_vector(31 downto 0);
wb_tdc_csr_dat_i : in std_logic_vector(31 downto 0);
wb_tdc_csr_cyc_i : in std_logic;
wb_tdc_csr_sel_i : in std_logic_vector(3 downto 0);
wb_tdc_csr_stb_i : in std_logic;
wb_tdc_csr_we_i : in std_logic;
wb_tdc_csr_dat_o : out std_logic_vector(31 downto 0);
wb_tdc_csr_ack_o : out std_logic;
wb_tdc_csr_stall_o : out std_logic;
wb_irq_o : out std_logic;
-- I2C EEPROM interface
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_o : out std_logic;
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
-- 1-wire UniqueID&Thermometer interface
onewire_b : inout std_logic);
end component;
---------------------------------------------------------------------------------------------------
component fmc_tdc_core
generic
(g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := FALSE);
port
(clk_125m_i : in std_logic;
rst_i : in std_logic;
acam_refclk_r_edge_p_i : in std_logic;
send_dac_word_p_o : out std_logic;
dac_word_o : out std_logic_vector(23 downto 0);
start_from_fpga_o : out std_logic;
err_flag_i : in std_logic;
int_flag_i : in std_logic;
start_dis_o : out std_logic;
stop_dis_o : out std_logic;
data_bus_io : inout std_logic_vector(27 downto 0);
address_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic;
oe_n_o : out std_logic;
rd_n_o : out std_logic;
wr_n_o : out std_logic;
ef1_i : in std_logic;
ef2_i : in std_logic;
tdc_in_fpga_1_i : in std_logic;
tdc_in_fpga_2_i : in std_logic;
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
enable_inputs_o : out std_logic;
term_en_1_o : out std_logic;
term_en_2_o : out std_logic;
term_en_3_o : out std_logic;
term_en_4_o : out std_logic;
term_en_5_o : out std_logic;
tdc_led_status_o : out std_logic;
tdc_led_trig1_o : out std_logic;
tdc_led_trig2_o : out std_logic;
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0);
wrabbit_synched_i : in std_logic;
wrabbit_tai_p_i : in std_logic;
wrabbit_tai_i : in std_logic_vector(31 downto 0);
irq_tstamp_p_o : out std_logic;
irq_time_p_o : out std_logic;
irq_acam_err_p_o : out std_logic;
tdc_config_wb_adr_i : in std_logic_vector(g_span-1 downto 0);
tdc_config_wb_dat_i : in std_logic_vector(g_width-1 downto 0);
tdc_config_wb_stb_i : in std_logic;
tdc_config_wb_we_i : in std_logic;
tdc_config_wb_cyc_i : in std_logic;
tdc_config_wb_dat_o : out std_logic_vector(g_width-1 downto 0);
tdc_config_wb_ack_o : out std_logic;
tdc_mem_wb_adr_i : in std_logic_vector(31 downto 0);
tdc_mem_wb_dat_i : in std_logic_vector(31 downto 0);
tdc_mem_wb_stb_i : in std_logic;
tdc_mem_wb_we_i : in std_logic;
tdc_mem_wb_cyc_i : in std_logic;
tdc_mem_wb_ack_o : out std_logic;
tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0);
tdc_mem_wb_stall_o : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
component wrabbit_sync is
generic
(g_simulation : boolean;
g_with_wrabbit_core : boolean);
port
(clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_ref_i : in std_logic;
wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
wrabbit_dac_wr_p_i : in std_logic;
wrabbit_link_up_i : in std_logic;
wrabbit_time_valid_i : in std_logic; -- this is i te clk_ref_0 domain, no??
wrabbit_clk_aux_lock_en_o : out std_logic;
wrabbit_clk_aux_locked_i : in std_logic;
wrabbit_clk_dmtd_locked_i : in std_logic;
wrabbit_synched_o : out std_logic;
wrabbit_reg_i : in std_logic_vector(31 downto 0);
wrabbit_reg_o : out std_logic_vector(31 downto 0));
end component;
---------------------------------------------------------------------------------------------------
component spec_serial_dac -- for White Rabbit
generic
(g_num_data_bits : integer;
g_num_extra_bits : integer;
g_num_cs_select : integer);
port
(clk_i : in std_logic;
rst_n_i : in std_logic;
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
load_i : in std_logic;
sclk_divsel_i : in std_logic_vector(2 downto 0);
dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
xdone_o : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
component xvme64x_core
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic;
irq_ack_o : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
component decr_counter
generic
(width : integer := 32);
port
(clk_i : in std_logic;
rst_i : in std_logic;
counter_load_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0);
-------------------------------------------------------------
counter_is_zero_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0));
-------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component free_counter is
generic
(width : integer := 32);
port
(clk_i : in std_logic;
counter_en_i : in std_logic;
rst_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0);
-------------------------------------------------------------
counter_is_zero_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0));
-------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component incr_counter
generic
(width : integer := 32);
port
(clk_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0);
counter_incr_en_i : in std_logic;
rst_i : in std_logic;
-------------------------------------------------------------
counter_is_full_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0));
-------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
component start_retrig_ctrl
generic
(g_width : integer := 32);
port
(clk_i : in std_logic;
rst_i : in std_logic;
acam_intflag_f_edge_p_i : in std_logic;
utc_p_i : in std_logic;
----------------------------------------------------------------------
current_retrig_nb_o : out std_logic_vector(g_width-1 downto 0);
roll_over_incr_recent_o : out std_logic;
clk_i_cycles_offset_o : out std_logic_vector(g_width-1 downto 0);
roll_over_nb_o : out std_logic_vector(g_width-1 downto 0);
retrig_nb_offset_o : out std_logic_vector(g_width-1 downto 0));
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component local_pps_gen
generic
(g_width : integer := 32);
port
(acam_refclk_r_edge_p_i : in std_logic;
clk_i : in std_logic;
clk_period_i : in std_logic_vector(g_width-1 downto 0);
load_utc_p_i : in std_logic;
pulse_delay_i : in std_logic_vector(g_width-1 downto 0);
rst_i : in std_logic;
starting_utc_i : in std_logic_vector(g_width-1 downto 0);
----------------------------------------------------------------------
local_utc_o : out std_logic_vector(g_width-1 downto 0);
local_utc_p_o : out std_logic);
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component data_engine
port
(acam_ack_i : in std_logic;
acam_dat_i : in std_logic_vector(31 downto 0);
clk_i : in std_logic;
rst_i : in std_logic;
acam_ef1_i : in std_logic;
acam_ef1_meta_i : in std_logic;
acam_ef2_i : in std_logic;
acam_ef2_meta_i : in std_logic;
activate_acq_p_i : in std_logic;
deactivate_acq_p_i : in std_logic;
acam_wr_config_p_i : in std_logic;
acam_rdbk_config_p_i : in std_logic;
acam_rdbk_status_p_i : in std_logic;
acam_rdbk_ififo1_p_i : in std_logic;
acam_rdbk_ififo2_p_i : in std_logic;
acam_rdbk_start01_p_i : in std_logic;
acam_rst_p_i : in std_logic;
acam_config_i : in config_vector;
start_from_fpga_i : in std_logic;
----------------------------------------------------------------------
state_active_p_o : out std_logic;
acam_adr_o : out std_logic_vector(7 downto 0);
acam_cyc_o : out std_logic;
acam_dat_o : out std_logic_vector(31 downto 0);
acam_stb_o : out std_logic;
acam_we_o : out std_logic;
acam_config_rdbk_o : out config_vector;
acam_ififo1_o : out std_logic_vector(31 downto 0);
acam_ififo2_o : out std_logic_vector(31 downto 0);
acam_start01_o : out std_logic_vector(31 downto 0);
acam_tstamp1_o : out std_logic_vector(31 downto 0);
acam_tstamp1_ok_p_o : out std_logic;
acam_tstamp2_o : out std_logic_vector(31 downto 0);
acam_tstamp2_ok_p_o : out std_logic);
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component reg_ctrl
generic
(g_span : integer := 32;
g_width : integer := 32);
port
(clk_i : in std_logic;
rst_i : in std_logic;
tdc_config_wb_adr_i : in std_logic_vector(g_span-1 downto 0);
tdc_config_wb_cyc_i : in std_logic;
tdc_config_wb_dat_i : in std_logic_vector(g_width-1 downto 0);
tdc_config_wb_stb_i : in std_logic;
tdc_config_wb_we_i : in std_logic;
acam_config_rdbk_i : in config_vector;
acam_ififo1_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo2_i : in std_logic_vector(g_width-1 downto 0);
acam_start01_i : in std_logic_vector(g_width-1 downto 0);
local_utc_i : in std_logic_vector(g_width-1 downto 0);
irq_code_i : in std_logic_vector(g_width-1 downto 0);
wr_index_i : in std_logic_vector(g_width-1 downto 0);
core_status_i : in std_logic_vector(g_width-1 downto 0);
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
----------------------------------------------------------------------
tdc_config_wb_ack_o : out std_logic;
tdc_config_wb_dat_o : out std_logic_vector(g_width-1 downto 0);
activate_acq_p_o : out std_logic;
deactivate_acq_p_o : out std_logic;
deactivate_chan_o : out std_logic_vector(4 downto 0);
acam_wr_config_p_o : out std_logic;
acam_rdbk_config_p_o : out std_logic;
acam_rdbk_status_p_o : out std_logic;
acam_rdbk_ififo1_p_o : out std_logic;
acam_rdbk_ififo2_p_o : out std_logic;
acam_rdbk_start01_p_o : out std_logic;
acam_rst_p_o : out std_logic;
load_utc_p_o : out std_logic;
irq_tstamp_threshold_o : out std_logic_vector(g_width-1 downto 0);
irq_time_threshold_o : out std_logic_vector(g_width-1 downto 0);
send_dac_word_p_o : out std_logic;
dac_word_o : out std_logic_vector(23 downto 0);
dacapo_c_rst_p_o : out std_logic;
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
acam_inputs_en_o : out std_logic_vector(g_width-1 downto 0);
start_phase_o : out std_logic_vector(g_width-1 downto 0);
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0);
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0));
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component acam_timecontrol_interface
port
(err_flag_i : in std_logic;
int_flag_i : in std_logic;
acam_refclk_r_edge_p_i : in std_logic;
utc_p_i : in std_logic;
clk_i : in std_logic;
activate_acq_p_i : in std_logic;
rst_i : in std_logic;
state_active_p_i : in std_logic;
deactivate_acq_p_i : in std_logic;
----------------------------------------------------------------------
start_from_fpga_o : out std_logic;
stop_dis_o : out std_logic;
acam_errflag_r_edge_p_o : out std_logic;
acam_errflag_f_edge_p_o : out std_logic;
acam_intflag_f_edge_p_o : out std_logic);
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component data_formatting
port
(tstamp_wr_wb_ack_i : in std_logic;
tstamp_wr_dat_i : in std_logic_vector(127 downto 0);
acam_tstamp1_i : in std_logic_vector(31 downto 0);
acam_tstamp1_ok_p_i : in std_logic;
acam_tstamp2_i : in std_logic_vector(31 downto 0);
acam_tstamp2_ok_p_i : in std_logic;
clk_i : in std_logic;
dacapo_c_rst_p_i : in std_logic;
deactivate_chan_i : in std_logic_vector(4 downto 0);
rst_i : in std_logic;
roll_over_incr_recent_i : in std_logic;
clk_i_cycles_offset_i : in std_logic_vector(31 downto 0);
roll_over_nb_i : in std_logic_vector(31 downto 0);
utc_i : in std_logic_vector(31 downto 0);
retrig_nb_offset_i : in std_logic_vector(31 downto 0);
utc_p_i : in std_logic;
----------------------------------------------------------------------
tstamp_wr_wb_adr_o : out std_logic_vector(7 downto 0);
tstamp_wr_wb_cyc_o : out std_logic;
tstamp_wr_dat_o : out std_logic_vector(127 downto 0);
tstamp_wr_wb_stb_o : out std_logic;
tstamp_wr_wb_we_o : out std_logic;
tstamp_wr_p_o : out std_logic;
acam_channel_o : out std_logic_vector(2 downto 0);
wr_index_o : out std_logic_vector(31 downto 0));
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component irq_generator is
generic
(g_width : integer := 32);
port
(clk_i : in std_logic;
rst_i : in std_logic;
irq_tstamp_threshold_i : in std_logic_vector(g_width-1 downto 0);
irq_time_threshold_i : in std_logic_vector(g_width-1 downto 0);
activate_acq_p_i : in std_logic;
deactivate_acq_p_i : in std_logic;
tstamp_wr_p_i : in std_logic;
acam_errflag_r_edge_p_i : in std_logic;
----------------------------------------------------------------------
irq_tstamp_p_o : out std_logic;
irq_acam_err_p_o : out std_logic;
irq_time_p_o : out std_logic);
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component tdc_eic
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_tdc_tstamps_i : in std_logic;
irq_tdc_time_i : in std_logic;
irq_tdc_acam_err_i : in std_logic);
end component tdc_eic;
---------------------------------------------------------------------------------------------------
component clks_rsts_manager
generic
(nb_of_reg : integer := 68);
port
(clk_sys_i : in std_logic;
acam_refclk_p_i : in std_logic;
acam_refclk_n_i : in std_logic;
tdc_125m_clk_p_i : in std_logic;
tdc_125m_clk_n_i : in std_logic;
rst_n_i : in std_logic;
pll_status_i : in std_logic;
pll_sdo_i : in std_logic;
send_dac_word_p_i : in std_logic;
dac_word_i : in std_logic_vector(23 downto 0);
wrabbit_dac_wr_p_i : in std_logic;
wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
----------------------------------------------------------------------
tdc_125m_clk_o : out std_logic;
internal_rst_o : out std_logic;
acam_refclk_r_edge_p_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_dac_sync_n_o : out std_logic;
pll_sdi_o : out std_logic;
pll_sclk_o : out std_logic;
pll_status_o : out std_logic);
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component carrier_info
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
carrier_info_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
carrier_info_carrier_reserved_i : in std_logic_vector(11 downto 0);
carrier_info_carrier_type_i : in std_logic_vector(15 downto 0);
carrier_info_stat_fmc_pres_i : in std_logic;
carrier_info_stat_p2l_pll_lck_i : in std_logic;
carrier_info_stat_sys_pll_lck_i : in std_logic;
carrier_info_stat_ddr3_cal_done_i : in std_logic;
carrier_info_stat_reserved_i : in std_logic_vector(27 downto 0);
carrier_info_ctrl_led_green_o : out std_logic;
carrier_info_ctrl_led_red_o : out std_logic;
carrier_info_ctrl_dac_clr_n_o : out std_logic;
carrier_info_ctrl_reserved_o : out std_logic_vector(28 downto 0);
carrier_info_rst_fmc0_n_o : out std_logic;
carrier_info_rst_fmc0_n_i : in std_logic;
carrier_info_rst_fmc0_n_load_o : out std_logic;
carrier_info_rst_reserved_o : out std_logic_vector(30 downto 0));
end component carrier_info;
---------------------------------------------------------------------------------------------------
component leds_manager is
generic
(g_width : integer := 32;
values_for_simul : boolean := FALSE);
port
(clk_i : in std_logic;
rst_i : in std_logic;
utc_p_i : in std_logic;
acam_inputs_en_i : in std_logic_vector(g_width-1 downto 0);
acam_channel_i : in std_logic_vector(5 downto 0);
tstamp_wr_p_i : in std_logic;
----------------------------------------------------------------------
tdc_led_status_o : out std_logic;
tdc_led_trig1_o : out std_logic;
tdc_led_trig2_o : out std_logic;
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic);
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component acam_databus_interface
port
(ef1_i : in std_logic;
ef2_i : in std_logic;
data_bus_io : inout std_logic_vector(27 downto 0);
clk_i : in std_logic;
rst_i : in std_logic;
adr_i : in std_logic_vector(7 downto 0);
cyc_i : in std_logic;
dat_i : in std_logic_vector(31 downto 0);
stb_i : in std_logic;
we_i : in std_logic;
----------------------------------------------------------------------
adr_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic;
oe_n_o : out std_logic;
rd_n_o : out std_logic;
wr_n_o : out std_logic;
ack_o : out std_logic;
ef1_o : out std_logic;
ef1_meta_o : out std_logic;
ef2_o : out std_logic;
ef2_meta_o : out std_logic;
dat_o : out std_logic_vector(31 downto 0));
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component circular_buffer
port
(clk_i : in std_logic;
tstamp_wr_rst_i : in std_logic;
tstamp_wr_stb_i : in std_logic;
tstamp_wr_cyc_i : in std_logic;
tstamp_wr_we_i : in std_logic;
tstamp_wr_adr_i : in std_logic_vector(7 downto 0);
tstamp_wr_dat_i : in std_logic_vector(127 downto 0);
tdc_mem_wb_rst_i : in std_logic;
tdc_mem_wb_stb_i : in std_logic;
tdc_mem_wb_cyc_i : in std_logic;
tdc_mem_wb_we_i : in std_logic;
tdc_mem_wb_adr_i : in std_logic_vector(31 downto 0);
tdc_mem_wb_dat_i : in std_logic_vector(31 downto 0);
--------------------------------------------------
tstamp_wr_ack_p_o : out std_logic;
tstamp_wr_dat_o : out std_logic_vector(127 downto 0);
tdc_mem_wb_ack_o : out std_logic;
tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0);
tdc_mem_wb_stall_o : out std_logic);
--------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component blk_mem_circ_buff_v6_4
port
(clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
dina : in std_logic_vector(127 downto 0);
ena : in std_logic;
wea : in std_logic_vector(0 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(9 downto 0);
dinb : in std_logic_vector(31 downto 0);
enb : in std_logic;
web : in std_logic_vector(0 downto 0);
--------------------------------------------------
douta : out std_logic_vector(127 downto 0);
doutb : out std_logic_vector(31 downto 0));
--------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component spec_reset_gen is
port
(clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
component dma_eic
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_dma_done_i : in std_logic;
irq_dma_error_i : in std_logic);
end component dma_eic;
---------------------------------------------------------------------------------------------------
component irq_controller
port
(clk_i : in std_logic;
rst_n_i : in std_logic;
irq_src_p_i : in std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
----------------------------------------------------------------------
wb_dat_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
irq_p_o : out std_logic);
end component irq_controller;
end tdc_core_pkg;
--=================================================================================================
-- package body
--=================================================================================================
package body tdc_core_pkg is
end tdc_core_pkg;
--=================================================================================================
-- package end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
hdl/top/spec/wr_spec_tdc.ucf
View file @ 5765c94d
......@@ -35,15 +35,139 @@ NET "tdc_clk_125m_n_i" IOSTANDARD = "LVDS_25";
NET "tdc_clk_125m_n_i" TNM_NET = "tdc_clk_125m_n_i";
TIMESPEC TS_tdc_clk_125m_n_i = PERIOD "tdc_clk_125m_n_i" 8 ns HIGH 50%;
NET "p2l_clk_n_i" LOC = M19;
NET "p2l_clk_n_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_clk_p_i" LOC = M20;
NET "p2l_clk_p_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_clk_p_i" TNM_NET = "p2l_clk_p_i";
TIMESPEC TS_p2l_clk_p_i = PERIOD "p2l_clk_p_i" 5 ns HIGH 50%;
NET "p2l_clk_n_i" TNM_NET = "p2l_clk_n_i";
TIMESPEC TS_p2l_clk_n_i = PERIOD "p2l_clk_n_i" 5 ns HIGH 50%;
#####################################################################
### Gennum ports
#####################################################################
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
#----------------------------------------
# FMC slot
......@@ -192,125 +316,6 @@ NET "mezz_sys_sda_b" IOSTANDARD = "LVCMOS25";
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "rst_n_a_i" LOC = N20;
NET "rst_n_a_i" IOSTANDARD = "LVCMOS18";
NET "l2p_clk_n_o" LOC = K22;
NET "l2p_clk_n_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "l2p_clk_p_o" LOC = K21;
NET "l2p_clk_p_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "l2p_dframe_o" LOC = U22;
NET "l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "l2p_edb_o" LOC = U20;
NET "l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "l2p_rdy_i" LOC = U19;
NET "l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "l2p_valid_o" LOC = T18;
NET "l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "l_wr_rdy_i[0]" LOC = R20;
NET "l_wr_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "l_wr_rdy_i[1]" LOC = T22;
NET "l_wr_rdy_i[1]" IOSTANDARD = "SSTL18_I";
#NET "L_CLKN" LOC = N19;
#NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
#NET "L_CLKP" LOC = P20;
#NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_dframe_i" LOC = J22;
NET "p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "p2l_rdy_o" LOC = J16;
NET "p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "p2l_valid_i" LOC = L19;
NET "p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "p_rd_d_rdy_i[0]" LOC = N16;
NET "p_rd_d_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "p_rd_d_rdy_i[1]" LOC = P19;
NET "p_rd_d_rdy_i[1]" IOSTANDARD = "SSTL18_I";
NET "p_wr_rdy_o[0]" LOC = L15;
NET "p_wr_rdy_o[0]" IOSTANDARD = "SSTL18_I";
NET "p_wr_rdy_o[1]" LOC = K16;
NET "p_wr_rdy_o[1]" IOSTANDARD = "SSTL18_I";
NET "p_wr_req_i[0]" LOC = M22;
NET "p_wr_req_i[0]" IOSTANDARD = "SSTL18_I";
NET "p_wr_req_i[1]" LOC = M21;
NET "p_wr_req_i[1]" IOSTANDARD = "SSTL18_I";
NET "rx_error_o" LOC = J17;
NET "rx_error_o" IOSTANDARD = "SSTL18_I";
NET "tx_error_i" LOC = M17;
NET "tx_error_i" IOSTANDARD = "SSTL18_I";
NET "vc_rdy_i[0]" LOC = B21;
NET "vc_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "vc_rdy_i[1]" LOC = B22;
NET "vc_rdy_i[1]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[0]" LOC = P16;
NET "l2p_data_o[0]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[1]" LOC = P21;
NET "l2p_data_o[1]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[2]" LOC = P18;
NET "l2p_data_o[2]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[3]" LOC = T20;
NET "l2p_data_o[3]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[4]" LOC = V21;
NET "l2p_data_o[4]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[5]" LOC = V19;
NET "l2p_data_o[5]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[6]" LOC = W22;
NET "l2p_data_o[6]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[7]" LOC = Y22;
NET "l2p_data_o[7]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[8]" LOC = P22;
NET "l2p_data_o[8]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[9]" LOC = R22;
NET "l2p_data_o[9]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[10]" LOC = T21;
NET "l2p_data_o[10]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[11]" LOC = T19;
NET "l2p_data_o[11]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[12]" LOC = V22;
NET "l2p_data_o[12]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[13]" LOC = V20;
NET "l2p_data_o[13]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[14]" LOC = W20;
NET "l2p_data_o[14]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[15]" LOC = Y21;
NET "l2p_data_o[15]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[0]" LOC = K20;
NET "p2l_data_i[0]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[1]" LOC = H22;
NET "p2l_data_i[1]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[2]" LOC = H21;
NET "p2l_data_i[2]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[3]" LOC = L17;
NET "p2l_data_i[3]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[4]" LOC = K17;
NET "p2l_data_i[4]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[5]" LOC = G22;
NET "p2l_data_i[5]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[6]" LOC = G20;
NET "p2l_data_i[6]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[7]" LOC = K18;
NET "p2l_data_i[7]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[8]" LOC = K19;
NET "p2l_data_i[8]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[9]" LOC = H20;
NET "p2l_data_i[9]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[10]" LOC = J19;
NET "p2l_data_i[10]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[11]" LOC = E22;
NET "p2l_data_i[11]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[12]" LOC = E20;
NET "p2l_data_i[12]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[13]" LOC = F22;
NET "p2l_data_i[13]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[14]" LOC = F21;
NET "p2l_data_i[14]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[15]" LOC = H19;
NET "p2l_data_i[15]" IOSTANDARD = "SSTL18_I";
NET "irq_p_o" LOC = U16;
NET "irq_p_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
......@@ -326,7 +331,6 @@ NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC Presence
#----------------------------------------
NET "prsnt_m2c_n_i" LOC = AB14;
NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
......@@ -394,14 +398,12 @@ NET "uart_txd_o" IOSTANDARD=LVCMOS25;
#----------------------------------------
# False Path
#----------------------------------------
# GN4124
NET "rst_n_a_i" TIG;
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clk_62m5_sys" TNM_NET = clk_62m5_sys;
TIMESPEC ts_ignore_crossclock = FROM "clk_62m5_sys" TO "tdc_clk_125m_p_i" 10ns DATAPATHONLY;
......@@ -412,9 +414,6 @@ TIMESPEC ts_ignore_xclock2 = FROM "clk_125m_pllref_p_i" TO "clk_62m5_sys" 10ns D
TIMESPEC ts_x3 = FROM "clk_62m5_sys" TO "U_GTP_ch1_rx_divclk" 10ns DATAPATHONLY;
TIMESPEC TS_x4 = FROM "U_GTP_ch1_rx_divclk" TO "clk_62m5_sys" 10ns DATAPATHONLY;
PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 125 MHz HIGH 50%;
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
......@@ -424,3 +423,8 @@ TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 2 ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/08
INST "U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o" TNM = rx_ts_trig;
TIMESPEC TS_RXTS = FROM "rx_ts_trig" TO "FFS" 2 ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2015/05/19
NET "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = cmp_gn4124_core/cmp_clk_in/feedback;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
hdl/top/spec/wr_spec_tdc.vhd
View file @ 5765c94d
......@@ -40,9 +40,6 @@
-- the FPGA startup, using the 62.5MHz clock. The clks_rsts_manager is keeping the |
-- the TDC mezzanine core under reset until the respective PLL gets locked. |
-- |
-- For the TDC mezzanine core, the crossing from the 125 MHz world to the 62.5 MHz |
-- world takes place through the dedicated clock_crossing module. |
-- |
-- ___________________________________________________________________________ |
-- | | |
-- | ____________________________ ___ _____ | |
......@@ -50,14 +47,14 @@
-- |------|------| WRabbit core, PHY, DAC | <----------> | | | | | |
-- \/ | |____________________________| | | | | | |
-- ________ | 62.5MHz | | | | | |
-- | | | ___________________ | | | | | |
-- | DAC |<->| | clks rsts manager | | | | G | | |
-- | PLL | |___________________| | | | | | |
-- | | | ____________________________ _______ | S | | N | | |
-- | | | | | | clk | | | | | | |
-- | ACAM |<->| | TDC mezzanine |-| cross |<--> | | | 4 | | |
-- |________| | |--|____________________________| |_______| | D | | | | |
-- TDC mezz | | 125MHz 62.5MHz | | | 1 | | |
-- | | | | | | | | |
-- | DAC |<->| | | | G | | |
-- | PLL | | | | | | |
-- | | | ____________________________ | S | | N | | |
-- | | | | | | | | | | |
-- | ACAM |<->|------| TDC wrapper |<------------> | | | 4 | | |
-- |________| | |--|____________________________| | D | | | | |
-- TDC mezz | | 62.5MHz | | | 1 | | |
-- | | ____________________________ | | | | | |
-- | |->| | | B | | 2 | | |
-- | | Vector Interrupt Controller| <----------> | | <--> | | | |
......@@ -140,140 +137,149 @@ use UNISIM.vcomponents.all;
--=================================================================================================
entity wr_spec_tdc is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
values_for_simul : boolean := FALSE); -- this generic is set to TRUE
-- when instantiated in a test-bench
(g_with_wr_phy : boolean := true;
g_simulation : boolean := false); -- this generic is set to TRUE
-- when instantiated in a test-bench
port
(-- SPEC carrier
clk_125m_pllref_p_i: in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i: in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
dac_sclk_o : out std_logic; -- PLL VCXO DAC Drive
dac_din_o : out std_logic;
dac_cs1_n_o : out std_logic;
dac_cs2_n_o : out std_logic;
sfp_txp_o : out std_logic; -- SFP
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic := '0';
sfp_rxn_i : in std_logic := '1';
sfp_mod_def0_b : in std_logic; -- SFP detect pin
sfp_mod_def1_b : inout std_logic; -- SFP scl
sfp_mod_def2_b : inout std_logic; -- SFP sda
sfp_rate_select_b : inout std_logic := '0';
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
uart_rxd_i : in std_logic := '1'; -- UART
uart_txd_o : out std_logic;
carrier_scl_b : inout std_logic; -- SPEC EEPROM
carrier_sda_b : inout std_logic;
carrier_onewire_b : inout std_logic; -- SPEC 1-wire
button1_i : in std_logic := '1';
button2_i : in std_logic := '1';
-- Interface with GN4124
rst_n_a_i : in std_logic;
-- P2L Direction
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0);-- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
-- L2P Direction
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+ (freq set in GN4124 config registers)
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock- (freq set in GN4124 config registers)
l2p_data_o : out std_logic_vector(15 downto 0);-- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 8
irq_aux_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 9, aux signal
-- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
pll_sclk_o : out std_logic; -- SPI clock
pll_sdi_o : out std_logic; -- data line for PLL and DAC
pll_cs_o : out std_logic; -- PLL chip select
pll_dac_sync_o : out std_logic; -- DAC chip select
pll_sdo_i : in std_logic; -- not used for the moment
pll_status_i : in std_logic; -- PLL Digital Lock Detect, active high
tdc_clk_125m_p_i : in std_logic; -- 125 MHz differential clock: system clock
tdc_clk_125m_n_i : in std_logic; -- 125 MHz differential clock: system clock
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
acam_refclk_n_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
-- Timing interface with the ACAM on TDC mezzanine
start_from_fpga_o : out std_logic; -- start signal
err_flag_i : in std_logic; -- error flag
int_flag_i : in std_logic; -- interrupt flag
start_dis_o : out std_logic; -- start disable, not used
stop_dis_o : out std_logic; -- stop disable, not used
-- Data interface with the ACAM on TDC mezzanine
data_bus_io : inout std_logic_vector(27 downto 0);
address_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic; -- chip select for ACAM
oe_n_o : out std_logic; -- output enable for ACAM
rd_n_o : out std_logic; -- read signal for ACAM
wr_n_o : out std_logic; -- write signal for ACAM
ef1_i : in std_logic; -- empty flag iFIFO1
ef2_i : in std_logic; -- empty flag iFIFO2
-- Enable of input Logic on TDC mezzanine
enable_inputs_o : out std_logic; -- enables all 5 inputs
term_en_1_o : out std_logic; -- Ch.1 termination enable of 50 Ohm termination
term_en_2_o : out std_logic; -- Ch.2 termination enable of 50 Ohm termination
term_en_3_o : out std_logic; -- Ch.3 termination enable of 50 Ohm termination
term_en_4_o : out std_logic; -- Ch.4 termination enable of 50 Ohm termination
term_en_5_o : out std_logic; -- Ch.5 termination enable of 50 Ohm termination
-- LEDs on TDC mezzanine
tdc_led_status_o : out std_logic; -- amber led on front pannel, division of 125 MHz tdc_clk
tdc_led_trig1_o : out std_logic; -- amber led on front pannel, Ch.1 enable
tdc_led_trig2_o : out std_logic; -- amber led on front pannel, Ch.2 enable
tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 enable
tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 enable
tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 enable
-- Input Logic on TDC mezzanine (not used currently)
tdc_in_fpga_1_i : in std_logic; -- Ch.1 for ACAM, also received by FPGA
tdc_in_fpga_2_i : in std_logic; -- Ch.2 for ACAM, also received by FPGA
tdc_in_fpga_3_i : in std_logic; -- Ch.3 for ACAM, also received by FPGA
tdc_in_fpga_4_i : in std_logic; -- Ch.4 for ACAM, also received by FPGA
tdc_in_fpga_5_i : in std_logic; -- Ch.5 for ACAM, also received by FPGA
-- I2C EEPROM interface on TDC mezzanine
mezz_sys_scl_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C clock
mezz_sys_sda_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C data
-- 1-wire interface on TDC mezzanine
mezz_onewire_b : inout std_logic;
-- font panel leds
led_red : out std_logic;
led_green : out std_logic;
-- Carrier other signals
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic); -- Mezzanine presence (active low)
( -- SPEC carrier
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
dac_sclk_o : out std_logic; -- PLL VCXO DAC Drive
dac_din_o : out std_logic;
dac_cs1_n_o : out std_logic;
dac_cs2_n_o : out std_logic;
sfp_txp_o : out std_logic; -- SFP
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic := '0';
sfp_rxn_i : in std_logic := '1';
sfp_mod_def0_b : in std_logic; -- SFP detect pin
sfp_mod_def1_b : inout std_logic; -- SFP scl
sfp_mod_def2_b : inout std_logic; -- SFP sda
sfp_rate_select_b : inout std_logic := '0';
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
uart_rxd_i : in std_logic := '1'; -- UART
uart_txd_o : out std_logic;
carrier_scl_b : inout std_logic; -- SPEC EEPROM
carrier_sda_b : inout std_logic;
carrier_onewire_b : inout std_logic; -- SPEC 1-wire
button1_i : in std_logic := '1';
button2_i : in std_logic := '1';
------------------------------------------------------------------------
-- GN4124 PCI bridge pins
------------------------------------------------------------------------
l_rst_n : in std_logic; -- reset from gn4124 (rstout18_n)
-- general purpose interface
gpio : inout std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
-- gpio[1] -> gn4124 gpio9
-- pcie to local [inbound data] - rx
p2l_rdy : out std_logic; -- rx buffer full flag
p2l_clkn : in std_logic; -- receiver source synchronous clock-
p2l_clkp : in std_logic; -- receiver source synchronous clock+
p2l_data : in std_logic_vector(15 downto 0); -- parallel receive data
p2l_dframe : in std_logic; -- receive frame
p2l_valid : in std_logic; -- receive data valid
-- inbound buffer request/status
p_wr_req : in std_logic_vector(1 downto 0); -- pcie write request
p_wr_rdy : out std_logic_vector(1 downto 0); -- pcie write ready
rx_error : out std_logic; -- receive error
-- local to parallel [outbound data] - tx
l2p_data : out std_logic_vector(15 downto 0); -- parallel transmit data
l2p_dframe : out std_logic; -- transmit data frame
l2p_valid : out std_logic; -- transmit data valid
l2p_clkn : out std_logic; -- transmitter source synchronous clock-
l2p_clkp : out std_logic; -- transmitter source synchronous clock+
l2p_edb : out std_logic; -- packet termination and discard
-- outbound buffer status
l2p_rdy : in std_logic; -- tx buffer full flag
l_wr_rdy : in std_logic_vector(1 downto 0); -- local-to-pcie write
p_rd_d_rdy : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
tx_error : in std_logic; -- transmit error
vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
-- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
pll_sclk_o : out std_logic; -- SPI clock
pll_sdi_o : out std_logic; -- data line for PLL and DAC
pll_cs_o : out std_logic; -- PLL chip select
pll_dac_sync_o : out std_logic; -- DAC chip select
pll_sdo_i : in std_logic; -- not used for the moment
pll_status_i : in std_logic; -- PLL Digital Lock Detect, active high
tdc_clk_125m_p_i : in std_logic; -- 125 MHz differential clock: system clock
tdc_clk_125m_n_i : in std_logic; -- 125 MHz differential clock: system clock
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
acam_refclk_n_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
-- Timing interface with the ACAM on TDC mezzanine
start_from_fpga_o : out std_logic; -- start signal
err_flag_i : in std_logic; -- error flag
int_flag_i : in std_logic; -- interrupt flag
start_dis_o : out std_logic; -- start disable, not used
stop_dis_o : out std_logic; -- stop disable, not used
-- Data interface with the ACAM on TDC mezzanine
data_bus_io : inout std_logic_vector(27 downto 0);
address_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic; -- chip select for ACAM
oe_n_o : out std_logic; -- output enable for ACAM
rd_n_o : out std_logic; -- read signal for ACAM
wr_n_o : out std_logic; -- write signal for ACAM
ef1_i : in std_logic; -- empty flag iFIFO1
ef2_i : in std_logic; -- empty flag iFIFO2
-- Enable of input Logic on TDC mezzanine
enable_inputs_o : out std_logic; -- enables all 5 inputs
term_en_1_o : out std_logic; -- Ch.1 termination enable of 50 Ohm termination
term_en_2_o : out std_logic; -- Ch.2 termination enable of 50 Ohm termination
term_en_3_o : out std_logic; -- Ch.3 termination enable of 50 Ohm termination
term_en_4_o : out std_logic; -- Ch.4 termination enable of 50 Ohm termination
term_en_5_o : out std_logic; -- Ch.5 termination enable of 50 Ohm termination
-- LEDs on TDC mezzanine
tdc_led_status_o : out std_logic; -- amber led on front pannel, division of 125 MHz tdc_clk
tdc_led_trig1_o : out std_logic; -- amber led on front pannel, Ch.1 enable
tdc_led_trig2_o : out std_logic; -- amber led on front pannel, Ch.2 enable
tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 enable
tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 enable
tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 enable
-- Input Logic on TDC mezzanine (not used currently)
tdc_in_fpga_1_i : in std_logic; -- Ch.1 for ACAM, also received by FPGA
tdc_in_fpga_2_i : in std_logic; -- Ch.2 for ACAM, also received by FPGA
tdc_in_fpga_3_i : in std_logic; -- Ch.3 for ACAM, also received by FPGA
tdc_in_fpga_4_i : in std_logic; -- Ch.4 for ACAM, also received by FPGA
tdc_in_fpga_5_i : in std_logic; -- Ch.5 for ACAM, also received by FPGA
-- I2C EEPROM interface on TDC mezzanine
mezz_sys_scl_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C clock
mezz_sys_sda_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C data
-- 1-wire interface on TDC mezzanine
mezz_onewire_b : inout std_logic;
-- font panel leds
led_red : out std_logic;
led_green : out std_logic;
-- Carrier other signals
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic); -- Mezzanine presence (active low)
end wr_spec_tdc;
......@@ -282,132 +288,130 @@ end wr_spec_tdc;
--=================================================================================================
architecture rtl of wr_spec_tdc is
function f_bool2int (x : boolean) return integer is
begin
if(x) then
return 1;
else
return 0;
end if;
end f_bool2int;
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
constant c_SPEC_INFO_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000603", -- "WB-SPEC.CSR " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-SPEC.CSR ")));
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 4;
constant c_WB_SLAVE_SPEC_INFO : integer := 0; -- Info on SPEC control and status registers
constant c_WB_SLAVE_VIC : integer := 1; -- Interrupt controller
constant c_WB_SLAVE_TDC : integer := 2; -- TDC core configuration
constant c_SLAVE_WRCORE : integer := 3; -- White Rabbit PTP core
constant c_NUM_WB_MASTERS : integer := 4;
constant c_WB_SLAVE_SPEC_INFO : integer := 0; -- Info on SPEC control and status registers
constant c_WB_SLAVE_VIC : integer := 1; -- Interrupt controller
constant c_WB_SLAVE_TDC : integer := 2; -- TDC core configuration
constant c_SLAVE_WRCORE : integer := 3; -- White Rabbit PTP core
-- SDB header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Slave port on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
constant c_MASTER_GENNUM : integer := 0;
constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_NUM_WB_SLAVES : integer := 1;
constant c_MASTER_GENNUM : integer := 0;
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
(0 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg
2 => f_sdb_embed_bridge (c_FMC_TDC_SDB_BRIDGE, x"00040000"),
3 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
4 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
5 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000FFFF", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
(0 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg
2 => f_sdb_embed_bridge (c_FMC_TDC_SDB_BRIDGE, x"00040000"),
3 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
4 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
5 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
---------------------------------------------------------------------------------------------------
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) :=
(0 => x"00052000");
(0 => x"00043000");
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- WRabbit clocks
signal pllout_clk_sys, pllout_clk_dmtd : std_logic;
signal pllout_clk_fb_pllref, pllout_clk_fb_dmtd : std_logic;
signal clk_125m_pllref, clk_125m_gtp : std_logic;
signal clk_dmtd : std_logic;
attribute buffer_type : string; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
attribute buffer_type of clk_125m_pllref : signal is "BUFG";
signal pllout_clk_sys, pllout_clk_dmtd : std_logic;
signal pllout_clk_fb_pllref, pllout_clk_fb_dmtd : std_logic;
signal clk_125m_pllref, clk_125m_gtp : std_logic;
signal clk_dmtd : std_logic;
attribute buffer_type : string; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
attribute buffer_type of clk_125m_pllref : signal is "BUFG";
-- TDC core clocks and resets
signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic;
signal clk_62m5_sys, sys_locked : std_logic;
signal clk_125m_mezz, pll_mezz_status : std_logic;
signal rst_125m_mezz_n, rst_125m_mezz : std_logic;
signal acam_refclk_r_edge_p : std_logic;
signal rst_sys, rst_sys_n : std_logic;
signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic;
signal clk_62m5_sys, sys_locked : std_logic;
signal rst_n_sys : std_logic;
-- DAC configuration through PCIe/VME
signal send_dac_word_p : std_logic;
signal dac_word : std_logic_vector(23 downto 0);
-- WISHBONE from crossbar master port
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- WISHBONE to crossbar slave port
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal tdc_slave_in : t_wishbone_slave_in;
signal tdc_slave_out : t_wishbone_slave_out;
signal gn_wb_adr : std_logic_vector(31 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal gn_wb_adr : std_logic_vector(31 downto 0);
-- Carrier CSR info
signal gn4124_status : std_logic_vector(31 downto 0);
signal gn4124_status : std_logic_vector(31 downto 0);
-- Carrier 1-wire
signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
-- VIC
signal fmc_eic_irq, irq_to_gn4124 : std_logic;
signal fmc_eic_irq_synch : std_logic_vector (1 downto 0);
signal irq_to_gn4124 : std_logic;
-- WRabbit time
signal tm_link_up, tm_time_valid, tm_dac_wr_p : std_logic;
signal tm_utc : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_dac_value, tm_dac_value_reg : std_logic_vector(23 downto 0);
signal tm_clk_aux_lock_en, tm_clk_aux_locked : std_logic;
signal tm_link_up, tm_time_valid, tm_dac_wr_p : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_dac_value, tm_dac_value_reg : std_logic_vector(23 downto 0);
signal tm_clk_aux_lock_en, tm_clk_aux_locked : std_logic;
-- WRabbit PHY
signal phy_tx_data, phy_rx_data : std_logic_vector(7 downto 0);
signal phy_tx_k, phy_tx_disparity, phy_rx_k : std_logic;
signal phy_tx_enc_err, phy_rx_rbclk : std_logic;
signal phy_rx_enc_err, phy_rst, phy_loopen : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_tx_data, phy_rx_data : std_logic_vector(7 downto 0);
signal phy_tx_k, phy_tx_disparity, phy_rx_k : std_logic;
signal phy_tx_enc_err, phy_rx_rbclk : std_logic;
signal phy_rx_enc_err, phy_rst, phy_loopen : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
-- DAC configuration through WRabbit
signal dac_hpll_load_p1, dac_dpll_load_p1 : std_logic;
signal dac_hpll_data, dac_dpll_data : std_logic_vector(15 downto 0);
signal dac_hpll_load_p1, dac_dpll_load_p1 : std_logic;
signal dac_hpll_data, dac_dpll_data : std_logic_vector(15 downto 0);
-- EEPROM on mezzanine
signal wrc_scl_out, wrc_scl_in, wrc_sda_out, wrc_sda_in: std_logic;
signal tdc_scl_out, tdc_scl_in, tdc_sda_out, tdc_sda_in: std_logic;
signal tdc_scl_oen, tdc_sda_oen : std_logic;
signal wrc_scl_out, wrc_scl_in, wrc_sda_out, wrc_sda_in : std_logic;
signal tdc_scl_out, tdc_scl_in, tdc_sda_out, tdc_sda_in : std_logic;
signal tdc_scl_oen, tdc_sda_oen : std_logic;
-- SFP EEPROM on mezzanine
signal sfp_scl_out, sfp_scl_in, sfp_sda_out, sfp_sda_in: std_logic;
signal sfp_scl_out, sfp_scl_in, sfp_sda_out, sfp_sda_in : std_logic;
-- Carrier 1-Wire
signal wrc_owr_en, wrc_owr_in : std_logic_vector(1 downto 0);
signal wrc_owr_en, wrc_owr_in : std_logic_vector(1 downto 0);
-- aux
signal pll_sclk, pll_sdi, pll_dac_sync, pll_cs : std_logic;
---------------------------------------------------------------------------------------------------
-- Chipscope --
---------------------------------------------------------------------------------------------------
-- -- Chipscope
-- component chipscope_ila
-- port (
-- CONTROL : inout std_logic_vector(35 downto 0);
-- CLK : in std_logic;
-- TRIG0 : in std_logic_vector(31 downto 0);
-- TRIG1 : in std_logic_vector(31 downto 0);
-- TRIG2 : in std_logic_vector(31 downto 0);
-- TRIG3 : in std_logic_vector(31 downto 0));
-- end component;
-- component chipscope_icon
-- port (
-- CONTROL0 : inout std_logic_vector (35 downto 0));
-- end component;
-- signal CONTROL : std_logic_vector(35 downto 0);
-- signal CLK : std_logic;
-- signal TRIG0 : std_logic_vector(31 downto 0);
-- signal TRIG1 : std_logic_vector(31 downto 0);
-- signal TRIG2 : std_logic_vector(31 downto 0);
-- signal TRIG3 : std_logic_vector(31 downto 0);
signal tdc0_irq: std_logic;
signal tdc0_clk_125m : std_logic;
signal tdc0_soft_rst_n: std_logic;
signal powerup_rst_cnt : unsigned(7 downto 0) := "00000000";
signal carrier_info_fmc_rst : std_logic_vector(30 downto 0);
--=================================================================================================
-- architecture begin
......@@ -418,30 +422,28 @@ begin
-- 62.5 MHz system clock --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_vcxo_ibuf : IBUFG
port map
port map
(O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
cmp_clk_vcxo_gbuf : BUFG
port map
port map
(O => clk_20m_vcxo,
I => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sys_clk_pll : PLL_BASE
generic map
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- not used
CLKOUT1_DIVIDE => 16, -- not used
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
......@@ -449,117 +451,42 @@ begin
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map
(CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_20m_vcxo);
port map
(CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_20m_vcxo);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_sys_buf : BUFG
port map
port map
(O => clk_62m5_sys,
I => pllout_clk_sys);
---------------------------------------------------------------------------------------------------
-- Reset for 62.5 MHz clk domain --
---------------------------------------------------------------------------------------------------
U_Reset_Generator : spec_reset_gen
port map
(clk_sys_i => clk_62m5_sys,
rst_pcie_n_a_i => rst_n_a_i,
rst_button_n_a_i => button1_i,
rst_n_o => rst_sys_n);
-- -- -- -- -- -- -- -- -- --
rst_sys <= not rst_sys_n;
I => pllout_clk_sys);
---------------------------------------------------------------------------------------------------
-- 125 MHz clk and Reset for TDC core --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_tdc_clks_rsts_mgment : clks_rsts_manager
generic map
(nb_of_reg => 68)
port map
(clk_sys_i => clk_62m5_sys,
acam_refclk_p_i => acam_refclk_p_i,
acam_refclk_n_i => acam_refclk_n_i,
tdc_125m_clk_p_i => tdc_clk_125m_p_i,
tdc_125m_clk_n_i => tdc_clk_125m_n_i,
rst_n_i => rst_n_a_i,
pll_sdo_i => pll_sdo_i,
pll_status_i => pll_status_i,
send_dac_word_p_i => send_dac_word_p,
dac_word_i => dac_word,
acam_refclk_r_edge_p_o => acam_refclk_r_edge_p,
wrabbit_dac_value_i => tm_dac_value,
wrabbit_dac_wr_p_i => tm_dac_wr_p,
internal_rst_o => rst_125m_mezz,
pll_cs_n_o => pll_cs,
pll_dac_sync_n_o => pll_dac_sync,
pll_sdi_o => pll_sdi,
pll_sclk_o => pll_sclk,
tdc_125m_clk_o => clk_125m_mezz,
pll_status_o => pll_mezz_status);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_125m_mezz_n <= not rst_125m_mezz;
pll_dac_sync_o <= pll_dac_sync;
pll_sdi_o <= pll_sdi;
pll_sclk_o <= pll_sclk;
pll_cs_o <= pll_cs;
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_62m5_sys,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
-- chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
-- TRIG0(23 downto 0) <= tm_dac_value;
-- TRIG0(24) <= tm_dac_wr_p;
-- TRIG0(25) <= pll_dac_sync;
-- TRIG0(26) <= pll_sdi;
-- TRIG0(27) <= pll_sclk;
-- TRIG0(28) <= pll_sdo_i;
-- TRIG0(29) <= pll_status_i;
-- TRIG0(30) <= pll_cs;
-- TRIG0(31) <= tm_clk_aux_lock_en;
---------------------------------------------------------------------------------------------------
-- 62.5 MHz DMTD clock --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_dmtd_clk_pll : PLL_BASE
generic map
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- not used
CLKOUT1_DIVIDE => 16, -- not used
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
......@@ -567,50 +494,78 @@ begin
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map
(CLKFBOUT => pllout_clk_fb_dmtd,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_buf);
port map
(CLKFBOUT => pllout_clk_fb_dmtd,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_dmtd_buf : BUFG
port map
port map
(O => clk_dmtd,
I => pllout_clk_dmtd);
---------------------------------------------------------------------------------------------------
-- 125 MHz clk for White Rabbit core --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_Buf_CLK_PLL : IBUFGDS
generic map
generic map
(DIFF_TERM => true,
IBUF_LOW_PWR => true) -- Low power (TRUE) vs. performance (FALSE) setting for referenced
port map
(O => clk_125m_pllref, -- Buffer output
IBUF_LOW_PWR => true) -- Low power (TRUE) vs. performance (FALSE) setting for referenced
port map
(O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i); -- Diff_n buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i); -- Diff_n buffer input (connect directly to top-level port)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_Buf_CLK_GTP : IBUFDS
generic map
(DIFF_TERM => true,
generic map
(DIFF_TERM => true,
IBUF_LOW_PWR => false)
port map
port map
(O => clk_125m_gtp,
I => clk_125m_gtp_p_i,
IB => clk_125m_gtp_n_i);
---------------------------------------------------------------------------------------------------
-- 62.5 MHz Reset --
---------------------------------------------------------------------------------------------------
-- SPEC power-up reset in the clk_62m5_sys domain: rst_n_sys is asserted asynchronously upon VME
-- reset or SVEC AFPGA power-on reset. If none of these signals is asserted at startup, the process
-- waits for the system clock PLL to lock + additional 256 clk_62m5_sys cycles before de-asserting
-- the reset.
p_powerup_reset : process(clk_62m5_sys,l_rst_n)
begin
if(l_rst_n = '0') then
rst_n_sys <= '0';
elsif rising_edge(clk_62m5_sys) then
if sys_locked = '1' then
if(powerup_rst_cnt = "11111111") then
rst_n_sys <= '1';
else
rst_n_sys <= '0';
powerup_rst_cnt <= powerup_rst_cnt + 1;
end if;
else
rst_n_sys <= '0';
powerup_rst_cnt <= "00000000";
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tdc0_soft_rst_n <= carrier_info_fmc_rst(0) and rst_n_sys;
---------------------------------------------------------------------------------------------------
-- White Rabbit Core + PHY --
......@@ -618,86 +573,87 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_WR_CORE : xwr_core
generic map
(g_simulation => 0,
generic map
(g_simulation => f_bool2int(g_simulation),
g_phys_uart => true,
g_virtual_uart => true,
g_with_external_clock_input => false,
g_aux_clks => 1,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "wrc.ram",
g_dpram_initf => "none",
g_dpram_size => 90112/4,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_softpll_enable_debugger => false)
port map
(clk_sys_i => clk_62m5_sys,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
clk_aux_i(0) => clk_125m_mezz,
rst_n_i => rst_sys_n,
port map
(clk_sys_i => clk_62m5_sys,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
clk_aux_i(0) => tdc0_clk_125m,
rst_n_i => rst_n_sys,
-- DAC
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
-- PHY
phy_ref_clk_i => clk_125m_pllref,
phy_tx_data_o => phy_tx_data,
phy_tx_k_o => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_enc_err,
phy_rx_data_i => phy_rx_data,
phy_rx_rbclk_i => phy_rx_rbclk,
phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_enc_err,
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
phy_ref_clk_i => clk_125m_pllref,
phy_tx_data_o => phy_tx_data,
phy_tx_k_o => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_enc_err,
phy_rx_data_i => phy_rx_data,
phy_rx_rbclk_i => phy_rx_rbclk,
phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_enc_err,
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
-- SPEC LEDs
led_act_o => LED_RED,
led_link_o => LED_GREEN,
led_act_o => LED_RED,
led_link_o => LED_GREEN,
-- SFP
scl_o => wrc_scl_out,
scl_i => wrc_scl_in,
sda_o => wrc_sda_out,
sda_i => wrc_sda_in,
sfp_scl_o => sfp_scl_out,
sfp_scl_i => sfp_scl_in,
sfp_sda_o => sfp_sda_out,
sfp_sda_i => sfp_sda_in,
sfp_det_i => sfp_mod_def0_b,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
scl_o => wrc_scl_out,
scl_i => wrc_scl_in,
sda_o => wrc_sda_out,
sda_i => wrc_sda_in,
sfp_scl_o => sfp_scl_out,
sfp_scl_i => sfp_scl_in,
sfp_sda_o => sfp_sda_out,
sfp_sda_i => sfp_sda_in,
sfp_det_i => sfp_mod_def0_b,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- 1-wire
owr_en_o => wrc_owr_en,
owr_i => wrc_owr_in,
owr_en_o => wrc_owr_en,
owr_i => wrc_owr_in,
-- WISHBONE
slave_i => cnx_master_out(c_SLAVE_WRCORE),
slave_o => cnx_master_in(c_SLAVE_WRCORE),
slave_i => cnx_master_out(c_SLAVE_WRCORE),
slave_o => cnx_master_in(c_SLAVE_WRCORE),
-- Timimg info for TDC core
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o(0) => tm_dac_wr_p,
tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
tm_clk_aux_locked_o(0) => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_utc,
tm_cycles_o => tm_cycles,
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o(0) => tm_dac_wr_p,
tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
tm_clk_aux_locked_o(0) => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
-- not used
btn1_i => '1',
btn2_i => '1',
pps_p_o => open,
btn1_i => '1',
btn2_i => '1',
pps_p_o => open,
-- aux reset
rst_aux_n_o => open);
rst_aux_n_o => open);
gen_with_wr_phy: if g_with_wr_phy generate
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_GTP : wr_gtp_phy_spartan6
generic map
(g_simulation => 0,
g_enable_ch0 => 0,
g_enable_ch1 => 1)
port map
generic map
(g_simulation => 0,
g_enable_ch0 => 0,
g_enable_ch1 => 1)
port map
(gtp_clk_i => clk_125m_gtp,
ch0_ref_clk_i => clk_125m_pllref,
ch0_tx_data_i => x"00",
......@@ -722,7 +678,7 @@ begin
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
ch1_loopen_i => '0', -- phy_loopen,
ch1_loopen_i => '0', -- phy_loopen,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
......@@ -732,47 +688,26 @@ begin
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
end generate gen_with_wr_phy;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_DAC_ARB : spec_serial_dac_arb
generic map
generic map
(g_invert_sclk => false,
g_num_extra_bits => 8)
port map
(clk_i => clk_62m5_sys,
rst_n_i => rst_sys_n,
val1_i => dac_dpll_data,
load1_i => dac_dpll_load_p1,
val2_i => dac_hpll_data,
load2_i => dac_hpll_load_p1,
dac_cs_n_o(0) => dac_cs1_n_o,
dac_cs_n_o(1) => dac_cs2_n_o,
port map
(clk_i => clk_62m5_sys,
rst_n_i => rst_n_sys,
val1_i => dac_dpll_data,
load1_i => dac_dpll_load_p1,
val2_i => dac_hpll_data,
load2_i => dac_hpll_load_p1,
dac_cs_n_o(0) => dac_cs1_n_o,
dac_cs_n_o(1) => dac_cs2_n_o,
-- dac_clr_n_o => open,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o);
-- -- -- -- -- --
sfp_tx_disable_o <= '0';
-- dac_clr_n_o <= '1';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for TDC mezzanine EEPROM
mezz_sys_scl_b <= tdc_scl_out when (tdc_scl_oen = '0') else '0' when (wrc_scl_out = '0') else 'Z';
mezz_sys_sda_b <= tdc_sda_out when (tdc_sda_oen = '0') else '0' when (wrc_sda_out = '0') else 'Z';
wrc_scl_in <= mezz_sys_scl_b;
wrc_sda_in <= mezz_sys_sda_b;
tdc_scl_in <= mezz_sys_scl_b;
tdc_sda_in <= mezz_sys_sda_b;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
carrier_onewire_b <= '0' when wrc_owr_en(0) = '1' else 'Z';
wrc_owr_in(0) <= carrier_onewire_b;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o);
---------------------------------------------------------------------------------------------------
......@@ -789,58 +724,66 @@ begin
-- 0x13000 -> TDC Mezzanine I2C master
-- 0x14000 -> TDC core timestamps retrieval from memory
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map
generic map
(g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map
(clk_sys_i => clk_62m5_sys,
rst_n_i => rst_sys_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
port map
(clk_sys_i => clk_62m5_sys,
rst_n_i => rst_n_sys,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
---------------------------------------------------------------------------------------------------
-- GN4124 CORE --
---------------------------------------------------------------------------------------------------
cmp_gn4124_core: gn4124_core
port map
(rst_n_a_i => rst_n_a_i,
cmp_gn4124_core : gn4124_core
port map
(rst_n_a_i => l_rst_n,
status_o => gn4124_status,
-- P2L Direction Source Sync DDR related signals
p2l_clk_p_i => p2l_clk_p_i,
p2l_clk_n_i => p2l_clk_n_i,
p2l_data_i => p2l_data_i,
p2l_dframe_i => p2l_dframe_i,
p2l_valid_i => p2l_valid_i,
-- P2L Control
p2l_rdy_o => p2l_rdy_o,
p_wr_req_i => p_wr_req_i,
p_wr_rdy_o => p_wr_rdy_o,
rx_error_o => rx_error_o,
-- L2P Direction Source Sync DDR related signals
l2p_clk_p_o => l2p_clk_p_o,
l2p_clk_n_o => l2p_clk_n_o,
l2p_data_o => l2p_data_o ,
l2p_dframe_o => l2p_dframe_o,
l2p_valid_o => l2p_valid_o,
l2p_edb_o => l2p_edb_o,
-- L2P Control
l2p_rdy_i => l2p_rdy_i,
l_wr_rdy_i => l_wr_rdy_i,
p_rd_d_rdy_i => p_rd_d_rdy_i,
tx_error_i => tx_error_i,
vc_rdy_i => vc_rdy_i,
-- Interrupt interface
dma_irq_o => open,
irq_p_i => irq_to_gn4124,
irq_p_o => irq_p_o,
-- CSR WISHBONE interface (master pipelined)
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
-- L2P Control
l2p_edb_o => L2P_EDB,
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
dma_irq_o => open,
irq_p_i => '0',
irq_p_o => open,
-- CSR WISHBONE interface (master pipelined)
csr_clk_i => clk_62m5_sys,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
......@@ -851,7 +794,10 @@ begin
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
-- DMA: not used
csr_err_i => '0',
csr_rty_i => '0',
csr_int_i => '0',
-- DMA: not used
dma_clk_i => clk_62m5_sys,
dma_adr_o => open,
dma_cyc_o => open,
......@@ -862,6 +808,9 @@ begin
dma_ack_i => '1',
dma_dat_i => (others => '0'),
dma_stall_i => '0',
dma_err_i => '0',
dma_rty_i => '0',
dma_int_i => '0',
dma_reg_clk_i => clk_62m5_sys,
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
......@@ -877,171 +826,102 @@ begin
-- Convert 32-bit word address into byte address for crossbar
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
cmp_tdc_mezzanine : fmc_tdc_wrapper
generic map (
g_simulation => g_simulation,
g_with_direct_readout => false)
port map (
clk_sys_i => clk_62m5_sys,
rst_sys_n_i => rst_n_sys,
rst_n_a_i => tdc0_soft_rst_n,
pll_sclk_o => pll_sclk_o,
pll_sdi_o => pll_sdi_o,
pll_cs_o => pll_cs_o,
pll_dac_sync_o => pll_dac_sync_o,
pll_sdo_i => pll_sdo_i,
pll_status_i => pll_status_i,
tdc_clk_125m_p_i => tdc_clk_125m_p_i,
tdc_clk_125m_n_i => tdc_clk_125m_n_i,
acam_refclk_p_i => acam_refclk_p_i,
acam_refclk_n_i => acam_refclk_n_i,
start_from_fpga_o => start_from_fpga_o,
err_flag_i => err_flag_i,
int_flag_i => int_flag_i,
start_dis_o => start_dis_o,
stop_dis_o => stop_dis_o,
data_bus_io => data_bus_io,
address_o => address_o,
cs_n_o => cs_n_o,
oe_n_o => oe_n_o,
rd_n_o => rd_n_o,
wr_n_o => wr_n_o,
ef1_i => ef1_i,
ef2_i => ef2_i,
enable_inputs_o => enable_inputs_o,
term_en_1_o => term_en_1_o,
term_en_2_o => term_en_2_o,
term_en_3_o => term_en_3_o,
term_en_4_o => term_en_4_o,
term_en_5_o => term_en_5_o,
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
tdc_in_fpga_1_i => tdc_in_fpga_1_i,
tdc_in_fpga_2_i => tdc_in_fpga_2_i,
tdc_in_fpga_3_i => tdc_in_fpga_3_i,
tdc_in_fpga_4_i => tdc_in_fpga_4_i,
tdc_in_fpga_5_i => tdc_in_fpga_5_i,
mezz_scl_o => tdc_scl_oen,
mezz_sda_o => tdc_sda_oen,
mezz_scl_i => tdc_scl_in,
mezz_sda_i => tdc_sda_in,
mezz_one_wire_b => mezz_onewire_b,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_tai_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en,
tm_clk_aux_locked_i => tm_clk_aux_locked,
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr_p,
slave_i => cnx_master_out(c_WB_SLAVE_TDC),
slave_o => cnx_master_in(c_WB_SLAVE_TDC),
irq_o => tdc0_irq,
clk_125m_tdc_o => tdc0_clk_125m);
---------------------------------------------------------------------------------------------------
-- TDC BOARD --
---------------------------------------------------------------------------------------------------
cmp_tdc_mezz : fmc_tdc_mezzanine
generic map
(g_with_wrabbit_core => TRUE,
g_span => g_span,
g_width => g_width,
values_for_simul => FALSE)
port map
-- 62M5 clk and reset
(clk_sys_i => clk_62m5_sys,
rst_sys_n_i => rst_sys_n,
-- 125M clk and reset
clk_ref_0_i => clk_125m_mezz,
rst_ref_0_i => rst_125m_mezz,
-- Configuration of the DAC on the TDC mezzanine, non White Rabbit
acam_refclk_r_edge_p_i => acam_refclk_r_edge_p,
send_dac_word_p_o => send_dac_word_p,
dac_word_o => dac_word,
-- ACAM interface
start_from_fpga_o => start_from_fpga_o,
err_flag_i => err_flag_i,
int_flag_i => int_flag_i,
start_dis_o => start_dis_o,
stop_dis_o => stop_dis_o,
data_bus_io => data_bus_io,
address_o => address_o,
cs_n_o => cs_n_o,
oe_n_o => oe_n_o,
rd_n_o => rd_n_o,
wr_n_o => wr_n_o,
ef1_i => ef1_i,
ef2_i => ef2_i,
-- Input channels enable
enable_inputs_o => enable_inputs_o,
term_en_1_o => term_en_1_o,
term_en_2_o => term_en_2_o,
term_en_3_o => term_en_3_o,
term_en_4_o => term_en_4_o,
term_en_5_o => term_en_5_o,
-- LEDs on TDC mezzanine
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
-- Input channels to FPGA (not used)
tdc_in_fpga_1_i => tdc_in_fpga_1_i,
tdc_in_fpga_2_i => tdc_in_fpga_2_i,
tdc_in_fpga_3_i => tdc_in_fpga_3_i,
tdc_in_fpga_4_i => tdc_in_fpga_4_i,
tdc_in_fpga_5_i => tdc_in_fpga_5_i,
-- WISHBONE interface with the GN4124 core
wb_tdc_csr_adr_i => tdc_slave_in.adr,
wb_tdc_csr_dat_i => tdc_slave_in.dat,
wb_tdc_csr_stb_i => tdc_slave_in.stb,
wb_tdc_csr_we_i => tdc_slave_in.we,
wb_tdc_csr_cyc_i => tdc_slave_in.cyc,
wb_tdc_csr_sel_i => tdc_slave_in.sel,
wb_tdc_csr_dat_o => tdc_slave_out.dat,
wb_tdc_csr_ack_o => tdc_slave_out.ack,
wb_tdc_csr_stall_o => tdc_slave_out.stall,
-- White Rabbit
wrabbit_link_up_i => tm_link_up,
wrabbit_time_valid_i => tm_time_valid,
wrabbit_cycles_i => tm_cycles,
wrabbit_utc_i => tm_utc(31 downto 0),
wrabbit_clk_aux_lock_en_o => tm_clk_aux_lock_en,
wrabbit_clk_aux_locked_i => tm_clk_aux_locked,
wrabbit_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the WRCore
wrabbit_dac_value_i => tm_dac_value_reg,
wrabbit_dac_wr_p_i => tm_dac_wr_p,
-- Interrupt line from EIC
wb_irq_o => fmc_eic_irq,
-- EEPROM I2C on TDC mezzanine
i2c_scl_oen_o => tdc_scl_oen,
i2c_scl_i => tdc_scl_in,
i2c_sda_oen_o => tdc_sda_oen,
i2c_sda_i => tdc_sda_in,
i2c_scl_o => tdc_scl_out,
i2c_sda_o => tdc_sda_out,
-- 1-Wire on TDC mezzanine
onewire_b => mezz_onewire_b);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Domains crossing: clk_125m_mezz <-> clk_62m5_sys
cmp_tdc_clk_crossing : xwb_clock_crossing
port map
(slave_clk_i => clk_62m5_sys, -- Slave control port: GNUM interface at 62.5 MHz
slave_rst_n_i => rst_sys_n,
slave_i => cnx_master_out(c_WB_SLAVE_TDC),
slave_o => cnx_master_in(c_WB_SLAVE_TDC),
master_clk_i => clk_125m_mezz, -- Master reader port: TDC core at 125 MHz
master_rst_n_i => rst_125m_mezz_n,
master_i => tdc_slave_out,
master_o => tdc_slave_in);
---------------------------------------------------------------------------------------------------
-- VIC --
---------------------------------------------------------------------------------------------------
cmp_vic : xwb_vic
generic map
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 1,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map
port map
(clk_sys_i => clk_62m5_sys,
rst_n_i => rst_sys_n,
rst_n_i => rst_n_sys,
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_eic_irq_synch(1),
irqs_i(0) => tdc0_irq,
irq_master_o => irq_to_gn4124);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Domains crossing: synchronization of the wb_ird_o from 125MHz to 62.5MHz
irq_pulse_synchronizer: process (clk_62m5_sys)
begin
if rising_edge (clk_62m5_sys) then
if rst_sys_n = '0' then
fmc_eic_irq_synch <= (others => '0');
else
fmc_eic_irq_synch <= fmc_eic_irq_synch(0) & fmc_eic_irq;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Carrier 1-wire MASTER DS18B20 (thermometer + unique ID) --
---------------------------------------------------------------------------------------------------
-- cmp_carrier_onewire : xwb_onewire_master
-- generic map
-- (g_interface_mode => CLASSIC,
-- g_address_granularity => BYTE,
-- g_num_ports => 1,
-- g_ow_btp_normal => "5.0",
-- g_ow_btp_overdrive => "1.0")
-- port map
-- (clk_sys_i => clk_62m5_sys,
-- rst_n_i => rst_sys_n,
-- slave_i => cnx_master_out(c_WB_SLAVE_SPEC_ONEWIRE),
-- slave_o => cnx_master_in(c_WB_SLAVE_SPEC_ONEWIRE),
-- desc_o => open,
-- owr_pwren_o => open,
-- owr_en_o => carrier_owr_en,
-- owr_i => carrier_owr_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- carrier_onewire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
-- carrier_owr_i(0) <= carrier_onewire_b;
gpio(0) <= irq_to_gn4124;
gpio(1) <= '0';
---------------------------------------------------------------------------------------------------
-- Carrier CSR information --
---------------------------------------------------------------------------------------------------
-- Information on carrier type, mezzanine presence, pcb version
cmp_carrier_info : carrier_info
port map
(rst_n_i => rst_sys_n,
port map
(rst_n_i => rst_n_sys,
clk_sys_i => clk_62m5_sys,
wb_adr_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).dat,
......@@ -1057,9 +937,10 @@ begin
carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_info_stat_p2l_pll_lck_i => gn4124_status(0),
carrier_info_stat_sys_pll_lck_i => pll_mezz_status,
carrier_info_stat_sys_pll_lck_i => sys_locked,
carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_reserved_i => x"000000" & "000" & sys_locked,
carrier_info_stat_reserved_i => x"0000000",
carrier_info_ctrl_led_green_o => open,
carrier_info_ctrl_led_red_o => open,
carrier_info_ctrl_dac_clr_n_o => open,
......@@ -1067,16 +948,42 @@ begin
carrier_info_rst_fmc0_n_o => open,
carrier_info_rst_fmc0_n_i => '1',
carrier_info_rst_fmc0_n_load_o => open,
carrier_info_rst_reserved_o => open);
carrier_info_rst_reserved_o => carrier_info_fmc_rst);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).rty <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).int <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).rty <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).int <= '0';
-- -- -- -- -- --
sfp_tx_disable_o <= '0';
-- dac_clr_n_o <= '1';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for TDC mezzanine EEPROM
mezz_sys_scl_b <= '0' when (tdc_scl_oen = '0') else '0' when (wrc_scl_out = '0') else 'Z';
mezz_sys_sda_b <= '0' when (tdc_sda_oen = '0') else '0' when (wrc_sda_out = '0') else 'Z';
wrc_scl_in <= mezz_sys_scl_b;
wrc_sda_in <= mezz_sys_sda_b;
tdc_scl_in <= mezz_sys_scl_b;
tdc_sda_in <= mezz_sys_sda_b;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
carrier_onewire_b <= '0' when wrc_owr_en(0) = '1' else 'Z';
wrc_owr_in(0) <= carrier_onewire_b;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
\ No newline at end of file
----------------------------------------------------------------------------------------------------
hdl/top/svec/wr_svec_tdc.vhd
View file @ 5765c94d
......@@ -25,18 +25,14 @@
-- All these cores communicate with the VME core through the WISHBONE. |
-- The SDB crossbar is mapping the different slaves into the WISHBONE address space. |
-- |
-- The speed for the VME core is 62.5 MHz. The TDC mezzanine cores however operate at|
-- 125 MHz (like this the TDC core can keep up to speed with the maximum speed the |
-- ACAM can be receiving timestamps). The crossing from the 62.5 MHz world to the |
-- 125 MHz world takes place through dedicated clock_crossing modules. |
-- The speed for the VME core is 62.5 MHz. The TDC mezzanine cores
-- internally operate at 125 MHz, but the wishbone bus works still
-- at system-wide 62.5 MHz clock.
-- |
-- The 62.5 MHz clock comes from an internal Xilinx FPGA PLL, using the 20MHz VCXO of|
-- the SVEC board. |
-- |
-- The 125 MHz clock for each TDC mezzanine comes from the PLL located on it. |
-- A clks_rsts_manager unit is responsible for automatically configuring the PLL upon|
-- the FPGA startup, using the 62.5 MHz clock. The clks_rsts_manager is keeping the |
-- the TDC mezzanine core under reset until the respective PLL gets locked. |
-- |
-- Upon powering up of the FPGA as well as after a VME reset, the whole logic gets |
-- reset (FMC1 125 MHz, FMC2 125 MHz and 62.5 MHz). This also triggers a |
......@@ -53,23 +49,23 @@
-- | | |____________________________| \ | | | |
-- | 62.5MHz \ | | | |
-- | | ____________________________ \| | _____ | |
-- | | | ____________ _______ | | | | | | |
-- | |---|->| | | clk | | | | | | | |
-- | | | | TDC mezz 1 | | cross | | | | | | | |
-- FMC1 | | | |____________| |_______| |\ | | | | | |
-- | | | FMC1 125MHz | \ | | | | | |
-- | | | ___________________ | \ | | | | | |
-- | |---|--->|_clks_rsts_manager_| | \ | | | | | |
-- | | | | | | | | | |
-- | |---| | | | | | | |
-- | | | | | | | | | |
-- FMC1 | | | TDC mezzanine 1 |\ | | | | | |
-- | | | wrapper | \ | | | | | |
-- | | | | \ | | | | | |
-- | |---| | \ | | | | | |
-- | | |____________________________| \| | | | | |
-- | | | | | | | |
-- | | ____________________________ | | | | | |
-- | | | ____________ _______ | | | | | | |
-- | | | | | | clk | | | | | | | |
-- | |---|->| TDC mezz 2 | | cross | | | S | | V | | |
-- FMC2 | | | |____________| |_______| | ---- | | | | | |
-- | | | FMC2 125MHz | | | | | | |
-- | | | ___________________ | | | | | | |
-- | |---|--->|_clks_rsts_manager_| | | | | | | |
-- | | | | | | | | | |
-- | | | | | | | | | |
-- | |---| | | S | | V | | |
-- FMC2 | | | TDC mezzanine 2 | ---- | | | | | |
-- | | | wrapper | | | | | | |
-- | | | | | | | | | |
-- | |---| | | | | | | |
-- | |____________________________| | D | <--> | M | | |
-- | | | | | | |
-- | ____________________________ | | | | | |
......@@ -137,10 +133,8 @@ use work.synthesis_descriptor.all;
-- Entity declaration for top_tdc
--=================================================================================================
entity wr_svec_tdc is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
g_simulation : boolean := false;
generic (
g_simulation : boolean := false;
g_with_wr_phy : boolean := true);
port
(-- SVEC carrier
......@@ -324,6 +318,15 @@ end wr_svec_tdc;
--=================================================================================================
architecture rtl of wr_svec_tdc is
function f_bool2int (x : boolean) return integer is
begin
if(x) then
return 1;
else
return 0;
end if;
end f_bool2int;
component spec_serial_dac is
generic (
g_num_data_bits : integer;
......@@ -664,7 +667,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_WR_CORE : xwr_core
generic map
(g_simulation => 0,
(g_simulation => f_bool2int(g_simulation),
g_phys_uart => true,
g_virtual_uart => true,
g_with_external_clock_input => false,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment