Skip to content

F
FMC TDC 1ns 5cha - Gateware
Commit 6103f3f1 authored by egousiou's avatar egousiou
Browse files
Options

patch on VME64xCore_Top.vhd and VME_IRQ_Controller.vhd to make IRQ line level-sensitive 

git-svn-id: http://svn.ohwr.org/fmc-tdc@140 85dfdc96-de2c-444c-878d-45b388be74a9
parent 2f82240d
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1399 additions and 1108 deletions
hdl/ip_cores/VMEcore/VME64xCore_Top.vhd
View file @ 6103f3f1
...@@ -77,8 +77,18 @@ ...@@ -77,8 +77,18 @@
-- Authors: -- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) -- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch) -- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 11/2012 -- Date 11/2012
-- Version v0.03 -- Version v0.03
-- Date 11/2013
-- Version Added patch from TWlostowski
-- [PATCH] VME_IRQ_Controller: made IRQ line level-sensitive.
-- There are two reasons for doing so:
-- compatibility with Wishbone and the VIC interrupt controller
-- possibility of losing an edge-triggered IRQ and hanging interrupts when
-- different cores trigger interrupts very close to each other.
-- The modified interrupter implements a retry mechanism, that is, if the IRQ line
-- gets stuck for longer than certain period (g_retry_timeout), an IRQ cycle
-- is repeated on the VME bus.
--______________________________________________________________________________ --______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------ -- ------------------------------------
...@@ -235,7 +245,7 @@ architecture RTL of VME64xCore_Top is ...@@ -235,7 +245,7 @@ architecture RTL of VME64xCore_Top is
signal s_BAR : std_logic_vector(4 downto 0); signal s_BAR : std_logic_vector(4 downto 0);
signal s_time : std_logic_vector(39 downto 0); signal s_time : std_logic_vector(39 downto 0);
signal s_bytes : std_logic_vector(12 downto 0); signal s_bytes : std_logic_vector(12 downto 0);
signal s_IRQ : std_logic; -- signal s_IRQ : std_logic;
-- Oversampled input signals -- Oversampled input signals
signal VME_RST_n_oversampled : std_logic; signal VME_RST_n_oversampled : std_logic;
...@@ -317,12 +327,12 @@ begin ...@@ -317,12 +327,12 @@ begin
clk_i => clk_i clk_i => clk_i
); );
IrqrisingEdge : RisEdgeDetection -- IrqrisingEdge : RisEdgeDetection
port map ( -- port map (
sig_i => IRQ_i, -- sig_i => IRQ_i,
clk_i => clk_i, -- clk_i => clk_i,
RisEdge_o => s_IRQ -- RisEdge_o => s_IRQ
); -- );
Inst_VME_bus : VME_bus Inst_VME_bus : VME_bus
generic map( generic map(
...@@ -431,7 +441,7 @@ begin ...@@ -431,7 +441,7 @@ begin
VME_ADDR_123_i => VME_ADDR_i(3 downto 1), VME_ADDR_123_i => VME_ADDR_i(3 downto 1),
INT_Level_i => s_INT_Level, INT_Level_i => s_INT_Level,
INT_Vector_i => s_INT_Vector , INT_Vector_i => s_INT_Vector ,
INT_Req_i => s_IRQ, INT_Req_i => irq_i,--s_IRQ,
VME_IRQ_n_o => s_VME_IRQ_n_o, VME_IRQ_n_o => s_VME_IRQ_n_o,
VME_IACKOUT_n_o => VME_IACKOUT_n_o, VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_n_o => s_VME_DTACK_IRQ, VME_DTACK_n_o => s_VME_DTACK_IRQ,
......
hdl/ip_cores/VMEcore/VME_IRQ_Controller.vhd
View file @ 6103f3f1
...@@ -29,8 +29,8 @@ ...@@ -29,8 +29,8 @@
-- All the output signals are registered -- All the output signals are registered
-- To implement the 5 phases before mentioned the follow FSM has been implemented: -- To implement the 5 phases before mentioned the follow FSM has been implemented:
-- __________ -- __________
-- |--| IACKOUT2 |<-| -- |--| IACKOUT2 |<-|
-- | |__________| | -- | |__________| |
-- | | -- | |
-- | _________ | _________ _________ _________ -- | _________ | _________ _________ _________
...@@ -83,7 +83,17 @@ ...@@ -83,7 +83,17 @@
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) -- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch) -- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 11/2012 -- Date 11/2012
-- Version v0.03 -- Version v0.03
-- Date 11/2013
-- Version Added patch from TWlostowski
-- [PATCH] VME_IRQ_Controller: made IRQ line level-sensitive.
-- There are two reasons for doing so:
-- compatibility with Wishbone and the VIC interrupt controller
-- possibility of losing an edge-triggered IRQ and hanging interrupts when
-- different cores trigger interrupts very close to each other.
-- The modified interrupter implements a retry mechanism, that is, if the IRQ line
-- gets stuck for longer than certain period (g_retry_timeout), an IRQ cycle
-- is repeated on the VME bus.
--_____________________________________________________________________________________ --_____________________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------ -- ------------------------------------
...@@ -106,6 +116,8 @@ use work.vme64x_pack.all; ...@@ -106,6 +116,8 @@ use work.vme64x_pack.all;
-- Entity declaration -- Entity declaration
--=========================================================================== --===========================================================================
entity VME_IRQ_Controller is entity VME_IRQ_Controller is
generic
(g_retry_timeout : integer range 1024 to 16777215 := 62500);
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
reset_n_i : in std_logic; reset_n_i : in std_logic;
...@@ -130,7 +142,11 @@ end VME_IRQ_Controller; ...@@ -130,7 +142,11 @@ end VME_IRQ_Controller;
--=========================================================================== --===========================================================================
architecture Behavioral of VME_IRQ_Controller is architecture Behavioral of VME_IRQ_Controller is
--input signals --input signals
signal s_INT_Req_sample : std_logic; -- signal s_INT_Req_sample : std_logic;
signal int_trigger_p : std_logic;
signal retry_count : unsigned(23 downto 0);
type t_retry_state is (R_IDLE, R_IRQ, R_WAIT_RETRY);
signal retry_state : t_retry_state;
--output signals --output signals
signal s_DTACK_OE_o : std_logic; signal s_DTACK_OE_o : std_logic;
signal s_enable : std_logic; signal s_enable : std_logic;
...@@ -166,10 +182,40 @@ begin ...@@ -166,10 +182,40 @@ begin
FallEdge_o => s_AS_FallingEdge FallEdge_o => s_AS_FallingEdge
); );
INT_ReqinputSample : process(clk_i) -- INT_ReqinputSample : process(clk_i)
begin p_int_retry : process(clk_i)
if rising_edge(clk_i) then begin
s_INT_Req_sample <= INT_Req_i; if rising_edge(clk_i) then
if reset_n_i = '0' then
int_trigger_p <= '0';
retry_count <= (others => '0');
retry_state <= R_IDLE;
else
case retry_state is
when R_IDLE =>
if(INT_Req_i = '1') then
retry_state <= R_IRQ;
end if;
when R_IRQ =>
retry_count <= (others => '0');
int_trigger_p <= '1';
retry_state <= R_WAIT_RETRY;
when R_WAIT_RETRY =>
int_trigger_p <= '0';
if(INT_Req_i = '1') then
retry_count <= retry_count + 1;
if(retry_count = g_retry_timeout) then
retry_state <= R_IRQ;
end if;
else
retry_state <= R_IDLE;
end if;
end case;
end if;
--s_INT_Req_sample <= INT_Req_i;
end if; end if;
end process; end process;
...@@ -225,11 +271,12 @@ begin ...@@ -225,11 +271,12 @@ begin
end if; end if;
end process; end process;
-- Update next state -- Update next state
process(s_currs, s_INT_Req_sample, VME_AS_n_i, VME_DS_n_i, s_ack_int, VME_IACKIN_n_i, s_AS_RisingEdge) process(s_currs, int_trigger_p, VME_AS_n_i, VME_DS_n_i, s_ack_int, VME_IACKIN_n_i, s_AS_RisingEdge)
begin begin
case s_currs is case s_currs is
when IDLE => when IDLE =>
if s_INT_Req_sample = '1' and VME_IACKIN_n_i = '1' then --if s_INT_Req_sample = '1' and VME_IACKIN_n_i = '1' then
if int_trigger_p = '1' and VME_IACKIN_n_i = '1' then
s_nexts <= IRQ; s_nexts <= IRQ;
elsif VME_IACKIN_n_i = '0' then elsif VME_IACKIN_n_i = '0' then
s_nexts <= IACKOUT2; s_nexts <= IACKOUT2;
......
hdl/rtl/data_formatting.vhd
View file @ 6103f3f1
...@@ -361,7 +361,7 @@ begin ...@@ -361,7 +361,7 @@ begin
-- (un_current_retrig_from_roll_over is 0 and un_acam_start_nb = un_current_retrig_nb_offset) -- (un_current_retrig_from_roll_over is 0 and un_acam_start_nb = un_current_retrig_nb_offset)
-- the values of the previous second should be used. -- the values of the previous second should be used.
-- Also, according to the ACAM documentation there is an indeterminacy to whether the fine time refers -- Also, according to the ACAM documentation there is an indeterminacy to whether the fine time refers
-- to the previous retrigger or the current one. The equation described on line 386 describes -- to the previous retrigger or the current one. The equation described on line 392 describes
-- the case where: a timestamp came on the same retrigger after a new second but the ACAM assigned -- the case where: a timestamp came on the same retrigger after a new second but the ACAM assigned
-- it to the previous retrigger (the "un_current_retrig_from_roll_over = 0" describes that a new second -- it to the previous retrigger (the "un_current_retrig_from_roll_over = 0" describes that a new second
-- has arrived; the "un_acam_fine_time > 6318" desribes a fine time that is referred to the previous retrigger; -- has arrived; the "un_acam_fine_time > 6318" desribes a fine time that is referred to the previous retrigger;
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 6103f3f1
...@@ -16,8 +16,10 @@ ...@@ -16,8 +16,10 @@
-- o the TDC core | -- o the TDC core |
-- o the I2C core for the communication with the TDC board EEPROM | -- o the I2C core for the communication with the TDC board EEPROM |
-- o the OneWire core for the communication with the TDC board UniqueID&Thermetec | -- o the OneWire core for the communication with the TDC board UniqueID&Thermetec |
-- o the IRQ controller core that concentrates several interrupt sources into one |
-- interrupt request line. |
-- For the interconnection between the GNUM/VME core and the different cores (TDC, | -- For the interconnection between the GNUM/VME core and the different cores (TDC, |
-- I2C, 1W) the unit also instantiates an SDB crossbar. | -- I2C, 1W, IRQ) the unit also instantiates an SDB crossbar. |
-- | -- |
-- ______________________________ | -- ______________________________ |
-- | | | -- | | |
...@@ -27,11 +29,15 @@ ...@@ -27,11 +29,15 @@
-- | |________________| | S | | | -- | |________________| | S | | |
-- | ________________ | | | | -- | ________________ | | | |
-- | | | | | | | -- | | | | | | |
-- EEPROM chip <--> | | I2C core | | D | | <--> GNUM/VME core | -- EEPROM chip <--> | | I2C core | | | | <--> |
-- | |________________| | | | |
-- | ________________ | D | | GNUM/VME core |
-- | | | | | | |
-- 1W chip <--> | | 1W core | | | | <--> |
-- | |________________| | | | | -- | |________________| | | | |
-- | ________________ | | | | -- | ________________ | | | |
-- | | | | B | | | -- | | | | B | | |
-- 1W chip <--> | | 1W core | | | | <--> | -- | | IRQ ctrler | | | | <--> |
-- | |________________| |___| | | -- | |________________| |___| | |
-- | | | -- | | |
-- |_______________________________| | -- |_______________________________| |
...@@ -39,7 +45,7 @@ ...@@ -39,7 +45,7 @@
-- _______________________________ | -- _______________________________ |
-- | | | -- | | |
-- DAC chip <--> | clks_rsts_manager | | -- DAC chip <--> | clks_rsts_manager | |
-- |_______________________________| | -- PLL chip |_______________________________| |
-- | -- |
-- Figure 1: FMC TDC mezzanine architecture | -- Figure 1: FMC TDC mezzanine architecture |
-- | -- |
...@@ -406,21 +412,21 @@ begin ...@@ -406,21 +412,21 @@ begin
cmp_irq_controller : irq_controller cmp_irq_controller : irq_controller
port map port map
(clk_sys_i => clk_125m_i, (clk_sys_i => clk_125m_i,
rst_n_i => general_rst_n, rst_n_i => general_rst_n,
wb_adr_i => cnx_master_out(c_WB_SLAVE_IRQ).adr(3 downto 2), wb_adr_i => cnx_master_out(c_WB_SLAVE_IRQ).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_IRQ).dat, wb_dat_i => cnx_master_out(c_WB_SLAVE_IRQ).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_IRQ).dat, wb_dat_o => cnx_master_in(c_WB_SLAVE_IRQ).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_IRQ).cyc, wb_cyc_i => cnx_master_out(c_WB_SLAVE_IRQ).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_IRQ).sel, wb_sel_i => cnx_master_out(c_WB_SLAVE_IRQ).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_IRQ).stb, wb_stb_i => cnx_master_out(c_WB_SLAVE_IRQ).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_IRQ).we, wb_we_i => cnx_master_out(c_WB_SLAVE_IRQ).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_IRQ).ack, wb_ack_o => cnx_master_in(c_WB_SLAVE_IRQ).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_IRQ).stall, wb_stall_o => cnx_master_in(c_WB_SLAVE_IRQ).stall,
wb_int_o => wb_irq_o, wb_int_o => wb_irq_o,
irq_tdc_tstamps_i => irq_tstamp_p, irq_tdc_tstamps_i => irq_tstamp_p,
irq_tdc_time_i => irq_time_p, irq_tdc_time_i => irq_time_p,
irq_tdc_acam_err_i => irq_acam_err_p); irq_tdc_acam_err_i => irq_acam_err_p);
end rtl; end rtl;
......
hdl/rtl/start_retrig_ctrl.vhd
View file @ 6103f3f1
...@@ -275,7 +275,7 @@ begin ...@@ -275,7 +275,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- When a new second starts, all values are captured and stored as offsets. -- When a new second starts, all values are captured and stored as offsets.
-- when a timestamps arrives, these offset will be subrstracted in order -- when a timestamp arrives, these offset will be subtracted in order
-- to base the final timestamp with respect to the current second. -- to base the final timestamp with respect to the current second.
capture_offset: process (clk_i) capture_offset: process (clk_i)
begin begin
......
hdl/syn/svec/svec-tdc-fmc.gise
View file @ 6103f3f1
...@@ -103,7 +103,7 @@ ...@@ -103,7 +103,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1384338996" xil_pn:in_ck="5268971704634117961" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7543648610729664005" xil_pn:start_ts="1384338805"> <transform xil_pn:end_ts="1385128254" xil_pn:in_ck="5268971704634117961" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7543648610729664005" xil_pn:start_ts="1385128088">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -125,7 +125,7 @@ ...@@ -125,7 +125,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1384339012" xil_pn:in_ck="-3760130385703199631" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8504525175841796663" xil_pn:start_ts="1384338996"> <transform xil_pn:end_ts="1385128269" xil_pn:in_ck="-3760130385703199631" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8504525175841796663" xil_pn:start_ts="1385128254">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -135,7 +135,7 @@ ...@@ -135,7 +135,7 @@
<outfile xil_pn:name="top_tdc.ngd"/> <outfile xil_pn:name="top_tdc.ngd"/>
<outfile xil_pn:name="top_tdc_ngdbuild.xrpt"/> <outfile xil_pn:name="top_tdc_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1384339231" xil_pn:in_ck="-7440346353620165565" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7568465460566446564" xil_pn:start_ts="1384339012"> <transform xil_pn:end_ts="1385128482" xil_pn:in_ck="-7440346353620165565" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7568465460566446564" xil_pn:start_ts="1385128269">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
...@@ -148,7 +148,7 @@ ...@@ -148,7 +148,7 @@
<outfile xil_pn:name="top_tdc_summary.xml"/> <outfile xil_pn:name="top_tdc_summary.xml"/>
<outfile xil_pn:name="top_tdc_usage.xml"/> <outfile xil_pn:name="top_tdc_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1384339823" xil_pn:in_ck="4998236143670007004" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-7978487711023391987" xil_pn:start_ts="1384339231"> <transform xil_pn:end_ts="1385128706" xil_pn:in_ck="4998236143670007004" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-7978487711023391987" xil_pn:start_ts="1385128482">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -163,7 +163,7 @@ ...@@ -163,7 +163,7 @@
<outfile xil_pn:name="top_tdc_pad.txt"/> <outfile xil_pn:name="top_tdc_pad.txt"/>
<outfile xil_pn:name="top_tdc_par.xrpt"/> <outfile xil_pn:name="top_tdc_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1384339889" xil_pn:in_ck="182976557419624816" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5293564962942599218" xil_pn:start_ts="1384339823"> <transform xil_pn:end_ts="1385128766" xil_pn:in_ck="182976557419624816" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5293564962942599218" xil_pn:start_ts="1385128706">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
...@@ -175,7 +175,7 @@ ...@@ -175,7 +175,7 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1384339823" xil_pn:in_ck="-7440346353620165697" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1384339778"> <transform xil_pn:end_ts="1385128706" xil_pn:in_ck="-7440346353620165697" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1385128683">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/syn/svec/top_tdc.bin
View file @ 6103f3f1
No preview for this file type
hdl/syn/svec/top_tdc.twr
View file @ 6103f3f1
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/svec/top_tdc_summary.html
View file @ 6103f3f1
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment