git-svn-id: http://svn.ohwr.org/fmc-tdc@121 85dfdc96-de2c-444c-878d-45b388be74a9

6b1a7386 · egousiou · 13d729a4 · 6b1a7386 · 6b1a7386 · 6b1a7386
Commit 6b1a7386 authored Oct 02, 2013 by egousiou
27 changed files
--- a/hdl/syn/spec/tdc.bit
+++ b/hdl/syn/spec/tdc.bit
--- a/hdl/syn/spec/tdc_par_script.tcl
+++ b/hdl/syn/spec/tdc_par_script.tcl
+cd <to /syn/spec>
+ngdbuild -uc synplicity.ucf syn_tdc.edf
+map -detail -w -timing -ol high syn_tdc.ngd
+par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf
+trce -v 32 -u par_tdc.ncd syn_tdc.pcf -o timing_report
+bitgen -w -g Binary:Yes par_tdc.ncd tdc
+
+
--- a/hdl/syn/spec/tdc_syn.prj
+++ b/hdl/syn/spec/tdc_syn.prj
+#-- Synopsys, Inc.
+#-- Version D-2010.03
+#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn.prj
+#-- Written on Fri Jul 4 10:00:00 2011
+
+
+#project files
+
+add_file -include "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
+add_file -include "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ndf"
+
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_pkg.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
+
+add_file -vhdl -lib work "../src/ip_cores/genram_pkg.vhd"
+add_file -vhdl -lib work "../src/ip_cores/wishbone_pkg.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gencores_pkg.vhd"
+add_file -vhdl -lib work "../src/ip_cores/sdb_meta_pkg.vhd"
+add_file -vhdl -lib work "../src/rtl/tdc_core_pkg.vhd"
+
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/generic_async_fifo_wrapper.vhd"
+
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_ser.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_des.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_decode32.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/wbmaster32.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_dma_master.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_dma_master.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_arbiter.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/pulse_sync_rtl.vhd"
+add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core.vhd"
+add_file -vhdl -lib work "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
+
+add_file -vhdl -lib work "../src/ip_cores/wb_crossbar/sdb_rom.vhd"
+add_file -vhdl -lib work "../src/ip_cores/wb_crossbar/xwb_crossbar.vhd"
+add_file -vhdl -lib work "../src/ip_cores/wb_crossbar/xwb_sdb_crossbar.vhd"
+
+add_file -vhdl -lib work  "../src/ip_cores/wb_slave_adapter/wb_slave_adapter.vhd"
+
+add_file -vhdl -lib work  "../src/ip_cores/wb_i2c_master/i2c_master_bit_ctrl.vhd"
+add_file -vhdl -lib work  "../src/ip_cores/wb_i2c_master/i2c_master_byte_ctrl.vhd"
+add_file -vhdl -lib work  "../src/ip_cores/wb_i2c_master/i2c_master_top.vhd"
+add_file -vhdl -lib work  "../src/ip_cores/wb_i2c_master/wb_i2c_master.vhd"
+add_file -vhdl -lib work  "../src/ip_cores/wb_i2c_master/xwb_i2c_master.vhd"
+
+add_file -verilog -lib work  "../src/ip_cores/wb_onewire_master/sockit_owm.v"
+add_file -vhdl -lib work  "../src/ip_cores/wb_onewire_master/wb_onewire_master.vhd"
+add_file -vhdl -lib work "../src/ip_cores/wb_onewire_master/xwb_onewire_master.vhd"
+
+add_file -vhdl -lib work "../src/ip_cores/wb_irq_controller/irq_controller_regs.vhd"
+add_file -vhdl -lib work "../src/ip_cores/wb_irq_controller/irq_controller.vhd"
+
+add_file -vhdl -lib work "../src/ip_cores/carrier_csr.vhd"
+
+add_file -vhdl -lib work "../src/rtl/fmc_tdc_core.vhd"
+add_file -vhdl -lib work "../src/rtl/free_counter.vhd"
+add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
+add_file -vhdl -lib work "../src/rtl/decr_counter.vhd"
+add_file -vhdl -lib work "../src/rtl/clks_rsts_manager.vhd"
+add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
+add_file -vhdl -lib work "../src/rtl/start_retrig_ctrl.vhd"
+add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
+add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
+add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
+add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
+add_file -vhdl -lib work "../src/rtl/circular_buffer.vhd"
+add_file -vhdl -lib work "../src/rtl/irq_generator.vhd"
+add_file -vhdl -lib work "../src/rtl/reg_ctrl.vhd"
+add_file -vhdl -lib work "../src/rtl/leds_manager.vhd" 
+
+add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
+
+add_file -constraint -lib work "./tdc_syn_constraints.sdc"
+
+#implementation attributes (Verilog)
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+
+#implementation: "syn"
+impl -add syn -type fpga
+impl -active "syn"
+
+#device options
+set_option -technology Spartan6
+set_option -part XC6SLX45T
+set_option -package FGG484
+set_option -speed_grade -3
+set_option -part_companion ""
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 0
+set_option -synthesis_onoff_pragma 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+set_option -no_sequential_opt 0
+
+#compilation/mapping options
+set_option -use_fsm_explorer 0
+set_option -top_module "top_tdc"
+
+# mapper_options
+set_option -frequency 200
+set_option -default_enum_encoding onehot
+set_option -write_verilog 0
+set_option -write_vhdl 0
+set_option -num_critical_paths 5
+
+# Xilinx options
+set_option -run_prop_extract 1
+set_option -maxfan 500
+set_option -disable_io_insertion 0
+set_option -pipe 0
+set_option -retiming 0
+set_option -update_models_cp 0
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -enable_prepacking 1
+set_option -enhance_optimization 1
+
+# NFilter (Netlist restructure)
+set_option -enable_nfilter 1
+set_option -popfeed 1
+set_option -constprop 1
+set_option -createhierarchy 0
+#VIF options
+set_option -write_vif 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./syn_tdc.edf"
+#project -result_file "./test_tdc_pll/syn_tdc.edf"
+#project -result_file "./test_tdc_acam/syn_tdc.edf"
+#project -run -fg synthesis
+#project -run -fg timing
\ No newline at end of file
--- a/hdl/syn/spec/tdc_syn_constraints.sdc
+++ b/hdl/syn/spec/tdc_syn_constraints.sdc
+# Synopsys, Inc. constraint file
+# C:/FMC_TDC/evas_fmc_tdc/syn/tdc_syn_constraints.sdc
+# Written on Wed Jul 17 10:47:25 2013
+# by Synplify Premier with Design Planner, F-2012.03 Scope Editor
+
+#
+# Collections
+#
+
+#
+# Clocks
+#
+define_clock   {p:tdc_clk_p_i} -name {tdc_clk125p}  -freq 125 -clockgroup default_clkgroup28__1
+define_clock   {p:spec_clk_i} -name {spec_clk20}  -freq 20 -clockgroup default_clkgroup29__2
+define_clock   {p:acam_refclk_p_i} -name {acam_refclk31_25}  -freq 31.25 -clockgroup default_clkgroup30__3
+define_clock   {n:gnum_interface_block.cmp_clk_in.rx_bufg_pll_x1} -name {gnum_clk200}  -freq 200 -clockgroup default_clkgroup31__4
+
+#
+# Clock to Clock
+#
+
+#
+# Inputs/Outputs
+#
+
+#
+# Registers
+#
+
+#
+# Delay Paths
+#
+define_multicycle_path  -from {{p:data_bus_io[27:0]}}  3
+define_multicycle_path  -to {{p:data_bus_io[27:0]}}  3
+define_multicycle_path  -to {{p:address_o[3:0]}}  3
+define_false_path  -from {{p:spec_aux0_i}} 
+define_false_path  -from {{p:spec_aux1_i}} 
+define_false_path  -to {{p:spec_aux2_o}} 
+define_false_path  -to {{p:spec_aux3_o}} 
+define_false_path  -to {{p:spec_aux4_o}} 
+define_false_path  -to {{p:spec_aux5_o}} 
+define_false_path  -to {{p:spec_led_green_o}} 
+define_false_path  -to {{p:spec_led_red_o}} 
+define_false_path  -to {{p:tdc_led_status_o}} 
+define_false_path  -to {{p:tdc_led_trig1_o}} 
+define_false_path  -to {{p:tdc_led_trig2_o}} 
+define_false_path  -to {{p:tdc_led_trig3_o}} 
+define_false_path  -to {{p:tdc_led_trig4_o}} 
+define_false_path  -to {{p:tdc_led_trig5_o}} 
+define_false_path  -from {{p:rst_n_a_i}} 
+define_false_path  -from {{i:gnum_interface_block.rst_reg}} 
+
+#
+# Attributes
+#
+define_global_attribute  {syn_useioff} {1}
+define_global_attribute  {syn_noarrayports} {1}
+define_global_attribute  {syn_netlist_hierarchy} {0}
+define_attribute {p:acam_refclk_p_i} {syn_loc} {E16}
+define_attribute {p:acam_refclk_n_i} {syn_loc} {F16}
+define_attribute {p:tdc_clk_p_i} {syn_loc} {L20}
+define_attribute {p:tdc_clk_n_i} {syn_loc} {L22}
+define_attribute {p:tdc_led_trig1_o} {syn_loc} {W18}
+define_attribute {p:tdc_led_trig2_o} {syn_loc} {B20}
+define_attribute {p:tdc_led_trig3_o} {syn_loc} {A20}
+define_attribute {p:term_en_1_o} {syn_loc} {Y11}
+define_attribute {p:term_en_2_o} {syn_loc} {AB11}
+define_attribute {p:ef1_i} {syn_loc} {W12}
+define_attribute {p:ef2_i} {syn_loc} {Y12}
+define_attribute {p:term_en_3_o} {syn_loc} {R11}
+define_attribute {p:term_en_4_o} {syn_loc} {T11}
+define_attribute {p:term_en_5_o} {syn_loc} {R13}
+define_attribute {p:tdc_led_status_o} {syn_loc} {T14}
+define_attribute {p:tdc_led_trig4_o} {syn_loc} {D17}
+define_attribute {p:tdc_led_trig5_o} {syn_loc} {C18}
+define_attribute {p:pll_sclk_o} {syn_loc} {AA16}
+define_attribute {p:pll_dac_sync_o} {syn_loc} {AB16}
+define_attribute {p:pll_cs_o} {syn_loc} {Y17}
+define_attribute {p:cs_n_o} {syn_loc} {AB17}
+define_attribute {p:prsnt_m2c_n_i} {syn_loc} {AB14}
+define_attribute {p:err_flag_i} {syn_loc} {V11}
+define_attribute {p:int_flag_i} {syn_loc} {W11}
+define_attribute {p:start_dis_o} {syn_loc} {T15}
+define_attribute {p:stop_dis_o} {syn_loc} {U15}
+define_attribute {p:rst_n_a_i} {syn_loc} {N20}
+define_attribute {p:p2l_clk_p_i} {syn_loc} {M20}
+define_attribute {p:p2l_clk_n_i} {syn_loc} {M19}
+define_attribute {p:p2l_data_i[15]} {syn_loc} {H19}
+define_attribute {p:p2l_data_i[14]} {syn_loc} {F21}
+define_attribute {p:p2l_data_i[13]} {syn_loc} {F22}
+define_attribute {p:p2l_data_i[12]} {syn_loc} {E20}
+define_attribute {p:p2l_data_i[11]} {syn_loc} {E22}
+define_attribute {p:p2l_data_i[10]} {syn_loc} {J19}
+define_attribute {p:p2l_data_i[9]} {syn_loc} {H20}
+define_attribute {p:p2l_data_i[8]} {syn_loc} {K19}
+define_attribute {p:p2l_data_i[7]} {syn_loc} {K18}
+define_attribute {p:p2l_data_i[6]} {syn_loc} {G20}
+define_attribute {p:p2l_data_i[5]} {syn_loc} {G22}
+define_attribute {p:p2l_data_i[4]} {syn_loc} {K17}
+define_attribute {p:p2l_data_i[3]} {syn_loc} {L17}
+define_attribute {p:p2l_data_i[2]} {syn_loc} {H21}
+define_attribute {p:p2l_data_i[1]} {syn_loc} {H22}
+define_attribute {p:p2l_data_i[0]} {syn_loc} {K20}
+define_attribute {p:p2l_dframe_i} {syn_loc} {J22}
+define_attribute {p:p2l_valid_i} {syn_loc} {L19}
+define_attribute {p:p2l_rdy_o} {syn_loc} {J16}
+define_attribute {p:p_wr_req_i[1]} {syn_loc} {M21}
+define_attribute {p:p_wr_req_i[0]} {syn_loc} {M22}
+define_attribute {p:p_wr_rdy_o[1]} {syn_loc} {K16}
+define_attribute {p:p_wr_rdy_o[0]} {syn_loc} {L15}
+define_attribute {p:rx_error_o} {syn_loc} {J17}
+define_attribute {p:vc_rdy_i[1]} {syn_loc} {B22}
+define_attribute {p:vc_rdy_i[0]} {syn_loc} {B21}
+define_attribute {p:l2p_clk_p_o} {syn_loc} {K21}
+define_attribute {p:l2p_clk_n_o} {syn_loc} {K22}
+define_attribute {p:l2p_data_o[15]} {syn_loc} {Y21}
+define_attribute {p:l2p_data_o[14]} {syn_loc} {W20}
+define_attribute {p:l2p_data_o[13]} {syn_loc} {V20}
+define_attribute {p:l2p_data_o[12]} {syn_loc} {V22}
+define_attribute {p:l2p_data_o[11]} {syn_loc} {T19}
+define_attribute {p:l2p_data_o[10]} {syn_loc} {T21}
+define_attribute {p:l2p_data_o[9]} {syn_loc} {R22}
+define_attribute {p:l2p_data_o[8]} {syn_loc} {P22}
+define_attribute {p:l2p_data_o[7]} {syn_loc} {Y22}
+define_attribute {p:l2p_data_o[6]} {syn_loc} {W22}
+define_attribute {p:l2p_data_o[5]} {syn_loc} {V19}
+define_attribute {p:l2p_data_o[4]} {syn_loc} {V21}
+define_attribute {p:l2p_data_o[3]} {syn_loc} {T20}
+define_attribute {p:l2p_data_o[2]} {syn_loc} {P18}
+define_attribute {p:l2p_data_o[1]} {syn_loc} {P21}
+define_attribute {p:l2p_data_o[0]} {syn_loc} {P16}
+define_attribute {p:l2p_dframe_o} {syn_loc} {U22}
+define_attribute {p:l2p_valid_o} {syn_loc} {T18}
+define_attribute {p:l2p_edb_o} {syn_loc} {U20}
+define_attribute {p:l2p_rdy_i} {syn_loc} {U19}
+define_attribute {p:l_wr_rdy_i[1]} {syn_loc} {T22}
+define_attribute {p:l_wr_rdy_i[0]} {syn_loc} {R20}
+define_attribute {p:p_rd_d_rdy_i[1]} {syn_loc} {P19}
+define_attribute {p:p_rd_d_rdy_i[0]} {syn_loc} {N16}
+define_attribute {p:tx_error_i} {syn_loc} {M17}
+define_attribute {p:irq_p_o} {syn_loc} {U16}
+define_attribute {p:pll_sdo_i} {syn_loc} {AB18}
+define_attribute {p:pll_status_i} {syn_loc} {Y18}
+define_attribute {p:pll_sdi_o} {syn_loc} {AA18}
+define_attribute {p:start_from_fpga_o} {syn_loc} {W17}
+define_attribute {p:data_bus_io[27]} {syn_loc} {AB4}
+define_attribute {p:data_bus_io[26]} {syn_loc} {AA4}
+define_attribute {p:data_bus_io[25]} {syn_loc} {AB9}
+define_attribute {p:data_bus_io[24]} {syn_loc} {Y9}
+define_attribute {p:data_bus_io[23]} {syn_loc} {Y10}
+define_attribute {p:data_bus_io[22]} {syn_loc} {W10}
+define_attribute {p:data_bus_io[21]} {syn_loc} {U10}
+define_attribute {p:data_bus_io[20]} {syn_loc} {T10}
+define_attribute {p:data_bus_io[19]} {syn_loc} {AB8}
+define_attribute {p:data_bus_io[18]} {syn_loc} {AA8}
+define_attribute {p:data_bus_io[17]} {syn_loc} {AB7}
+define_attribute {p:data_bus_io[16]} {syn_loc} {Y7}
+define_attribute {p:data_bus_io[15]} {syn_loc} {V9}
+define_attribute {p:data_bus_io[14]} {syn_loc} {U9}
+define_attribute {p:data_bus_io[13]} {syn_loc} {AB6}
+define_attribute {p:data_bus_io[12]} {syn_loc} {AA6}
+define_attribute {p:data_bus_io[11]} {syn_loc} {R8}
+define_attribute {p:data_bus_io[10]} {syn_loc} {R9}
+define_attribute {p:data_bus_io[9]} {syn_loc} {AB5}
+define_attribute {p:data_bus_io[8]} {syn_loc} {Y5}
+define_attribute {p:data_bus_io[7]} {syn_loc} {AB12}
+define_attribute {p:data_bus_io[6]} {syn_loc} {U8}
+define_attribute {p:data_bus_io[5]} {syn_loc} {AA12}
+define_attribute {p:data_bus_io[4]} {syn_loc} {T8}
+define_attribute {p:data_bus_io[3]} {syn_loc} {W8}
+define_attribute {p:data_bus_io[2]} {syn_loc} {V7}
+define_attribute {p:data_bus_io[1]} {syn_loc} {Y6}
+define_attribute {p:data_bus_io[0]} {syn_loc} {W6}
+define_attribute {p:address_o[3]} {syn_loc} {AB15}
+define_attribute {p:address_o[2]} {syn_loc} {Y15}
+define_attribute {p:address_o[1]} {syn_loc} {U12}
+define_attribute {p:address_o[0]} {syn_loc} {T12}
+define_attribute {p:oe_n_o} {syn_loc} {V13}
+define_attribute {p:rd_n_o} {syn_loc} {AB13}
+define_attribute {p:wr_n_o} {syn_loc} {Y13}
+define_attribute {p:enable_inputs_o} {syn_loc} {C19}
+define_attribute {p:spec_aux0_i} {syn_loc} {C22}
+define_attribute {p:spec_aux1_i} {syn_loc} {D21}
+define_attribute {p:spec_aux2_o} {syn_loc} {G19}
+define_attribute {p:spec_aux3_o} {syn_loc} {F20}
+define_attribute {p:spec_aux4_o} {syn_loc} {F18}
+define_attribute {p:spec_aux5_o} {syn_loc} {C20}
+define_attribute {p:spec_led_green_o} {syn_loc} {E5}
+define_attribute {p:spec_led_red_o} {syn_loc} {D5}
+define_attribute {p:spec_clk_i} {syn_loc} {H12}
+define_attribute {p:carrier_one_wire_b} {syn_loc} {D4}
+define_attribute {p:mezz_one_wire_b} {syn_loc} {A19}
+define_attribute {p:sys_scl_b} {syn_loc} {F7}
+define_attribute {p:sys_sda_b} {syn_loc} {F8}
+define_attribute {p:pcb_ver_i[0]} {syn_loc} {P5}
+define_attribute {p:pcb_ver_i[1]} {syn_loc} {P4}
+define_attribute {p:pcb_ver_i[2]} {syn_loc} {AA2}
+define_attribute {p:pcb_ver_i[3]} {syn_loc} {AA1}
+define_attribute {p:prsnt_m2c_n_i} {syn_loc} {AB14}
+
+#
+# I/O Standards
+#
+define_io_standard               {acam_refclk_p_i} syn_pad_type {DIFF_SSTL_18_Class_II}
+define_io_standard               {acam_refclk_n_i} syn_pad_type {DIFF_SSTL_18_Class_II}
+define_io_standard               {tdc_clk_p_i} syn_pad_type {DIFF_SSTL_18_Class_II}
+define_io_standard               {tdc_clk_n_i} syn_pad_type {DIFF_SSTL_18_Class_II}
+define_io_standard               {tdc_led_trig1_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {tdc_led_trig2_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {tdc_led_trig3_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {term_en_1_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {term_en_2_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {ef1_i} syn_pad_type {LVCMOS_25}
+define_io_standard               {ef2_i} syn_pad_type {LVCMOS_25}
+define_io_standard               {term_en_3_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {term_en_4_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {term_en_5_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {tdc_led_status_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {tdc_led_trig4_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {tdc_led_trig5_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {pll_sclk_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {pll_dac_sync_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {pll_cs_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {cs_n_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {prsnt_m2c_n_i} syn_pad_type {LVCMOS_25}
+define_io_standard               {rst_n_a_i} syn_pad_type {LVCMOS18}
+define_io_standard               {p2l_clk_p_i} syn_pad_type {DIFF_SSTL_18_Class_II}
+define_io_standard               {p2l_clk_n_i} syn_pad_type {DIFF_SSTL_18_Class_II}
+define_io_standard               {p2l_data_i[15:0]} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {p2l_dframe_i} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {p2l_valid_i} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {p2l_rdy_o} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {p_wr_req_i[1:0]} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {p_wr_rdy_o[1:0]} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {rx_error_o} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {vc_rdy_i[1:0]} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {l2p_clk_p_o} syn_pad_type {DIFF_SSTL_18_Class_II}
+define_io_standard               {l2p_clk_n_o} syn_pad_type {DIFF_SSTL_18_Class_II}
+define_io_standard               {l2p_data_o[15:0]} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {l2p_dframe_o} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {l2p_valid_o} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {l2p_edb_o} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {l2p_rdy_i} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {l_wr_rdy_i[1:0]} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {p_rd_d_rdy_i[1:0]} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {tx_error_i} syn_pad_type {SSTL_18_Class_I}
+define_io_standard               {irq_p_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {pcb_ver_i[0]} syn_pad_type {LVCMOS_15}
+define_io_standard               {pcb_ver_i[1]} syn_pad_type {LVCMOS_15}
+define_io_standard               {pcb_ver_i[2]} syn_pad_type {LVCMOS_15}
+define_io_standard               {pcb_ver_i[3]} syn_pad_type {LVCMOS_15}
+define_io_standard               {prsnt_m2c_n_i} syn_pad_type {LVCMOS_25}
+define_io_standard               {pll_status_i} syn_pad_type {LVCMOS_25}
+define_io_standard               {pll_sdo_i} syn_pad_type {LVCMOS_25}
+define_io_standard               {pll_sdi_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {err_flag_i} syn_pad_type {LVCMOS_25}
+define_io_standard               {int_flag_i} syn_pad_type {LVCMOS_25}
+define_io_standard               {start_dis_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {start_from_fpga_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {stop_dis_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {data_bus_io[27:0]} syn_pad_type {LVCMOS_25}
+define_io_standard               {address_o[3:0]} syn_pad_type {LVCMOS_25}
+define_io_standard               {oe_n_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {rd_n_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {wr_n_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {enable_inputs_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {spec_aux0_i} syn_pad_type {LVCMOS18}
+define_io_standard               {spec_aux1_i} syn_pad_type {LVCMOS18}
+define_io_standard               {spec_aux2_o} syn_pad_type {LVCMOS18}
+define_io_standard               {spec_aux3_o} syn_pad_type {LVCMOS18}
+define_io_standard               {spec_aux4_o} syn_pad_type {LVCMOS18}
+define_io_standard               {spec_aux5_o} syn_pad_type {LVCMOS18}
+define_io_standard               {spec_led_green_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {spec_led_red_o} syn_pad_type {LVCMOS_25}
+define_io_standard               {spec_clk_i} syn_pad_type {LVCMOS_25}
+define_io_standard               {carrier_one_wire_b} syn_pad_type {LVCMOS_25}
+define_io_standard               {sys_scl_b} syn_pad_type {LVCMOS_25}
+define_io_standard               {sys_sda_b} syn_pad_type {LVCMOS_25}
+define_io_standard               {mezz_one_wire_b} syn_pad_type {LVCMOS_25}
+
+#
+# Compile Points
+#
+
+#
+# Other
+#
--- a/hdl/syn/spec/timing_report.twr
+++ b/hdl/syn/spec/timing_report.twr
--- a/hdl/syn/svec/svec-tdc-fmc.gise
+++ b/hdl/syn/svec/svec-tdc-fmc.gise
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="svec-tdc-fmc.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema"/>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
--- a/hdl/syn/svec/svec-tdc-fmc.xise
+++ b/hdl/syn/svec/svec-tdc-fmc.xise
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx150t" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top_tdc|rtl" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../top/svec/top_tdc.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top_tdc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="top_tdc" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="fgg900" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_tdc_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="top_tdc_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_tdc_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="top_tdc_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="svec-tdc-fmc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-07-18T19:43:10" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="45427D10D2FF965F3239A68B42785882" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <libraries/>
+
+  <files>
+    <file xil_pn:name="../../top/svec/svec_tdc.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/mem_core/blk_mem_gen_v6_1.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/mem_core/blk_mem_gen_v6_2.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/mem_core/blk_mem_gen_v6_3.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../top/svec/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+    </file>
+    <file xil_pn:name="../../top/svec/sdb_meta_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    </file>
+    <file xil_pn:name="../../top/svec/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+    </file>
+    <file xil_pn:name="../../rtl/clks_rsts_manager.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
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--- a/hdl/syn/svec/top_tdc.bin
+++ b/hdl/syn/svec/top_tdc.bin
--- a/hdl/syn/svec/top_tdc.twr
+++ b/hdl/syn/svec/top_tdc.twr
--- a/hdl/syn/svec/top_tdc_summary.html
+++ b/hdl/syn/svec/top_tdc_summary.html
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>top_tdc Project Status</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>svec-tdc-fmc.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+<TD> No Errors </TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>top_tdc</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>New</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc6slx150t-3fgg900</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD>&nbsp;</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fmc-tdc/hdl/syn/svec\top_tdc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Oct 2 16:35:12 2013</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 10/02/2013 - 19:12:58</center>
+</BODY></HTML>
\ No newline at end of file
--- a/hdl/testbench/spec/acam_data_model.vhd
+++ b/hdl/testbench/spec/acam_data_model.vhd
+-- Created by : G. Penacoba
+-- Creation Date: June 2011
+-- Description: reproduced roughly the functionality of the acam:
+--              handles the FIFO and the data communication handshake
+-- Modified by:
+-- Modification Date:
+-- Modification consisted on:
+
+
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity acam_data_model is
+    port(
+        start01_i               : in std_logic_vector(16 downto 0);
+        timestamp_for_fifo1     : in std_logic_vector(27 downto 0);
+        timestamp_for_fifo2     : in std_logic_vector(27 downto 0);
+
+        address_i               : in std_logic_vector(3 downto 0);
+        cs_n_i                  : in std_logic;
+        oe_n_i                  : in std_logic;
+        rd_n_i                  : in std_logic;
+        wr_n_i                  : in std_logic;
+       
+        data_bus_o              : out std_logic_vector(27 downto 0);
+        ef1_o                   : out std_logic;
+        ef2_o                   : out std_logic;
+        lf1_o                   : out std_logic;
+        lf2_o                   : out std_logic
+    );
+end acam_data_model;
+
+architecture behavioral of acam_data_model is
+
+    component acam_fifo_model
+    generic(
+        size                : integer;
+        full_threshold      : integer;
+        empty_threshold     : integer
+    );
+    port(
+        data_input          : in std_logic_vector(27 downto 0);
+        rd_fifo             : in std_logic;
+        
+        data_output         : out std_logic_vector(27 downto 0);
+        empty               : out std_logic;
+        full                : out std_logic
+    );
+    end component;
+
+constant ts_ad                  : time:= 2000 ps;       -- minimum address setup time
+constant th_ad                  : time:= 0 ps;          -- minimum address hold time
+constant tpw_rl                 : time:= 6000 ps;       -- minimum read low time
+constant tpw_rh                 : time:= 6000 ps;       -- minimum read high time
+constant tpw_wl                 : time:= 6000 ps;       -- minimum write low time
+constant tpw_wh                 : time:= 6000 ps;       -- minimum write high time
+constant tv_dr                  : time:= 11800 ps;      -- maximum read data valid time
+constant th_dr                  : time:= 4000 ps;       -- minimum read data hold time
+constant ts_dw                  : time:= 5000 ps;       -- minimum write data setup time
+constant th_dw                  : time:= 4000 ps;       -- minimum write data hold time
+constant ts_csn                 : time:= 0 ps;          -- minimum chip select setup time
+constant th_csn                 : time:= 0 ps;          -- minimum chip select hold time
+constant ts_ef                  : time:= 11800 ps;      -- maximum empty flag set time
+
+signal address                  : std_logic_vector(3 downto 0);
+signal cs_n                     : std_logic;
+signal oe_n                     : std_logic;
+signal rd_n                     : std_logic;
+signal wr_n                     : std_logic;
+       
+signal data_bus                 : std_logic_vector(27 downto 0):= (others =>'Z');
+signal ef1                      : std_logic;
+signal ef2                      : std_logic;
+signal lf1                      : std_logic;
+signal lf2                      : std_logic;
+
+signal address_change_time      : time:= 0 ps;
+signal data_change_time         : time:= 0 ps;
+signal cs_falling_time          : time:= 0 ps;
+signal cs_rising_time           : time:= 0 ps;
+signal rd_falling_time          : time:= 0 ps;
+signal rd_rising_time           : time:= 0 ps;
+signal wr_falling_time          : time:= 0 ps;
+signal wr_rising_time           : time:= 0 ps;
+
+signal start01                  : std_logic_vector(16 downto 0);
+signal data_for_bus             : std_logic_vector(27 downto 0);
+signal data_from_fifo1          : std_logic_vector(27 downto 0);
+signal data_from_fifo2          : std_logic_vector(27 downto 0);
+signal rd_fifo1                 : std_logic;
+signal rd_fifo2                 : std_logic;
+
+begin
+
+    read: process
+    begin
+        wait until rd_n ='0';
+        if cs_n ='0' then
+            wait for tv_dr;
+            data_bus        <= data_for_bus;
+        end if;
+
+        wait until rd_n ='1';
+        if cs_n ='0' then
+            wait for th_dr;
+            data_bus        <= (others =>'Z');
+        end if;
+    end process;
+    
+    data_mux: process(address, data_from_fifo1, data_from_fifo2, start01, rd_n, cs_n)
+    begin
+    case address is
+        when x"8" =>
+            data_for_bus        <= data_from_fifo1;
+
+            if rd_n ='0' and cs_n ='0' then
+                rd_fifo1            <= '1';
+                rd_fifo2            <= '0';
+            else
+                rd_fifo1            <= '0';
+                rd_fifo2            <= '0';
+            end if;
+        
+        when x"9" =>
+            data_for_bus        <= data_from_fifo2;
+
+            if rd_n ='0' and cs_n ='0' then
+                rd_fifo1            <= '0';
+                rd_fifo2            <= '1';
+            else
+                rd_fifo1            <= '0';
+                rd_fifo2            <= '0';
+            end if;
+        
+        when x"A" =>
+            data_for_bus        <= "00000000000" & start01;
+
+            rd_fifo1            <= '0';
+            rd_fifo2            <= '0';
+
+        when others =>
+            data_for_bus        <= (others => 'Z');
+
+            rd_fifo1            <= '0';
+            rd_fifo2            <= '0';
+        end case;
+    end process;
+
+    interface_fifo1: acam_fifo_model
+    generic map(
+        size                => 256,
+        full_threshold      => 10,
+        empty_threshold     => 1
+    )
+    port map(
+        data_input          => timestamp_for_fifo1,
+        rd_fifo             => rd_fifo1,
+        
+        data_output         => data_from_fifo1,
+        empty               => ef1,
+        full                => lf1
+    );
+
+    interface_fifo2: acam_fifo_model
+    generic map(
+        size                => 256,
+        full_threshold      => 10,
+        empty_threshold     => 1
+    )
+    port map(
+        data_input          => timestamp_for_fifo2,
+        rd_fifo             => rd_fifo2,
+        
+        data_output         => data_from_fifo2,
+        empty               => ef2,
+        full                => lf2
+    );
+
+    start01                 <= start01_i;
+    address                 <= address_i;
+    cs_n                    <= cs_n_i;
+    oe_n                    <= oe_n_i;
+    rd_n                    <= rd_n_i;
+    wr_n                    <= wr_n_i;
+       
+    data_bus_o              <= data_bus;
+    ef1_o                   <= ef1;
+    ef2_o                   <= ef2;
+    lf1_o                   <= lf1;
+    lf2_o                   <= lf2;
+
+    address_timing: process(address)
+    begin
+        address_change_time         <= now;
+    end process;
+    
+    data_timing: process(address)
+    begin
+        data_change_time            <= now;
+    end process;
+    
+    read_timing: process(rd_n)
+    begin
+        if falling_edge(rd_n) then
+            rd_falling_time         <= now;
+        end if;
+        if rising_edge(rd_n) then
+            rd_rising_time          <= now;
+        end if;
+    end process;
+    
+    write_timing: process(wr_n)
+    begin
+        if falling_edge(wr_n) then
+            wr_falling_time         <= now;
+        end if;
+        if rising_edge(wr_n) then
+            wr_rising_time          <= now;
+        end if;
+    end process;
+    
+    chip_select_timing: process(cs_n)
+    begin
+        if falling_edge(cs_n) then
+            cs_falling_time         <= now;
+        end if;
+        if rising_edge(cs_n) then
+            cs_rising_time          <= now;
+        end if;
+    end process;
+    
+    reporting_read_times: process(rd_falling_time, rd_rising_time)
+    begin
+        if rd_rising_time - rd_falling_time < tpw_rl 
+        and rd_rising_time - rd_falling_time > 0 ps
+        and now /= 0 ps then
+            report LF & " #### Timing error in read signal when reading: minimum low time not respected" & LF
+            severity warning;
+        end if;
+        
+        if rd_falling_time - rd_rising_time < tpw_rh 
+        and rd_falling_time - rd_rising_time > 0 ps
+        and now /= 0 ps then
+            report LF & " #### Timing error in read signal when reading: minimum high time not respected" & LF
+            severity warning;
+        end if;
+    end process;
+        
+    reporting_write_times: process(wr_falling_time, wr_rising_time)
+    begin
+        if wr_rising_time - wr_falling_time < tpw_wl 
+        and wr_rising_time - wr_falling_time > 0 ps
+        and now /= 0 ps then
+            report LF & " #### Timing error in read signal when writing: minimum low time not respected" & LF
+            severity warning;
+        end if;
+        
+        if wr_falling_time - wr_rising_time < tpw_wh 
+        and wr_falling_time - wr_rising_time > 0 ps
+        and now /= 0 ps then
+            report " #### Timing error in read signal when writing: minimum high time not respected" & LF
+            severity warning;
+        end if;
+    end process;
+        
+    reporting_setup_rd: process(rd_falling_time)
+    begin
+        if rd_falling_time - address_change_time < ts_ad and now /= 0 ps then
+            report LF & " #### Timing error in address bus when reading: minimum setup time not respected" & LF
+            severity warning;
+        end if;
+        if rd_falling_time - cs_falling_time < ts_csn and now /= 0 ps then
+            report LF & " #### Timing error in chip select signal when reading: minimum setup time not respected" & LF
+            severity warning;
+        end if;
+    end process;
+    
+    reporting_setup_wr: process(wr_falling_time)
+    begin
+        if wr_falling_time - address_change_time < ts_ad and now /= 0 ps then
+            report LF & " #### Timing error in address bus when writing: minimum setup time not respected" & LF
+            severity warning;
+        end if;
+        if wr_falling_time - cs_falling_time < ts_csn then
+            report LF & " #### Timing error in chip select signal when writing: minimum setup time not respected" & LF
+            severity warning;
+        end if;
+    end process;
+    
+    reporting_hold_ad: process(address_change_time)
+    begin
+        if address_change_time - rd_rising_time < th_ad and now /= 0 ps then
+            report LF & " #### Timing error in address bus when reading: minimum hold time not respected" & LF
+            severity warning;
+        end if;
+        if address_change_time - wr_rising_time < th_ad and now /= 0 ps then
+            report LF & " #### Timing error in address bus when writing: minimum hold time not respected" & LF
+            severity warning;
+        end if;
+    end process;
+    
+    reporting_hold_cs: process(cs_rising_time)
+    begin
+        if cs_rising_time - rd_rising_time < th_csn and now /= 0 ps then
+            report LF & " #### Timing error in chip select signal when reading: minimum hold time not respected" & LF
+            severity warning;
+        end if;
+        if cs_rising_time - wr_rising_time < th_csn and now /= 0 ps then
+            report LF & " #### Timing error in chip select signal when writing: minimum hold time not respected" & LF
+            severity warning;
+        end if;
+    end process;
+    
+    reporting_data_setup_wr: process(wr_rising_time)
+    begin
+        if  wr_rising_time - data_change_time < ts_dw and now /= 0 ps then
+            report LF & " #### Timing error in data bus when writing: minimum setup time not respected" & LF
+            severity warning;
+        end if;
+    end process;
+    
+    reporting_data_hold_wr: process(data_change_time)
+    begin
+        if  data_change_time - wr_rising_time < th_dw and now /= 0 ps then
+            report LF & " #### Timing error in data bus when writing: minimum hold time not respected" & LF
+            severity warning;
+        end if;
+    end process;
+    
+end behavioral;
--- a/hdl/testbench/spec/acam_fifo_model.vhd
+++ b/hdl/testbench/spec/acam_fifo_model.vhd
+-- Created by : G. Penacoba
+-- Creation Date: June 2011
+-- Description: reproduces roughly the functionality of the acam:
+--              handles the FIFO and the data communication handshake
+-- Modified by:
+-- Modification Date:
+-- Modification consisted on:
+
+
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity acam_fifo_model is
+    generic(
+        size                : integer;
+        full_threshold      : integer;
+        empty_threshold     : integer
+    );
+    port(
+        data_input          : in std_logic_vector(27 downto 0);
+        rd_fifo             : in std_logic;
+        
+        data_output         : out std_logic_vector(27 downto 0);
+        empty               : out std_logic;
+        full                : out std_logic
+    );
+end acam_fifo_model;
+
+architecture behavioral of acam_fifo_model is
+
+constant ts_ef              : time:= 11800 ps;      -- maximum empty flag set time
+
+subtype index               is natural range size-1 downto 0;
+subtype memory_cell         is std_logic_vector(27 downto 0);
+type memory_block           is array (natural range size-1 downto 0) of memory_cell;
+
+signal fifo                 : memory_block;
+signal wr_pointer           : index:= 0;
+signal rd_pointer           : index:= 0;
+signal level                : index:= 0;
+
+begin
+
+
+    writing: process(data_input)
+    begin
+        if now /= 0 ps then
+            fifo(wr_pointer)        <= data_input;
+            if wr_pointer = size-1 then
+                wr_pointer          <= 0;
+            else
+                wr_pointer          <= wr_pointer + 1;
+            end if;
+        end if;
+    end process;
+    
+    reading: process(rd_fifo)
+    begin
+        if rising_edge(rd_fifo) then
+            data_output             <= fifo(rd_pointer);
+
+            if rd_pointer = size-1 then
+                rd_pointer          <= 0 after ts_ef;
+            else
+                rd_pointer          <= rd_pointer + 1 after ts_ef;
+            end if;
+
+        end if;
+        
+--        if falling_edge(rd_fifo) then
+--            if rd_pointer = size-1 then
+--                rd_pointer          <= 0;
+--            else
+--                rd_pointer          <= rd_pointer + 1;
+--            end if;
+--        end if;
+    end process;
+    
+    flags: process(level)
+    begin
+        if level > full_threshold then
+            full                <= '1';
+        else
+            full                <= '0';
+        end if;
+        if level < empty_threshold then
+            empty               <= '1';
+        else
+            empty               <= '0';
+        end if;
+    end process;
+
+    filling_level: process(rd_pointer, wr_pointer)
+    begin
+        if wr_pointer >= rd_pointer then
+            level               <= wr_pointer - rd_pointer;
+        else
+            level               <= wr_pointer + 256 - rd_pointer;
+        end if;
+        
+    end process;
+    
+--    process(level)
+--    begin
+--        report  " filling level " & integer'image(level) & LF &
+--                " rd_pointer " & integer'image(rd_pointer) & LF &
+--                " wr_pointer " & integer'image(wr_pointer) & LF;
+--    end process;
+    
+    corruption_reporting_reading: process(rd_pointer)
+    begin
+        if now /= 0 ps then
+            if rd_pointer = wr_pointer then
+                report LF & " #### Interface FIFO is empty: no further reading should be performed" & LF
+                severity warning;
+            end if;
+        end if;
+    end process;
+                
+    corruption_reporting_writing: process(wr_pointer)
+    begin
+        if now /= 0 ps then
+            if rd_pointer = wr_pointer then
+                report LF & " #### Interface FIFO is full: no further writing should be performed" & LF
+                severity warning;
+            end if;
+        end if;
+    end process;
+
+end behavioral;
+
+
+
+
+
+
+
+
+
+
--- a/hdl/testbench/spec/acam_model.vhd
+++ b/hdl/testbench/spec/acam_model.vhd
+-- Creation Date: May 2011
+-- Description: reproduced roughly the functionality of the acam:
+-- Modified by:
+-- Modification Date:
+-- Modification consisted on:
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity acam_model is
+    generic(
+        start_retrig_period     : time:= 3200 ns;
+        refclk_period           : time:= 32 ns
+    );
+    port(
+        tstart_i                : in std_logic;
+        tstop1_i                : in std_logic;
+        tstop2_i                : in std_logic;
+        tstop3_i                : in std_logic;
+        tstop4_i                : in std_logic;
+        tstop5_i                : in std_logic;
+        startdis_i              : in std_logic;
+        stopdis_i               : in std_logic;
+
+        int_flag_o              : out std_logic;
+        err_flag_o              : out std_logic;
+
+        address_i               : in std_logic_vector(3 downto 0);
+        cs_n_i                  : in std_logic;
+        oe_n_i                  : in std_logic;
+        rd_n_i                  : in std_logic;
+        wr_n_i                  : in std_logic;
+       
+        data_bus_io             : inout std_logic_vector(27 downto 0);
+        ef1_o                   : out std_logic;
+        ef2_o                   : out std_logic;
+        lf1_o                   : out std_logic;
+        lf2_o                   : out std_logic
+    );
+end acam_model;
+
+architecture behavioral of acam_model is
+
+    component acam_timing_model
+    generic(
+        refclk_period           : time:= 32 ns;
+        start_retrig_period     : time:= 3200 ns
+    );
+    port(
+        tstart_i                : in std_logic;
+        tstop1_i                : in std_logic;
+        tstop2_i                : in std_logic;
+        tstop3_i                : in std_logic;
+        tstop4_i                : in std_logic;
+        tstop5_i                : in std_logic;
+        startdis_i              : in std_logic;
+        stopdis_i               : in std_logic;
+        
+        err_flag_o              : out std_logic;
+        int_flag_o              : out std_logic;
+        start01_o               : out std_logic_vector(16 downto 0);
+        timestamp_for_fifo1     : out std_logic_vector(27 downto 0);
+        timestamp_for_fifo2     : out std_logic_vector(27 downto 0)
+    );
+    end component;
+
+    component acam_data_model
+    port(
+        start01_i               : in std_logic_vector(16 downto 0);
+        timestamp_for_fifo1     : in std_logic_vector(27 downto 0);
+        timestamp_for_fifo2     : in std_logic_vector(27 downto 0);
+
+        address_i               : in std_logic_vector(3 downto 0);
+        cs_n_i                  : in std_logic;
+        oe_n_i                  : in std_logic;
+        rd_n_i                  : in std_logic;
+        wr_n_i                  : in std_logic;
+       
+        data_bus_o              : out std_logic_vector(27 downto 0);
+        ef1_o                   : out std_logic;
+        ef2_o                   : out std_logic;
+        lf1_o                   : out std_logic;
+        lf2_o                   : out std_logic
+    );
+    end component;
+
+signal timestamp_for_fifo1      : std_logic_vector(27 downto 0);
+signal timestamp_for_fifo2      : std_logic_vector(27 downto 0);
+signal start01                  : std_logic_vector(16 downto 0);
+
+
+begin
+    
+    timing_block: acam_timing_model
+    generic map(
+        refclk_period           => refclk_period,
+        start_retrig_period     => start_retrig_period
+    )
+    port map(
+        tstart_i                => tstart_i,
+        tstop1_i                => tstop1_i,
+        tstop2_i                => tstop2_i,
+        tstop3_i                => tstop3_i,
+        tstop4_i                => tstop4_i,
+        tstop5_i                => tstop5_i,
+        startdis_i              => startdis_i,
+        stopdis_i               => stopdis_i,
+        
+        err_flag_o              => err_flag_o,
+        int_flag_o              => int_flag_o,
+        start01_o               => start01,
+        timestamp_for_fifo1     => timestamp_for_fifo1,
+        timestamp_for_fifo2     => timestamp_for_fifo2
+    );
+    
+    data_block: acam_data_model
+    port map(
+        start01_i               => start01,
+        timestamp_for_fifo1     => timestamp_for_fifo1,
+        timestamp_for_fifo2     => timestamp_for_fifo2,
+        
+        address_i               => address_i,
+        cs_n_i                  => cs_n_i,
+        oe_n_i                  => oe_n_i,
+        rd_n_i                  => rd_n_i,
+        wr_n_i                  => wr_n_i,
+        
+        data_bus_o              => data_bus_io,
+        ef1_o                   => ef1_o,
+        ef2_o                   => ef2_o,
+        lf1_o                   => lf1_o,
+        lf2_o                   => lf2_o
+    );
+        
+
+end behavioral;
+
--- a/hdl/testbench/spec/acam_timing_model.vhd
+++ b/hdl/testbench/spec/acam_timing_model.vhd
+-- Created by : G. Penacoba
+-- Creation Date: May 2011
+-- Description: reproduced roughly the functionality of the acam:
+--              measures the time between input pulses.
+-- Modified by:
+-- Modification Date:
+-- Modification consisted on:
+
+
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity acam_timing_model is
+    generic(
+        refclk_period           : time:= 32 ns;
+        start_retrig_period     : time:= 3200 ns
+    );
+    port(
+        tstart_i                : in std_logic;
+        tstop1_i                : in std_logic;
+        tstop2_i                : in std_logic;
+        tstop3_i                : in std_logic;
+        tstop4_i                : in std_logic;
+        tstop5_i                : in std_logic;
+        startdis_i              : in std_logic;
+        stopdis_i               : in std_logic;
+        
+        err_flag_o              : out std_logic;
+        int_flag_o              : out std_logic;
+        start01_o               : out std_logic_vector(16 downto 0);
+        timestamp_for_fifo1     : out std_logic_vector(27 downto 0);
+        timestamp_for_fifo2     : out std_logic_vector(27 downto 0)
+    );
+end acam_timing_model;
+
+architecture behavioral of acam_timing_model is
+
+constant resolution       : time:= 81 ps;
+
+
+signal tstart           : std_logic;
+signal tstop1           : std_logic;
+signal tstop2           : std_logic;
+signal tstop3           : std_logic;
+signal tstop4           : std_logic;
+signal tstop5           : std_logic;
+
+signal startdis         : std_logic;
+signal stopdis          : std_logic;
+signal intflag          : std_logic;
+signal start01_reg      : std_logic_vector(16 downto 0);
+
+signal start01          : time:= 0 ps;
+
+signal start_trig       : time:= 0 ps;
+signal stop1_trig       : time:= 0 ps;
+signal stop2_trig       : time:= 0 ps;
+signal stop3_trig       : time:= 0 ps;
+signal stop4_trig       : time:= 0 ps;
+signal stop5_trig       : time:= 0 ps;
+
+signal stop1            : time:= 0 ps;
+signal stop2            : time:= 0 ps;
+signal stop3            : time:= 0 ps;
+signal stop4            : time:= 0 ps;
+signal stop5            : time:= 0 ps;
+
+signal start_nb1        : integer:=0;
+signal start_nb2        : integer:=0;
+signal start_nb3        : integer:=0;
+signal start_nb4        : integer:=0;
+signal start_nb5        : integer:=0;
+
+signal start_retrig_nb  : integer:=0;
+signal start_retrig_p   : std_logic;
+
+begin
+    
+    listening: process (tstart, tstop1, tstop2, tstop3, tstop4, tstop5)
+    begin
+        if rising_edge(tstart) then
+            if startdis ='0' then
+                start_trig          <= now;
+            end if;
+        end if;
+        if rising_edge(tstop1) then
+            if stopdis ='0' then
+                stop1_trig          <= now;
+            end if;
+        end if;
+        if rising_edge(tstop2) then
+            if stopdis ='0' then
+                stop2_trig          <= now;
+            end if;
+        end if;
+        if rising_edge(tstop3) then
+            if stopdis ='0' then
+                stop3_trig          <= now;
+            end if;
+        end if;
+        if rising_edge(tstop4) then
+            if stopdis ='0' then
+                stop4_trig          <= now;
+            end if;
+        end if;
+        if rising_edge(tstop5) then
+            if stopdis ='0' then
+                stop5_trig          <= now;
+            end if;
+        end if;
+    end process;
+    
+    measuring1: process(stop1_trig)
+    begin
+        if start_retrig_nb > 1 then
+            stop1           <= (stop1_trig-start_trig-start01)-((start_retrig_nb-1)*start_retrig_period);
+        elsif start_retrig_nb = 1 then
+            stop1           <= (stop1_trig-start_trig-start01);
+        else
+            stop1           <= (stop1_trig-start_trig);
+        end if;        
+        start_nb1       <= start_retrig_nb mod 256;
+    end process;
+
+    measuring2: process(stop2_trig)
+    begin
+        if start_retrig_nb > 1 then
+            stop2           <= (stop2_trig-start_trig-start01)-((start_retrig_nb-1)*start_retrig_period);
+        elsif start_retrig_nb = 1 then
+            stop2           <= (stop2_trig-start_trig-start01);
+        else
+            stop2           <= (stop2_trig-start_trig);
+        end if;        
+        start_nb2       <= start_retrig_nb mod 256;
+    end process;
+
+    measuring3: process(stop3_trig)
+    begin
+        if start_retrig_nb > 1 then
+            stop3           <= (stop3_trig-start_trig-start01)-((start_retrig_nb-1)*start_retrig_period);
+        elsif start_retrig_nb = 1 then
+            stop3           <= (stop3_trig-start_trig-start01);
+        else
+            stop3           <= (stop3_trig-start_trig);
+        end if;        
+        start_nb3       <= start_retrig_nb mod 256;
+    end process;
+
+    measuring4: process(stop4_trig)
+    begin
+        if start_retrig_nb > 1 then
+            stop4           <= (stop4_trig-start_trig-start01)-((start_retrig_nb-1)*start_retrig_period);
+        elsif start_retrig_nb = 1 then
+            stop4           <= (stop4_trig-start_trig-start01);
+        else
+            stop4           <= (stop4_trig-start_trig);
+        end if;        
+        start_nb4       <= start_retrig_nb mod 256;
+    end process;
+
+    measuring5: process(stop5_trig)
+    begin
+        if start_retrig_nb > 1 then
+            stop5           <= (stop5_trig-start_trig-start01)-((start_retrig_nb-1)*start_retrig_period);
+        elsif start_retrig_nb = 1 then
+            stop5           <= (stop5_trig-start_trig-start01);
+        else
+            stop5           <= (stop5_trig-start_trig);
+        end if;        
+        start_nb5       <= start_retrig_nb mod 256;
+    end process;
+
+    measuring_start01: process(start_retrig_p)
+    begin
+        if rising_edge(start_retrig_p) then
+            if start_retrig_nb = 0 then
+                start01            <= now - start_trig;
+            end if;
+        end if;
+    end process;
+
+    writing_fifo1: process (tstop1, tstop2, tstop3, tstop4)
+    begin
+        if falling_edge(tstop1) then
+            timestamp_for_fifo1(27 downto 26)       <= "00";
+            timestamp_for_fifo1(25 downto 18)       <= std_logic_vector(to_unsigned(start_nb1,8));
+            timestamp_for_fifo1(17)                 <= '1';
+            timestamp_for_fifo1(16 downto 0)        <= std_logic_vector(to_unsigned(stop1/resolution,17));
+            start01_reg                             <= std_logic_vector(to_unsigned(start01/resolution,17));
+            report " Timestamp for interface FIFO 1:" & LF &
+                    "===============================" & LF &
+                    "Channel 1" & LF &
+                    "Start number: " & integer'image(start_nb1) & LF &
+                    "Time Interval: " & integer'image(stop1/resolution) & LF &
+                    "Start01: " & integer'image(start01/resolution) & LF;
+        end if;
+
+        if falling_edge(tstop2) then
+            timestamp_for_fifo1(27 downto 26)       <= "01";
+            timestamp_for_fifo1(25 downto 18)       <= std_logic_vector(to_unsigned(start_nb2,8));
+            timestamp_for_fifo1(17)                 <= '1';
+            timestamp_for_fifo1(16 downto 0)        <= std_logic_vector(to_unsigned(stop2/resolution,17));
+            start01_reg                             <= std_logic_vector(to_unsigned(start01/resolution,17));
+            report " Timestamp for interface FIFO 1:" & LF &
+                    "===============================" & LF &
+                    "Channel 2" & LF &
+                    "Start number: " & integer'image(start_nb2) & LF &
+                    "Time Interval: " & integer'image(stop2/resolution) & LF &
+                    "Start01: " & integer'image(start01/resolution) & LF;
+        end if;
+
+        if falling_edge(tstop3) then
+            timestamp_for_fifo1(27 downto 26)       <= "10";
+            timestamp_for_fifo1(25 downto 18)       <= std_logic_vector(to_unsigned(start_nb3,8));
+            timestamp_for_fifo1(17)                 <= '1';
+            timestamp_for_fifo1(16 downto 0)        <= std_logic_vector(to_unsigned(stop3/resolution,17));
+            start01_reg                             <= std_logic_vector(to_unsigned(start01/resolution,17));
+            report " Timestamp for interface FIFO 1:" & LF &
+                    "===============================" & LF &
+                    "Channel 3" & LF &
+                    "Start number: " & integer'image(start_nb3) & LF &
+                    "Time Interval: " & integer'image(stop3/resolution) & LF &
+                    "Start01: " & integer'image(start01/resolution) & LF;
+        end if;
+
+        if falling_edge(tstop4) then
+            timestamp_for_fifo1(27 downto 26)       <= "11";
+            timestamp_for_fifo1(25 downto 18)       <= std_logic_vector(to_unsigned(start_nb4,8));
+            timestamp_for_fifo1(17)                 <= '1';
+            timestamp_for_fifo1(16 downto 0)        <= std_logic_vector(to_unsigned(stop4/resolution,17));
+            start01_reg                             <= std_logic_vector(to_unsigned(start01/resolution,17));
+            report " Timestamp for interface FIFO 1:" & LF &
+                    "===============================" & LF &
+                    "Channel 4" & LF &
+                    "Start number: " & integer'image(start_nb4) & LF &
+                    "Time Interval: " & integer'image(stop4/resolution) & LF &
+                    "Start01: " & integer'image(start01/resolution) & LF;
+        end if;
+    end process;
+
+    writing_fifo2: process (tstop5)
+    begin
+        if falling_edge(tstop5) then
+            timestamp_for_fifo2(27 downto 26)       <= "00";
+            timestamp_for_fifo2(25 downto 18)       <= std_logic_vector(to_unsigned(start_nb5,8));
+            timestamp_for_fifo2(17)                 <= '1';
+            timestamp_for_fifo2(16 downto 0)        <= std_logic_vector(to_unsigned(stop5/resolution,17));
+            start01_reg                             <= std_logic_vector(to_unsigned(start01/resolution,17));
+            report " Timestamp for interface FIFO 2:" & LF &
+                    "===============================" & LF &
+                    "Channel 5" & LF &
+                    "Start number: " & integer'image(start_nb5) & LF &
+                    "Time Interval: " & integer'image(stop5/resolution) & LF &
+                    "Start01: " & integer'image(start01/resolution) & LF;
+        end if;
+    end process;
+
+    start_retrigger_pulses: process
+    begin
+        start_retrig_p      <= '0' after 333 ps;
+        wait for start_retrig_period/4;
+        start_retrig_p      <= '1' after 333 ps;
+        wait for start_retrig_period/4;
+        start_retrig_p      <= '0' after 333 ps;
+        wait for start_retrig_period/2;
+    end process;
+    
+    start_nb_counter: process(tstart, start_retrig_p)
+    begin
+        if rising_edge(tstart) then
+            start_retrig_nb     <= 0;
+        elsif rising_edge(start_retrig_p) then
+            start_retrig_nb     <= start_retrig_nb + 1;
+        end if;
+    end process;
+    
+    interrupt_flag: process(start_retrig_nb)
+    begin
+        if (start_retrig_nb mod 256) > 127 then
+            intflag             <= '1';
+        else
+            intflag             <= '0';
+        end if;
+    end process;
+
+    tstart                      <= tstart_i;
+    tstop1                      <= tstop1_i;
+    tstop2                      <= tstop2_i;
+    tstop3                      <= tstop3_i;
+    tstop4                      <= tstop4_i;
+    tstop5                      <= tstop5_i;
+    
+    startdis                    <= startdis_i;
+    stopdis                     <= stopdis_i;
+    
+    int_flag_o                  <= intflag;
+    
+    start01_o                   <= start01_reg;
+
+end behavioral;
+
+        
--- a/hdl/testbench/spec/gnum_model/cmd_router.vhd
+++ b/hdl/testbench/spec/gnum_model/cmd_router.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use std.textio.all;
+
+--library std_developerskit;
+--use std_developerskit.std_iopak.all;
+
+use work.util.all;
+use work.textutil.all;
+
+
+--==========================================================================--
+--
+-- *MODULE << cmd_router >>
+--
+-- *Description : This module routes commands to all command driven modules
+--               in the simulation. It instanciates N_FILES instances of
+--               cmd_router1 and agregates the outputs to control N_BFM BFMs.
+--
+-- *History: M. Alford (originaly created 1993 with subsequent updates)
+--
+--==========================================================================--
+
+--==========================================================================--
+-- Operation
+--
+-- This module opens a text file and passes commands to individual vhdl models.
+-- 
+--==========================================================================--
+
+entity cmd_router is
+	generic( N_BFM      : integer := 8;
+	         N_FILES    : integer := 3;
+	         FIFO_DEPTH : integer := 16;
+	         STRING_MAX : integer := 256
+	       );
+	port( CMD                : out    string(1 to STRING_MAX);
+	      CMD_REQ            : out    bit_vector(N_BFM-1 downto 0);
+	      CMD_ACK            : in     bit_vector(N_BFM-1 downto 0);
+	      CMD_ERR            : in     bit_vector(N_BFM-1 downto 0);
+	      CMD_CLOCK_EN       : out    boolean
+	    );
+end cmd_router;
+
+architecture MODEL of cmd_router is
+
+component cmd_router1
+	generic( N_BFM      : integer := 8;
+	         FIFO_DEPTH : integer := 8;
+	         STRING_MAX : integer := 256;
+	         FILENAME   : string :="cmdfile.vec"
+	       );
+	port( CMD                : out    STRING(1 to STRING_MAX);
+	      CMD_REQ            : out    bit_vector(N_BFM-1 downto 0);
+	      CMD_ACK            : in     bit_vector(N_BFM-1 downto 0);
+	      CMD_ERR            : in     bit_vector(N_BFM-1 downto 0);
+	      CMD_CLOCK_EN       : out    boolean;
+	      CMD_DONE_IN        : in     boolean;
+	      CMD_DONE_OUT       : out    boolean
+	    );
+end component; -- cmd_router1
+
+
+	type FILE_ARRAY     is array (natural range <>) of string(1 to 31);
+	type CMD_ARRAY      is array (natural range <>) of string(CMD'range);
+	type CMD_REQ_ARRAY  is array (natural range <>) of bit_vector(N_BFM-1 downto 0);
+	type integer_vector is array (natural range <>) of integer; 
+	type boolean_vector is array (natural range <>) of boolean; 
+
+	constant MAX_FILES         : integer := 10;
+	constant FILENAMES         : FILE_ARRAY(0 to MAX_FILES-1) := (others=>"data_vectors/atdc_test_cmd0.vec");
+--    , "data_vectors/acam_test_cmd1.vec");
+--	                                                               "data_vectors/acam_test_cmd2.vec", "data_vectors/acam_test_cmd3.vec", 
+--	                                                               "data_vectors/acam_test_cmd4.vec", "data_vectors/acam_test_cmd5.vec", 
+--	                                                               "data_vectors/acam_test_cmd6.vec", "data_vectors/acam_test_cmd7.vec", 
+--	                                                               "data_vectors/acam_test_cmd8.vec", "data_vectors/acam_test_cmd9.vec" );
+
+	signal	CMDo               : CMD_ARRAY(N_FILES-1 downto 0);
+	signal	REQ                : bit_vector(CMD_REQ'range);
+	signal	CMD_REQo           : CMD_REQ_ARRAY(N_FILES-1 downto 0);
+	signal	CMD_ACKi           : CMD_REQ_ARRAY(N_FILES-1 downto 0);
+	signal	CMD_ACK_MASK       : CMD_REQ_ARRAY(N_FILES-1 downto 0); -- 1 bit_vector per file to mask CMD_ACK
+	signal	CMD_CLOCK_ENo      : boolean_vector(N_FILES-1 downto 0);
+	signal	CMD_ALL_DONE       : boolean;
+	signal	CMD_DONE_OUT       : boolean_vector(N_FILES-1 downto 0);
+
+    function or_reduce(ARG: bit_vector) return bit is
+	variable result: bit;
+    begin
+		result := '0';
+		for i in ARG'range loop
+		    result := result or ARG(i);
+		end loop;
+		return result;
+    end;
+
+    function or_reduce(ARG: boolean_vector) return boolean is
+	variable result: boolean;
+    begin
+		result := FALSE;
+		for i in ARG'range loop
+		    result := result or ARG(i);
+		end loop;
+		return result;
+    end;
+
+    function and_reduce(ARG: boolean_vector) return boolean is
+	variable result: boolean;
+    begin
+		result := TRUE;
+		for i in ARG'range loop
+		    result := result and ARG(i);
+		end loop;
+		return result;
+    end;
+
+
+begin
+
+-----------------------------------------------------------------------------
+-- Instanciate 1 cmd_router1 per file to be processed
+-----------------------------------------------------------------------------
+	G1 : for i in 0 to N_FILES-1 generate
+		U1 : cmd_router1
+		generic map
+		    ( N_BFM      => N_BFM,
+		      FIFO_DEPTH => FIFO_DEPTH, 
+		      STRING_MAX => STRING_MAX, 
+		      FILENAME   => FILENAMES(i)
+		    )
+		port map
+		    ( CMD           => CMDo(i), 
+		      CMD_REQ       => CMD_REQo(i), 
+		      CMD_ACK       => CMD_ACKi(i), 
+		      CMD_ERR       => CMD_ERR, 
+		      CMD_CLOCK_EN  => CMD_CLOCK_ENo(i), 
+		      CMD_DONE_IN   => CMD_ALL_DONE, 
+		      CMD_DONE_OUT  => CMD_DONE_OUT(i)
+		    );
+	end generate;
+
+-----------------------------------------------------------------------------
+-- Multiplex the commands from the cmd_router1 modules
+-----------------------------------------------------------------------------
+
+	process
+	variable vDONE : boolean;
+	begin
+		CMD <= (others => '0');
+		wait on CMD_REQo;
+		vDONE := FALSE;
+		while(not vDONE) loop
+		vDONE := TRUE;
+		for i in 0 to N_FILES-1 loop             -- Loop on each file
+			if(or_reduce(CMD_REQo(i)) = '1') then -- this file wants to do a command
+				vDONE := FALSE;
+				--
+				-- if the ACK is already on from another cmd_router1
+				--
+				while(or_reduce(CMD_REQo(i) and CMD_ACK) = '1') loop
+					wait on CMD_ACK;
+				end loop;
+				--
+				-- Do the request
+				--
+				CMD      <= CMDo(i);
+				REQ      <= CMD_REQo(i);
+				--
+				-- Wait for the ACK
+				--
+				wait until(CMD_ACK'event and (or_reduce(CMD_ACK and REQ) = '1'));
+				-- 
+				-- send the ack to the proper file
+				--
+				for j in 0 to N_FILES-1 loop
+					if(i = j) then -- enable this one
+						CMD_ACK_MASK(j) <= CMD_ACK_MASK(j) or REQ;
+					else
+						CMD_ACK_MASK(j) <= CMD_ACK_MASK(j) and not REQ;
+					end if;
+				end loop;
+				--
+				-- Wait for the request to de-assert
+				--
+				while(or_reduce(CMD_REQo(i) and REQ) = '1') loop
+					wait on CMD_REQo;
+				end loop;
+				REQ      <= (others => '0');
+			end if;
+		end loop;
+	end loop;
+	end process;
+
+	process(CMD_ACK, CMD_ACK_MASK)
+	begin
+		for i in 0 to N_FILES-1 loop             -- Loop on each file
+			CMD_ACKi(i) <= CMD_ACK and CMD_ACK_MASK(i);
+		end loop;
+	end process;
+	
+
+	CMD_REQ <= REQ;
+
+	CMD_ALL_DONE <= and_reduce(CMD_DONE_OUT);
+
+	CMD_CLOCK_EN <= CMD_CLOCK_ENo(0);
+
+end MODEL;
+
--- a/hdl/testbench/spec/gnum_model/cmd_router1.vhd
+++ b/hdl/testbench/spec/gnum_model/cmd_router1.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use std.textio.all;
+
+--library std_developerskit;
+--use std_developerskit.std_iopak.all;
+
+use work.util.all;
+use work.textutil.all;
+
+--==========================================================================--
+--
+-- *MODULE << model1 >>
+--
+-- *Description : This module routes commands to all command driven modules
+--               in the simulation.
+--
+-- *History: M. Alford (originaly created 1993 with subsequent updates)
+--
+--==========================================================================--
+
+--==========================================================================--
+-- Operation
+--
+-- This module opens a text file and passes commands to individual vhdl models.
+-- 
+--==========================================================================--
+
+entity cmd_router1 is
+	generic( N_BFM      : integer := 8;
+	         FIFO_DEPTH : integer := 8;
+	         STRING_MAX : integer := 256;
+	         FILENAME   : string :="cmdfile.vec"
+	       );
+	port( CMD                : out    STRING(1 to STRING_MAX);
+	      CMD_REQ            : out    bit_vector(N_BFM-1 downto 0);
+	      CMD_ACK            : in     bit_vector(N_BFM-1 downto 0);
+	      CMD_ERR            : in     bit_vector(N_BFM-1 downto 0);
+	      CMD_CLOCK_EN       : out    boolean;
+	      CMD_DONE_IN        : in     boolean;
+	      CMD_DONE_OUT       : out    boolean
+	    );
+end cmd_router1;
+
+architecture MODEL of cmd_router1 is
+
+
+	type STRING_ARRAY   is array (FIFO_DEPTH-1 downto 0) of STRING(1 to STRING_MAX);
+	type FD_ARRAY       is array (N_BFM-1 downto 0) of STRING_ARRAY;
+	type integer_vector is array (natural range <>) of integer; 
+
+	signal	FD                 : FD_ARRAY;
+	signal  ERR_CNT            : integer;
+	signal	PUSH_PTR           : integer_vector(N_BFM-1 downto 0);
+	signal	POP_PTR            : integer_vector(N_BFM-1 downto 0);
+	signal  SET_CHAN           : std_ulogic;
+	signal  POP_INIT           : std_ulogic;
+	signal	CMD_REQo           : bit_vector(CMD_REQ'range);
+	signal	LINE_NUM           : integer;
+
+begin
+	PUSH_PROCESS : process
+	file FOUT : text open write_mode is "usc.lst";
+
+	file        stim_file   : text open read_mode is FILENAME;
+	file        out_file    : text open write_mode is "STD_OUTPUT";
+
+-------- For VHDL-87
+--	file        stim_file   : text is in FILENAME;
+--	file        out_file    : text is out "STD_OUTPUT";
+
+	variable	input_line  : line;
+	variable	output_line : line;
+	variable	tmp_lout    : line;
+	variable	command     : string(1 to 8);
+	variable	tmp_str     : string(1 to STRING_MAX);
+	variable	input_str   : string(1 to STRING_MAX);
+	variable	i           : integer;
+	variable	CHANNEL     : integer;
+	variable	S_PTR       : integer;
+	variable	vLINE_NUM   : integer;
+	variable	vPUSH_PTR   : integer_vector(N_BFM-1 downto 0);
+	variable	DONE        : boolean;
+	variable	EOS         : integer;
+	variable	ERR         : integer;
+
+
+
+	begin
+
+-----------------------------------------------------------------------------
+-- Main Loop
+-----------------------------------------------------------------------------
+		vLINE_NUM := 0;
+		PUSH_PTR  <= (others => 0);
+		vPUSH_PTR := (others => 0);
+		CHANNEL := 0;
+		CMD_CLOCK_EN <= TRUE;
+		SET_CHAN <= '0';
+		CMD_DONE_OUT <= FALSE;
+		if(POP_INIT /= '1') then
+			wait until(POP_INIT'event and (POP_INIT = '1'));
+		end if;
+		
+		ST_LOOP: while not endfile(stim_file) loop
+			readline(stim_file, input_line);
+			S_PTR := 1;
+			vLINE_NUM := vLINE_NUM + 1;
+			LINE_NUM <= vLINE_NUM;
+
+-- Copy the line
+			input_str := (others => ' ');
+			input_str(1 to 6) := To_Strn(vLINE_NUM, 6);
+			input_str(7 to 8) := string'(": ");
+			input_str(9 to input_line'length+8) := string'(input_line.all);
+			while(input_str(S_PTR) /= ':') loop
+				S_PTR := S_PTR + 1;
+			end loop;
+			S_PTR := S_PTR + 1;
+
+			sget_token(input_str, S_PTR, command);
+
+			SET_CHAN <= '1';
+
+			for j in STRING_MAX downto 1 loop
+				if(input_str(j) /= ' ') then
+					EOS := j;
+					exit;
+				end if;
+			end loop;
+
+
+			---------------------------
+			-- "model" command ?
+			---------------------------
+			if(command(1 to 5) = "model") then
+				sget_int(input_str, S_PTR, i);
+				write(tmp_lout, FILENAME);
+				write(tmp_lout, input_str(1 to EOS));
+				writeline(out_file, tmp_lout);
+				if((i >= N_BFM) or (i < 0)) then
+					CHANNEL := N_BFM-1;
+					write(tmp_lout, string'("ERROR: Invalid Channel "));
+					write(tmp_lout, i);
+					writeline(out_file, tmp_lout);
+				else
+					CHANNEL := i;
+				end if;
+
+			---------------------------
+			-- "sync" command ?
+			---------------------------
+			elsif(command(1 to 4) = "sync") then
+				loop
+					DONE := TRUE;
+					for i in PUSH_PTR'reverse_range loop
+						if((vPUSH_PTR(i) /= POP_PTR(i)) or (CMD_ACK(i) /= '0')) then
+							DONE := FALSE;
+						end if;
+					end loop;
+					if(DONE) then
+						exit;
+					end if;
+					wait on POP_PTR, CMD_ACK;
+				end loop;
+				write(tmp_lout, FILENAME);
+				write(tmp_lout, input_str(1 to EOS));
+				writeline(out_file, tmp_lout);
+
+			---------------------------
+			-- "gsync" and "ckoff" command ?
+			---------------------------
+			elsif((command(1 to 5) = "gsync") or (command(1 to 5) = "ckoff")) then
+write(tmp_lout, FILENAME);
+write(tmp_lout, string'(": entering the gsync command"));
+writeline(out_file, tmp_lout);
+				loop
+					DONE := TRUE;
+					for i in PUSH_PTR'reverse_range loop
+						if((vPUSH_PTR(i) /= POP_PTR(i)) or (CMD_ACK(i) /= '0')) then
+							DONE := FALSE;
+						end if;
+					end loop;
+					if(DONE) then
+						exit;
+					end if;
+					wait on POP_PTR, CMD_ACK;
+				end loop;
+				CMD_DONE_OUT <= TRUE;
+				-- wait for the external CMD_DONE_IN to be done
+				while (not CMD_DONE_IN) loop
+					wait on CMD_DONE_IN;
+				end loop;
+				CMD_DONE_OUT <= FALSE;
+				write(tmp_lout, FILENAME);
+				write(tmp_lout, input_str(1 to EOS));
+				writeline(out_file, tmp_lout);
+				if (command(1 to 5) = "ckoff") then
+					CMD_CLOCK_EN <= FALSE;
+				end if;
+write(tmp_lout, FILENAME);
+write(tmp_lout, string'(": gsync command is DONE"));
+writeline(out_file, tmp_lout);
+
+			--------------------
+			-- ckon
+			--------------------
+			elsif (command(1 to 4) = "ckon") then
+				CMD_CLOCK_EN <= TRUE;
+				write(tmp_lout, FILENAME);
+				write(tmp_lout, input_str(1 to EOS));
+				writeline(out_file, tmp_lout);
+
+			---------------------------
+			-- put the line in the FIFO
+			---------------------------
+			else
+
+
+				FD(CHANNEL)(vPUSH_PTR(CHANNEL)) <= input_str;
+
+				vPUSH_PTR(CHANNEL) := vPUSH_PTR(CHANNEL) + 1;
+
+				if(vPUSH_PTR(CHANNEL) >= FIFO_DEPTH) then
+					vPUSH_PTR(CHANNEL) := 0;
+				end if;
+
+				if(vPUSH_PTR(CHANNEL) = POP_PTR(CHANNEL)) then -- The FIFO is full
+					wait until(POP_PTR'event and (vPUSH_PTR(CHANNEL) /= POP_PTR(CHANNEL)));
+				end if;
+
+				PUSH_PTR(CHANNEL) <= vPUSH_PTR(CHANNEL);
+
+			end if;
+		
+		end loop;
+
+		loop
+			DONE := TRUE;
+			for i in POP_PTR'reverse_range loop
+				if((POP_PTR(i) /= vPUSH_PTR(i)) or (CMD_ACK(i) = '1')) then -- FIFO channel not empty
+					DONE := FALSE;
+				end if;
+			end loop;
+			if(DONE) then
+				exit;
+			end if;
+			wait on CMD_ACK, POP_PTR;
+		end loop;
+
+		CMD_DONE_OUT <= TRUE;
+
+		write(output_line, string'("******************************* Test Finished *******************************"));
+		writeline(out_file, output_line);
+		write(output_line, string'("* Total Errors for "));
+		write(output_line, FILENAME);
+		write(output_line, string'(": "));
+		write(output_line, err_cnt);
+		writeline(out_file, output_line);
+		write(output_line, string'("*****************************************************************************"));
+		writeline(out_file, output_line);
+
+		file_close(stim_file); -- Close File
+
+		loop
+			wait for 100000 us;
+		end loop;
+
+	end process;
+
+-----------------------------------------------------------------------------
+-- POP Process
+-----------------------------------------------------------------------------
+	POP_PROCESS : process
+	variable	vPOP_PTR   : integer_vector(POP_PTR'range);
+	variable	DONE       : boolean;
+
+	file        out_file    : text open write_mode is "STD_OUTPUT";
+
+-------- For VHDL-87
+--	file        out_file    : text is out "STD_OUTPUT";
+
+	variable	tmp_lout    : line;
+	
+	
+	variable    CHAR_PTR    : integer;
+	variable    EOS         : integer;
+	
+	begin
+		CHAR_PTR := 1;
+		ERR_CNT  <= 0;
+		POP_PTR  <= (others => 0);
+		vPOP_PTR := (others => 0);
+		CMD_REQo  <= (others => '0');
+		POP_INIT  <= '1';
+		if(SET_CHAN /= '1') then
+			wait until(SET_CHAN'event and (SET_CHAN = '1'));
+		end if;
+
+		loop
+			DONE := FALSE;
+			loop
+				DONE := TRUE;
+				for i in POP_PTR'reverse_range loop
+					if((vPOP_PTR(i) /= PUSH_PTR(i)) and (CMD_ACK(i) = '0')) then -- FIFO channel not empty
+						CMD <= FD(i)(vPOP_PTR(i));
+						CMD_REQo(i) <= '1';
+						for j in STRING_MAX downto 1 loop
+							if(FD(i)(vPOP_PTR(i))(j) /= ' ') then
+								EOS := j;
+								exit;
+							end if;
+						end loop;
+						write(tmp_lout, FILENAME);
+						write(tmp_lout, FD(i)(vPOP_PTR(i))(1 to EOS));
+						writeline(out_file, tmp_lout);
+						if(CMD_ACK(i) /= '1') then
+							wait until(CMD_ACK'event and (CMD_ACK(i) = '1'));
+						end if;
+						CMD_REQo(i) <= '0';
+						DONE := FALSE;
+						vPOP_PTR(i) := vPOP_PTR(i) + 1;
+						if(vPOP_PTR(i) >= FIFO_DEPTH) then
+							vPOP_PTR(i) := 0;
+						end if;
+						POP_PTR(i) <= vPOP_PTR(i);
+					end if;
+				end loop;
+				if(DONE) then
+					exit;
+				end if;
+			end loop;
+			
+			
+			
+			wait on PUSH_PTR, CMD_ACK;
+
+		end loop;
+
+	end process;
+
+	CMD_REQ <= CMD_REQo;
+
+end MODEL;
+
--- a/hdl/testbench/spec/gnum_model/gennum_tb.tar
+++ b/hdl/testbench/spec/gnum_model/gennum_tb.tar
--- a/hdl/testbench/spec/gnum_model/gn412x_bfm.vhd
+++ b/hdl/testbench/spec/gnum_model/gn412x_bfm.vhd
--- a/hdl/testbench/spec/gnum_model/mem_model.vhd
+++ b/hdl/testbench/spec/gnum_model/mem_model.vhd
--- a/hdl/testbench/spec/gnum_model/textutil.vhd
+++ b/hdl/testbench/spec/gnum_model/textutil.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use std.textio.all;
+use work.util.all;
+
+-----------------------------------------------------------------------------
+-- *Module      : textutil
+--
+-- *Description : Improved Free-format string and line manipulation
+--
+-- *History: M. Alford (originaly created 1993 with subsequent updates)
+-----------------------------------------------------------------------------
+package textutil is
+	procedure read_token(L : inout line; X : out STRING);
+	procedure sget_token(S : in string; P : inout integer; X : out STRING);
+	procedure sget_vector(S : in string; P : inout integer; VEC : out STD_ULOGIC_VECTOR);
+	procedure sget_vector_64(S : in string; P : inout integer; VEC : out STD_ULOGIC_VECTOR);
+	procedure sget_int(S : in string; P : inout integer; X : out integer);
+	function  hex_char_to_vector(C : in character) return STD_ULOGIC_VECTOR;
+	function  vector_to_hex_char(V : in STD_ULOGIC_VECTOR) return character;
+	function  is_hex(C : in character) return BOOLEAN;
+	function  hex_char_to_int(C : in character) return integer;
+	procedure read_vector(L : inout line; VEC : out STD_ULOGIC_VECTOR);
+	procedure read_int(L : inout line; I : out integer);
+	procedure write_hex_vector(L : inout line; V : in STD_ULOGIC_VECTOR);
+	function  to_str(constant V: in STD_ULOGIC_VECTOR) return STRING;
+	function  to_str(constant V: in STD_ULOGIC) return STRING;
+	function  to_str(constant val : in INTEGER) return STRING;
+	function  to_strn(constant val : in INTEGER; constant n : in INTEGER) return STRING;
+end textutil;
+
+package body textutil is
+
+-----------------------------------------------------------------------------
+-- *Module      : read_token
+--
+-- *Description : Skip over spaces then load a token string from a line
+--                until either the string is full or the token is finished
+--                (i.e. another space).  The output string is padded out
+--                with blanks at the end if the token length is less then
+--                the full string length.
+-----------------------------------------------------------------------------
+	procedure read_token(L : inout line; X : out STRING) is
+	variable char : character;
+	begin
+		if(L'length > 0) then
+			char := ' ';
+			while((char = ' ') and (L'length > 0)) loop	-- Skip spaces
+				read(L, char);
+			end loop;
+			for i in X'low to X'high loop
+				X(i) := char;
+				if(char /= ' ') then
+					if(L'length > 0) then
+						read(L, char);
+					else
+						char := ' ';
+					end if;
+				end if;
+			end loop;
+		else
+			assert false report "Couldn't read a token from file"
+			severity error;
+		end if;
+	end read_token;
+
+-----------------------------------------------------------------------------
+-- *Module      : sget_token
+--
+-- *Description : Same as read_token except for strings.
+-----------------------------------------------------------------------------
+	procedure sget_token(S : in string; P : inout integer; X : out STRING) is
+	variable char : character;
+	begin
+		if(S'length > P) then
+			char := ' ';
+			while((char = ' ') and (S'length >= P)) loop	-- Skip spaces
+				char := S(P);
+				P := P + 1;
+			end loop;
+			for i in X'low to X'high loop
+				X(i) := char;
+				if(char /= ' ') then
+					if(S'length > P) then
+						char := S(P);
+						P := P + 1;
+					else
+						char := ' ';
+					end if;
+				end if;
+			end loop;
+		else
+			assert false report "Couldn't read a token from a string"
+			severity error;
+		end if;
+	end sget_token;
+			
+-----------------------------------------------------------------------------
+-- *Module      : hex_char_to_vector
+--
+-- *Description : Convert a hex character to a vector
+-----------------------------------------------------------------------------
+	function hex_char_to_vector(C : in character) return STD_ULOGIC_VECTOR is
+	variable X : STD_ULOGIC_VECTOR( 3 downto 0);
+	begin
+		case C is
+			when '0' => X := "0000";
+			when '1' => X := "0001";
+			when '2' => X := "0010";
+			when '3' => X := "0011";
+			when '4' => X := "0100";
+			when '5' => X := "0101";
+			when '6' => X := "0110";
+			when '7' => X := "0111";
+			when '8' => X := "1000";
+			when '9' => X := "1001";
+			when 'A' => X := "1010";
+			when 'B' => X := "1011";
+			when 'C' => X := "1100";
+			when 'D' => X := "1101";
+			when 'E' => X := "1110";
+			when 'F' => X := "1111";
+			when 'a' => X := "1010";
+			when 'b' => X := "1011";
+			when 'c' => X := "1100";
+			when 'd' => X := "1101";
+			when 'e' => X := "1110";
+			when 'f' => X := "1111";
+			when others => 
+				X := "0000";
+				assert false report "Invalid Hex Character"
+				severity error;
+		end case;
+		return(X);
+	end hex_char_to_vector;
+
+-----------------------------------------------------------------------------
+-- *Module      : vector_to_hex_char
+--
+-- *Description : Convert a vector to a hex character. Only uses low 4 bits.
+-----------------------------------------------------------------------------
+	function vector_to_hex_char(V : in STD_ULOGIC_VECTOR) return character is
+	variable C  : character;
+	variable VV : STD_ULOGIC_VECTOR(3 downto 0);
+	begin
+		if(V'length < 4) then
+			VV := To_X01(V(V'low + 3 downto V'low));
+		else
+			VV := To_X01(V(V'low + V'length - 1 downto V'low));
+		end if;
+		case VV is
+			when "0000" => C := '0';
+			when "0001" => C := '1';
+			when "0010" => C := '2';
+			when "0011" => C := '3';
+			when "0100" => C := '4';
+			when "0101" => C := '5';
+			when "0110" => C := '6';
+			when "0111" => C := '7';
+			when "1000" => C := '8';
+			when "1001" => C := '9';
+			when "1010" => C := 'A';
+			when "1011" => C := 'B';
+			when "1100" => C := 'C';
+			when "1101" => C := 'D';
+			when "1110" => C := 'E';
+			when "1111" => C := 'F';
+			when others => C := 'X';
+		end case;
+		return(C);
+	end vector_to_hex_char;
+
+-----------------------------------------------------------------------------
+-- *Module      : is_hex
+--
+-- *Description : report if a char is ASCII hex
+-----------------------------------------------------------------------------
+	function is_hex(C : in character) return BOOLEAN is
+	variable X : boolean;
+	begin
+		case C is
+			when '0' => X := TRUE;
+			when '1' => X := TRUE;
+			when '2' => X := TRUE;
+			when '3' => X := TRUE;
+			when '4' => X := TRUE;
+			when '5' => X := TRUE;
+			when '6' => X := TRUE;
+			when '7' => X := TRUE;
+			when '8' => X := TRUE;
+			when '9' => X := TRUE;
+			when 'A' => X := TRUE;
+			when 'B' => X := TRUE;
+			when 'C' => X := TRUE;
+			when 'D' => X := TRUE;
+			when 'E' => X := TRUE;
+			when 'F' => X := TRUE;
+			when 'a' => X := TRUE;
+			when 'b' => X := TRUE;
+			when 'c' => X := TRUE;
+			when 'd' => X := TRUE;
+			when 'e' => X := TRUE;
+			when 'f' => X := TRUE;
+			when others => 
+				X := FALSE;
+		end case;
+		return(X);
+	end is_hex;
+
+-----------------------------------------------------------------------------
+-- *Module      : hex_char_to_int
+--
+-- *Description : Convert a hex character to an integer
+-----------------------------------------------------------------------------
+	function hex_char_to_int(C : in character) return integer is
+	variable X : integer;
+	begin
+		case C is
+			when '0' => X := 0;
+			when '1' => X := 1;
+			when '2' => X := 2;
+			when '3' => X := 3;
+			when '4' => X := 4;
+			when '5' => X := 5;
+			when '6' => X := 6;
+			when '7' => X := 7;
+			when '8' => X := 8;
+			when '9' => X := 9;
+			when 'A' => X := 10;
+			when 'B' => X := 11;
+			when 'C' => X := 12;
+			when 'D' => X := 13;
+			when 'E' => X := 14;
+			when 'F' => X := 15;
+			when 'a' => X := 10;
+			when 'b' => X := 11;
+			when 'c' => X := 12;
+			when 'd' => X := 13;
+			when 'e' => X := 14;
+			when 'f' => X := 15;
+			when others => 
+				X := 0;
+				assert false report "Invalid Hex Character"
+				severity error;
+		end case;
+		return(X);
+	end hex_char_to_int;
+			
+-----------------------------------------------------------------------------
+-- *Module      : read_vector
+--
+-- *Description : load a vector from the input line in a free floating format
+-----------------------------------------------------------------------------
+	procedure read_vector(L : inout line; VEC : out STD_ULOGIC_VECTOR) is
+	variable char : character;
+	variable base : integer;
+	variable q : integer;
+	variable v : STD_ULOGIC_VECTOR(31 downto 0);
+	begin
+		if(L'length > 0) then
+			char := ' ';
+			while(char = ' ') loop	-- Skip spaces
+				read(L, char);
+			end loop;
+			base := 16;			-- Hex is the default
+			if(char = '%') then -- determine base
+				read(L, char);
+				if(char = 'b' or char = 'B') then
+					base := 2;
+				elsif(char = 'x' or char = 'X') then
+					base := 16;
+				elsif(char = 'd' or char = 'D') then
+					base := 10;
+				else
+					assert false report "Unsupported Base detected when reading a Vector"
+					severity error;
+				end if;
+				read(L, char);
+			end if;
+			q := 0;
+			if(is_hex(char)) then
+				q := q * base + hex_char_to_int(char);
+				while(is_hex(char) and not (L'length = 0))  loop
+					read(L, char);
+					if(is_hex(char)) then
+						q := q * base + hex_char_to_int(char);
+					end if;
+				end loop;
+			end if;			
+			if(q < 0) then
+				q := q-2147483648;
+				V(30 downto 0) := to_vector(q, 31);
+				V(31) := '1';
+			else
+				V(30 downto 0) := to_vector(q, 31);
+				V(31) := '0';
+			end if;
+			VEC := V((VEC'high - VEC'low) downto 0);
+		else
+			assert false report "Couldn't read a vector"
+			severity error;
+		end if;
+	end read_vector;
+
+-----------------------------------------------------------------------------
+-- *Module      : sget_vector
+--
+-- *Description : Same as sget_vector except for strings
+-----------------------------------------------------------------------------
+	procedure sget_vector(S : in string; P : inout integer; VEC : out STD_ULOGIC_VECTOR) is
+	variable char : character;
+	variable base : integer;
+	variable q : integer;
+	variable v : STD_ULOGIC_VECTOR(31 downto 0);
+	begin
+		while(S(P) = ' ') loop	-- Skip spaces
+			if(P >= S'length) then
+				P := S'length;
+				exit;
+			end if;
+			P := P + 1;
+		end loop;
+		if(S'length > P) then
+			char := S(P);
+			if(char = '"') then -- read in as a literal
+				q := v'high;
+				v := (others => 'U');
+				VEC := v(VEC'range);
+				char := ' ';
+				P := P + 1;
+				while((char /= '"') and not (S'length = P))  loop
+					char := S(P);
+					P := P + 1;				
+					case char is
+						when '0' =>
+							v(q) := '0';
+						when '1' =>
+							v(q) := '1';
+						when 'L' | 'l' =>
+							v(q) := 'L';
+						when 'H' | 'h' =>
+							v(q) := 'H';
+						when 'Z' | 'z' =>
+							v(q) := 'Z';
+						when 'X' | 'x' =>
+							v(q) := 'X';
+						when 'U' | 'u' =>
+							v(q) := 'U';
+						when others =>
+--							char := '"';
+							exit;
+					end case;
+					q := q - 1;
+				end loop;
+				if(v'high-q < 2) then -- only a single bit was read
+					VEC(VEC'low) := v(v'high);
+				elsif((v'high - q) > VEC'length) then -- too many bits
+					VEC := v(q+VEC'length downto q+1);
+				else -- the number of bits read is same or less than required
+					VEC(v'high-q-1+VEC'low downto VEC'low) := v(v'high downto q+1);
+				end if;
+			else
+				base := 16;			-- Hex is the default
+				if(char = '%') then -- determine base
+					P := P + 1;			
+					char := S(P);
+					P := P + 1;			
+					if(char = 'b' or char = 'B') then
+						base := 2;
+					elsif(char = 'x' or char = 'X') then
+						base := 16;
+					elsif(char = 'd' or char = 'D') then
+						base := 10;
+					else
+						assert false report "Unsupported Base detected when reading a Vector"
+						severity error;
+					end if;
+				elsif((char = '0') and ((S(P+1) = 'x') or (S(P+1) = 'X'))) then
+					P := P + 2;
+				end if;
+				q := 0;
+				char := S(P);
+				if(is_hex(char)) then
+					while(is_hex(char) and not (S'length = P))  loop
+						if(is_hex(char)) then
+							q := q * base + hex_char_to_int(char);
+						end if;
+						P := P + 1;				
+						char := S(P);
+					end loop;
+				end if;			
+				if(q < 0) then
+					q := q-2147483648;
+					V(30 downto 0) := to_vector(q, 31);
+					V(31) := '1';
+				else
+					V(30 downto 0) := to_vector(q, 31);
+					V(31) := '0';
+				end if;
+				VEC := V((VEC'high - VEC'low) downto 0);
+			end if;
+		else
+			assert false report "Couldn't read a vector"
+			severity error;
+			V := (others => '0');
+			VEC := V((VEC'high - VEC'low) downto 0);
+		end if;
+	end sget_vector;
+	
+-----------------------------------------------------------------------------
+-- *Module      : sget_vector_64
+--
+-- *Description : Same as sget_vector except can handle 64 bit quantities and hex or binary base (no base 10)
+-----------------------------------------------------------------------------
+	procedure sget_vector_64(S : in string; P : inout integer; VEC : out STD_ULOGIC_VECTOR) is
+	variable char : character;
+	variable base : integer;
+	variable q : integer;
+	variable v : STD_ULOGIC_VECTOR(63 downto 0);
+	begin
+		while(S(P) = ' ') loop	-- Skip spaces
+			if(P >= S'length) then
+				P := S'length;
+				exit;
+			end if;
+			P := P + 1;
+		end loop;
+		if(S'length > P) then
+			char := S(P);
+			if(char = '"') then -- read in as a literal
+				q := v'high;
+				v := (others => 'U');
+				VEC := v(VEC'range);
+				char := ' ';
+				P := P + 1;
+				while((char /= '"') and not (S'length = P))  loop
+					char := S(P);
+					P := P + 1;				
+					case char is
+						when '0' =>
+							v(q) := '0';
+						when '1' =>
+							v(q) := '1';
+						when 'L' | 'l' =>
+							v(q) := 'L';
+						when 'H' | 'h' =>
+							v(q) := 'H';
+						when 'Z' | 'z' =>
+							v(q) := 'Z';
+						when 'X' | 'x' =>
+							v(q) := 'X';
+						when 'U' | 'u' =>
+							v(q) := 'U';
+						when others =>
+--							char := '"';
+							exit;
+					end case;
+					q := q - 1;
+				end loop;
+				if(v'high-q < 2) then -- only a single bit was read
+					VEC(VEC'low) := v(v'high);
+				elsif((v'high - q) > VEC'length) then -- too many bits
+					VEC := v(q+VEC'length downto q+1);
+				else -- the number of bits read is same or less than required
+					VEC(v'high-q-1+VEC'low downto VEC'low) := v(v'high downto q+1);
+				end if;
+			else
+				base := 16;			-- Hex is the default
+				if(char = '%') then -- determine base
+					P := P + 1;			
+					char := S(P);
+					P := P + 1;			
+					if(char = 'b' or char = 'B') then
+						base := 2;
+					elsif(char = 'x' or char = 'X') then
+						base := 16;
+					else
+						assert false report "Unsupported Base detected when reading a Vector"
+						severity error;
+					end if;
+					char := S(P);
+--					P := P + 1;	
+				elsif((char = '0') and ((S(P+1) = 'x') or (S(P+1) = 'X'))) then
+					P := P + 2;
+				end if;
+				v := (others => '0');
+				char := S(P);
+				if(base = 2) then
+					while(((char = '0') or (char = '1')) and not (P > S'length))  loop
+						if(char = '0') then
+							v := v(v'high-1 downto 0) & '0';
+						else
+							v := v(v'high-1 downto 0) & '1';
+						end if;
+						P := P + 1;				
+						char := S(P);
+					end loop;
+				else
+					while(is_hex(char) and not (P > S'length))  loop
+						if(is_hex(char)) then
+							v := v(v'high-4 downto 0) & hex_char_to_vector(char);
+						end if;
+						P := P + 1;				
+						char := S(P);
+					end loop;
+				end if;
+				VEC := V((VEC'high - VEC'low) downto 0);
+			end if;
+		else
+			assert false report "Couldn't read a vector"
+			severity error;
+			V := (others => '0');
+			VEC := V((VEC'high - VEC'low) downto 0);
+		end if;
+	end sget_vector_64;
+	
+-----------------------------------------------------------------------------
+-- *Module      : read_int
+--
+-- *Description : load an integer from the input line in a free floating format
+-----------------------------------------------------------------------------
+	procedure read_int(L : inout line; I : out integer) is
+	variable char : character;
+	variable base : integer;
+	variable q : integer;
+	begin
+		if(L'length > 0) then
+			char := ' ';
+			while(char = ' ') loop	-- Skip spaces
+				read(L, char);
+			end loop;
+			base := 16;			-- Hex is the default
+			if(char = '%') then -- determine base
+				read(L, char);
+				if(char = 'b' or char = 'B') then
+					base := 2;
+				elsif(char = 'x' or char = 'X') then
+					base := 16;
+				elsif(char = 'd' or char = 'D') then
+					base := 10;
+				else
+					assert false report "Unsupported Base detected when reading an integer"
+					severity error;
+				end if;
+				read(L, char);
+			end if;
+			q := 0;
+			if(is_hex(char)) then
+				q := q * base + hex_char_to_int(char);
+				while(is_hex(char) and not (L'length = 0))  loop
+					read(L, char);
+					if(is_hex(char)) then
+						q := q * base + hex_char_to_int(char);
+					end if;
+				end loop;
+			end if;
+			I := q;
+		else
+			assert false report "Couldn't read an integer"
+			severity error;
+		end if;
+	end read_int;
+
+-----------------------------------------------------------------------------
+-- *Module      : sget_int
+--
+-- *Description : Same as read_int except for strings
+-----------------------------------------------------------------------------
+	procedure sget_int(S : in string;  P : inout integer; X : out integer) is
+	variable char : character;
+	variable base : integer;
+	variable q : integer;
+	begin
+		if(S'length > P) then
+			char := ' ';
+			while(char = ' ') loop	-- Skip spaces
+				char := S(P);
+				P := P + 1;
+			end loop;
+			base := 16;			-- Hex is the default
+			if(char = '%') then -- determine base
+				char := S(P);
+				P := P + 1;			
+				if(char = 'b' or char = 'B') then
+					base := 2;
+				elsif(char = 'x' or char = 'X') then
+					base := 16;
+				elsif(char = 'd' or char = 'D') then
+					base := 10;
+				else
+					assert false report "Unsupported Base detected when reading an integer"
+					severity error;
+				end if;
+				char := S(P);
+				P := P + 1;
+			end if;
+			q := 0;
+			if(is_hex(char)) then
+				q := q * base + hex_char_to_int(char);
+				while(is_hex(char) and not (S'length = P))  loop
+					char := S(P);
+					P := P + 1;					
+					if(is_hex(char)) then
+						q := q * base + hex_char_to_int(char);
+					end if;
+				end loop;
+			end if;
+			X := q;
+		else
+			assert false report "Couldn't read an integer"
+			severity error;
+		end if;
+	end sget_int;
+
+-----------------------------------------------------------------------------
+-- *Module      : write_hex_vector
+--
+-- *Description : writes out a vector as hex
+-----------------------------------------------------------------------------
+	procedure write_hex_vector(L : inout line; V : in STD_ULOGIC_VECTOR) is
+	variable C : character;
+	variable VV : STD_ULOGIC_VECTOR(((V'length + 3)/4) * 4 - 1 downto 0);
+	begin
+
+		VV := (others => '0');
+		VV(V'length -1 downto 0) := V;
+
+		for i in VV'length/4 - 1 downto 0 loop
+			C := vector_to_hex_char(VV(i*4+3 downto i*4));
+			write(L, C);
+		end loop;
+
+	end write_hex_vector;
+
+-----------------------------------------------------------------------------
+-- *Module      : to_str
+--
+-- *Description : Converts a STD_ULOGIC_VECTOR to a string of the same length
+-----------------------------------------------------------------------------
+	function to_str(constant V: in STD_ULOGIC_VECTOR) return STRING is
+	variable S : STRING(1 to V'length);
+	variable sp : integer;
+	begin
+		sp := 1;
+		for i in V'range loop
+			case V(i) is
+				when '1' | 'H' =>
+					S(sp) := '1';
+				when '0' | 'L' =>
+					S(sp) := '0';
+				when others =>
+					S(sp) := 'X';
+			end case;
+			sp := sp + 1;
+		end loop;
+		return(S);
+	end to_str;
+
+-----------------------------------------------------------------------------
+-- *Module      : to_str
+--
+-- *Description : Converts a STD_ULOGIC to a string
+-----------------------------------------------------------------------------
+	function to_str(constant V: in STD_ULOGIC) return STRING is
+--	variable S : STRING(1);
+	begin
+			case V is
+				when '1' | 'H' =>
+					return("1");
+				when '0' | 'L' =>
+					return("0");
+				when others =>
+					return("X");
+			end case;
+		return("X");
+	end to_str;
+
+-----------------------------------------------------------------------------
+-- *Module      : to_str
+--
+-- *Description : Converts a integer to a string
+-----------------------------------------------------------------------------
+	function  to_str(constant val : in INTEGER) return STRING is
+	variable result : STRING(11 downto 1) := "-2147483648"; -- smallest integer and longest string
+	variable tmp    : INTEGER;
+	variable pos    : NATURAL := 1;
+	variable digit  : NATURAL;
+	begin
+		-- for the smallest integer MOD does not seem to work...
+		--if val = -2147483648 then	: compilation error with Xilinx tools...
+		if val < -2147483647 then
+			pos := 12;
+		else
+			tmp := abs(val);
+			loop
+		  		digit := abs(tmp MOD 10);
+			   		tmp := tmp / 10;
+		    		result(pos) := character'val(character'pos('0') + digit);
+		    		pos := pos + 1;
+		    		exit when tmp = 0;
+			end loop;
+			if val < 0 then
+		   		result(pos) := '-';
+		   		pos := pos + 1;
+			end if;
+		end if;
+		return result((pos-1) downto 1);
+	end to_str;
+
+-----------------------------------------------------------------------------
+-- *Module      : to_strn
+--
+-- *Description : Converts an integer to a string of length N
+-----------------------------------------------------------------------------
+	function  to_strn(constant val : in INTEGER; constant n : in INTEGER) return STRING is
+	variable result : STRING(11 downto 1) := "-2147483648"; -- smallest integer and longest string
+	variable tmp    : INTEGER;
+	variable pos    : NATURAL := 1;
+	variable digit  : NATURAL;
+	begin
+		-- for the smallest integer MOD does not seem to work...
+		--if val = -2147483648 then	: compilation error with Xilinx tools...
+		if val < -2147483647 then
+			pos := 12;
+		else
+			result := (others => ' ');
+			tmp := abs(val);
+			loop
+		  		digit := abs(tmp MOD 10);
+			   		tmp := tmp / 10;
+		    		result(pos) := character'val(character'pos('0') + digit);
+		    		pos := pos + 1;
+		    		exit when tmp = 0;
+			end loop;
+			if val < 0 then
+		   		result(pos) := '-';
+		   		pos := pos + 1;
+			end if;
+		end if;
+		return result(n downto 1);
+	end to_strn;
+
+
+end textutil;
--- a/hdl/testbench/spec/gnum_model/util.vhd
+++ b/hdl/testbench/spec/gnum_model/util.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+--library synopsys;
+--use synopsys.arithmetic.all;
+
+package UTIL is
+	function to_mvl ( b: in boolean ) return STD_ULOGIC;
+	function to_mvl ( i: in integer ) return STD_ULOGIC;
+	function to_vector(input,num_bits:integer) return STD_ULOGIC_VECTOR;
+--	function to_signed( b: in std_ulogic_vector ) return signed;
+--	function to_std_ulogic_vector( b: in signed ) return std_ulogic_vector;
+--	function std_logic_to_std_ulogic( b: in std_logic ) return std_ulogic;
+--	function std_ulogic_to_std_logic( b: in std_ulogic ) return std_logic;
+	function "and"(l: STD_ULOGIC_VECTOR; r: STD_ULOGIC) return STD_ULOGIC_VECTOR;
+	function "and"(l: STD_ULOGIC; r: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+	function "and"(l: STD_ULOGIC_VECTOR; r: BOOLEAN) return STD_ULOGIC_VECTOR;
+	function "and"(l: BOOLEAN; r: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+	function "and"(l: BOOLEAN; r: STD_ULOGIC) return STD_ULOGIC;
+	function "and"(l: STD_ULOGIC; r: BOOLEAN) return STD_ULOGIC;
+	function exp(input: STD_ULOGIC; num_bits: integer) return STD_ULOGIC_VECTOR;
+	function exp(input: STD_ULOGIC_VECTOR; num_bits: integer) return STD_ULOGIC_VECTOR;
+	function conv_integer ( ARG: in STD_ULOGIC_VECTOR ) return integer;
+	function "+"(l: STD_ULOGIC_VECTOR; r: STD_ULOGIC) return STD_ULOGIC_VECTOR;
+--	function "+"(l: STD_ULOGIC_VECTOR; r: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+--	function "-"(l: STD_ULOGIC_VECTOR; r: STD_ULOGIC) return STD_ULOGIC_VECTOR;
+--	function "-"(l: STD_ULOGIC_VECTOR; r: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+	function to_int(l: std_ulogic_vector) return natural;
+	function to_int(l: std_ulogic) return natural;
+	function and_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC;
+	function nand_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC;
+	function or_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC;
+	function nor_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC;
+	function xor_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC;
+	function xnor_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC;
+	function ge ( l, r : STD_ULOGIC_VECTOR ) return BOOLEAN;
+	function gt ( l, r : STD_ULOGIC_VECTOR ) return BOOLEAN;
+	function lt ( l, r : STD_ULOGIC_VECTOR ) return BOOLEAN;
+	function eq ( l, r : STD_ULOGIC_VECTOR ) return BOOLEAN;
+	function maximum ( arg1, arg2 : INTEGER) return INTEGER;
+	function minimum ( arg1, arg2 : INTEGER) return INTEGER;
+	procedure keep(signal X: inout STD_LOGIC);
+	function log2(A: in integer) return integer;
+    -------------------------------------------------------------------
+    -- Declaration of Synthesis directive attributes
+    -------------------------------------------------------------------
+    ATTRIBUTE synthesis_return : string ;
+
+end UTIL;
+
+package body UTIL is
+
+    --------------------------------------------------------------------
+--	function to_signed ( b: in std_ulogic_vector ) return signed is
+--		variable result	: signed(b'range);
+--	begin
+--		for i in b'range loop
+--			result(i) := b(i);
+--		end loop;
+--		return result;
+--	end to_signed;
+
+    --------------------------------------------------------------------
+--	function to_std_ulogic_vector ( b: in signed ) return std_ulogic_vector is
+--		variable result	: std_ulogic_vector(b'range);
+--	begin
+--		for i in b'range loop
+--			result(i) := b(i);
+--		end loop;
+--		return result;
+--	end to_std_ulogic_vector;
+
+    --------------------------------------------------------------------
+
+	function to_mvl ( b: in boolean ) return STD_ULOGIC is
+	begin
+		if ( b = TRUE ) then
+			return( '1' );
+		else
+			return( '0' );
+		end if;
+	end to_mvl;
+
+    --------------------------------------------------------------------
+
+	function to_mvl ( i: in integer ) return STD_ULOGIC is
+	begin
+		if ( i = 1 ) then
+			return( '1' );
+		else
+			return( '0' );
+		end if;
+	end to_mvl;
+
+    --------------------------------------------------------------------
+
+	function "and"(l: STD_ULOGIC; r: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+	variable rr: STD_ULOGIC_vector(r'range);
+	begin
+		if (l = '1') then
+			rr := r;
+		else
+			rr := (others => '0');
+		end if;
+		return(rr);
+	end;
+
+    --------------------------------------------------------------------
+
+	function "and"(l: STD_ULOGIC_VECTOR; r: STD_ULOGIC) return STD_ULOGIC_VECTOR is
+	variable ll: STD_ULOGIC_vector(l'range);
+	begin
+		if (r = '1') then
+			ll := l;
+		else
+			ll := (others => '0');
+		end if;
+		return(ll);
+	end;
+
+    --------------------------------------------------------------------
+
+	function "and"(l: BOOLEAN; r: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+	variable rr: STD_ULOGIC_vector(r'range);
+	begin
+		if (l) then
+			rr := r;
+		else
+			rr := (others => '0');
+		end if;
+		return(rr);
+	end;
+
+    --------------------------------------------------------------------
+
+	function "and"(l: STD_ULOGIC_VECTOR; r: BOOLEAN) return STD_ULOGIC_VECTOR is
+	variable ll: STD_ULOGIC_vector(l'range);
+	begin
+		if (r) then
+			ll := l;
+		else
+			ll := (others => '0');
+		end if;
+		return(ll);
+	end;
+
+    --------------------------------------------------------------------
+
+	function "and"(l: BOOLEAN; r: STD_ULOGIC) return STD_ULOGIC is
+	variable ll: STD_ULOGIC;
+	begin
+		if (l) then
+			ll := r;
+		else
+			ll := '0';
+		end if;
+		return(ll);
+	end;
+
+    --------------------------------------------------------------------
+
+	function "and"(l: STD_ULOGIC; r: BOOLEAN) return STD_ULOGIC is
+	variable ll: STD_ULOGIC;
+	begin
+		if (r) then
+			ll := l;
+		else
+			ll := '0';
+		end if;
+		return(ll);
+	end;
+
+    --------------------------------------------------------------------
+
+--	function std_ulogic_to_std_logic(b : std_ulogic) return std_logic is
+--	variable result: std_logic;
+--	begin
+--		result := b;
+--		return result;
+--	end;
+
+    --------------------------------------------------------------------
+ 
+--	function std_logic_to_std_ulogic(b : std_logic) return std_ulogic is
+--	variable result: std_ulogic;
+--	begin
+--		result := b;
+--		return result;
+--	end;
+ 
+	--------------------------------------------------------------------
+
+	function to_vector(input,num_bits: integer) return std_ulogic_vector is
+		variable vec: std_ulogic_vector(num_bits-1 downto 0);
+		variable a: integer;
+	begin
+		a := input;
+		for i in 0 to num_bits-1 loop
+			if ((a mod 2) = 1) then
+				vec(i) := '1';
+			else
+				vec(i) := '0';
+			end if;
+			a := a / 2;
+		end loop;
+		return vec;
+	end to_vector;
+
+
+
+--	FUNCTION  to_vector(input,num_bits:integer) RETURN STD_ULOGIC_VECTOR IS
+--	VARIABLE result:STD_ULOGIC_VECTOR(num_bits-1 DOWNTO 0);
+--	VARIABLE weight:integer;
+--	VARIABLE temp:integer;
+--	BEGIN
+--		weight := 2**(num_bits-1);
+--		temp := input;
+--		FOR i in result'HIGH DOWNTO result'LOW LOOP
+--			IF temp >= weight THEN
+--				result(i) := '1';
+--				temp := temp - weight;
+--			ELSE
+--				result(i) := '0';
+--			END IF;
+--			weight := weight/2;
+--		END LOOP;
+--		RETURN result;
+--	END to_vector;
+
+	--------------------------------------------------------------------
+	-- exp: Expand one bit into many
+	--------------------------------------------------------------------
+
+	FUNCTION  exp(input:STD_ULOGIC; num_bits:integer) RETURN STD_ULOGIC_VECTOR IS
+	VARIABLE result:STD_ULOGIC_VECTOR(num_bits-1 DOWNTO 0);
+	BEGIN
+		FOR i in result'HIGH DOWNTO result'LOW LOOP
+			result(i) := input;
+		END LOOP;
+		RETURN result;
+	END exp;
+
+	--------------------------------------------------------------------
+	-- exp: Expand n bits into m bits
+	--------------------------------------------------------------------
+
+	FUNCTION  exp(input:STD_ULOGIC_VECTOR; num_bits:integer) RETURN STD_ULOGIC_VECTOR IS
+	VARIABLE result:STD_ULOGIC_VECTOR(num_bits-1 DOWNTO 0);
+	BEGIN
+		result(input'high-input'low downto 0) := input;
+		result(num_bits-1 downto input'high-input'low+1) := (others => '0');
+		RETURN result;
+	END exp;
+
+	--------------------------------------------------------------------
+	-- conv_integer
+	--------------------------------------------------------------------
+
+	function conv_integer ( ARG: in STD_ULOGIC_VECTOR ) return integer is
+	variable result: INTEGER;
+	begin
+		assert ARG'length <= 31
+			report "ARG is too large in CONV_INTEGER"
+			severity FAILURE;
+		result := 0;
+		for i in ARG'range loop
+			result := result * 2;
+			if(ARG(i) = 'H' or ARG(i) = '1') then
+				result := result + 1;
+			end if;
+		end loop;
+		return result;
+	end;
+
+	--------------------------------------------------------------------
+	-- "+" Increment function
+	--------------------------------------------------------------------
+	function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is
+	variable Q: STD_ULOGIC_VECTOR(L'range);
+	variable A: STD_ULOGIC;
+	begin
+		A := R;
+		for i in L'low to L'high loop
+			Q(i) := L(i) xor A;
+			A := A and L(i);
+		end loop;
+		return Q;
+	end;
+
+	--------------------------------------------------------------------
+	-- "+" adder function
+	--------------------------------------------------------------------
+--	function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+--	variable Q	 : SIGNED(L'range);
+--	variable result: STD_ULOGIC_VECTOR(L'range);
+--	begin
+--		Q      := to_signed(L) + to_signed(R);
+--		result := to_std_ulogic_vector(Q);
+--		return result;
+--	end;
+
+	--------------------------------------------------------------------
+	-- "-" Decrement function
+	--------------------------------------------------------------------
+--	function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is
+--	variable Q: STD_ULOGIC_VECTOR(L'range);
+--	variable A: STD_ULOGIC;
+--	begin
+--		A := R;
+--		for i in L'low to L'high loop
+--			Q(i) := L(i) xor A;
+--			A := A and not L(i);
+--		end loop;
+--		return Q;
+--	end;
+
+	--------------------------------------------------------------------
+	-- "-" subtractor function
+	--------------------------------------------------------------------
+--	function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+--	variable Q     : SIGNED(L'range);
+--	variable result: STD_ULOGIC_VECTOR(L'range);
+--	begin
+--		Q      := to_signed(L) - to_signed(R);
+--		result := to_std_ulogic_vector(Q);
+--		return result;
+--	end;
+
+	--------------------------------------------------------------------
+	-- to_int : Convert std_ulogic_vector to an integer
+	--------------------------------------------------------------------
+	function to_int(l: std_ulogic_vector) return natural is
+	variable result: natural := 0;
+	begin
+		for t1 in l'range loop
+			result := result * 2;
+			if (l(t1) = '1') or (l(t1) = 'H') then
+				result := result + 1;
+			end if;
+		end loop;
+		return result;
+	end to_int;
+
+	--------------------------------------------------------------------
+	-- to_int : Convert std_ulogic_vector to an integer
+	--------------------------------------------------------------------
+	function to_int(l: std_ulogic) return natural is
+	variable result: natural := 0;
+	begin
+		if (l = '1') or (l = 'H') then
+			result := 1;
+		else
+			result := 0;
+		end if;
+		return result;
+	end to_int;
+
+	--------------------------------------------------------------------
+	-- Reduce Functions
+	--------------------------------------------------------------------
+	function and_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+	variable result: STD_ULOGIC;
+	begin
+	result := '1';
+	for i in ARG'range loop
+		result := result and ARG(i);
+	end loop;
+	return result;
+	end;
+
+	function nand_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+	begin
+	return not and_reduce(ARG);
+	end;
+
+	function or_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+	variable result: STD_ULOGIC;
+	begin
+	result := '0';
+	for i in ARG'range loop
+		result := result or ARG(i);
+	end loop;
+	return result;
+	end;
+
+	function nor_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+	begin
+	return not or_reduce(ARG);
+	end;
+
+	function xor_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+	variable result: STD_ULOGIC;
+	begin
+	result := '0';
+	for i in ARG'range loop
+		result := result xor ARG(i);
+	end loop;
+	return result;
+	end;
+
+	function xnor_reduce(ARG: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+	begin
+	return not xor_reduce(ARG);
+	end;
+
+	--------------------------------------------------------------------
+	-- Some useful generic functions
+	--------------------------------------------------------------------
+	--//// Zero Extend ////
+	--
+	-- Function zxt
+	--
+	FUNCTION zxt( q : STD_ULOGIC_VECTOR; i : INTEGER ) RETURN STD_ULOGIC_VECTOR IS
+		VARIABLE qs : STD_ULOGIC_VECTOR (1 TO i);
+		VARIABLE qt : STD_ULOGIC_VECTOR (1 TO q'length);
+		-- Hidden function. Synthesis directives are present in its callers
+	BEGIN
+		qt := q;
+		IF i < q'length THEN
+			qs := qt( (q'length-i+1) TO qt'right);
+		ELSIF i > q'length THEN
+			qs := (OTHERS=>'0');
+			qs := qs(1 TO (i-q'length)) & qt;
+		ELSE
+			qs := qt;
+		END IF;
+		RETURN qs;
+	END;
+
+	FUNCTION maximum (arg1,arg2:INTEGER) RETURN INTEGER IS
+	BEGIN
+		IF(arg1 > arg2) THEN
+			RETURN(arg1) ;
+		ELSE
+			RETURN(arg2) ;
+		END IF;
+	END ;
+
+	FUNCTION minimum (arg1,arg2:INTEGER) RETURN INTEGER IS
+	BEGIN
+		IF(arg1 < arg2) THEN
+			RETURN(arg1) ;
+		ELSE
+			RETURN(arg2) ;
+		END IF;
+	END ;
+
+	--------------------------------------------------------------------
+	-- Comparision functions
+	--------------------------------------------------------------------
+--
+-- Equal functions.
+--
+	TYPE stdlogic_boolean_table IS ARRAY(std_ulogic, std_ulogic) OF BOOLEAN;
+
+	CONSTANT eq_table : stdlogic_boolean_table := (
+	--
+	 ----------------------------------------------------------------------------
+	--      |  U       X      0     1      Z      W      L      H      D |   |
+    --
+     ----------------------------------------------------------------------------
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | U |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | X |
+    ( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ),    -- | 0 |
+    ( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ),    -- | 1 |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | Z |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | W |
+    ( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ),    -- | L |
+    ( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ),    -- | H |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE )   -- | D |
+    );
+
+    FUNCTION eq  ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
+        -- Equal for two logic types  
+        VARIABLE result : BOOLEAN ;
+        ATTRIBUTE synthesis_return OF result:VARIABLE IS "EQ" ; 
+    BEGIN
+        result := eq_table( l, r );
+        RETURN result ;
+    END;
+
+    FUNCTION eq  ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
+        CONSTANT ml  : INTEGER := maximum( l'length, r'length );
+        VARIABLE lt  : STD_ULOGIC_VECTOR ( 1 TO ml );
+        VARIABLE rt  : STD_ULOGIC_VECTOR ( 1 TO ml );
+        -- Arithmetic Equal for two Unsigned vectors  
+        VARIABLE result : BOOLEAN ;
+        ATTRIBUTE synthesis_return OF result:VARIABLE IS "EQ" ; 
+    BEGIN
+        lt := zxt( l, ml );
+        rt := zxt( r, ml );
+        FOR i IN lt'range LOOP
+            IF NOT eq( lt(i), rt(i) ) THEN
+               result := FALSE;
+               RETURN result ;
+            END IF;
+        END LOOP;
+        RETURN TRUE;
+    END;
+
+    TYPE std_ulogic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
+    TYPE std_ulogic_fuzzy_state_table IS ARRAY ( std_ulogic, std_ulogic ) OF std_ulogic_fuzzy_state;
+
+    CONSTANT ge_fuzzy_table : std_ulogic_fuzzy_state_table := (
+	--      ----------------------------------------------------
+	--      |  U    X    0    1    Z    W    L    H    D         |   |
+	--      ----------------------------------------------------
+            ( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ),  -- | U |
+	        ( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ),  -- | X |
+	        ( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ),  -- | 0 |
+	        ( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ),  -- | 1 |
+	        ( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ),  -- | Z |
+	        ( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ),  -- | W |
+	        ( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ),  -- | L |
+	        ( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ),  -- | H |
+	        ( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' )   -- | D |
+    );
+
+    FUNCTION ge  ( L,R : std_ulogic_vector ) RETURN boolean IS
+        CONSTANT ml  : integer := maximum( L'LENGTH, R'LENGTH );
+        VARIABLE lt  : std_ulogic_vector ( 1 to ml );
+        VARIABLE rt  : std_ulogic_vector ( 1 to ml );
+        VARIABLE res : std_ulogic_fuzzy_state;
+        -- Greater-than-or-equal for two Unsigned vectors
+        VARIABLE result : BOOLEAN ;
+        ATTRIBUTE synthesis_return OF result:VARIABLE IS "GTE" ; 
+    begin
+        lt := zxt( l, ml );
+        rt := zxt( r, ml );
+        FOR i IN lt'RANGE LOOP
+            res := ge_fuzzy_table( lt(i), rt(i) );
+            CASE res IS
+              WHEN 'U'          => RETURN FALSE;
+              WHEN 'X'          => RETURN FALSE;
+              WHEN 'T'          => RETURN TRUE;
+              WHEN 'F'          => RETURN FALSE;
+              WHEN OTHERS       => null;
+            END CASE;
+        END LOOP;
+        result := TRUE ;
+        RETURN result;
+    end ;
+
+--
+-- Greater Than functions.
+--
+    CONSTANT gtb_table : stdlogic_boolean_table := (
+    --
+     ----------------------------------------------------------------------------
+    --      |  U       X      0     1      Z      W      L      H      D |   |
+    --
+     ----------------------------------------------------------------------------
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | U |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | X |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | 0 |
+    ( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ),    -- | 1 |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | Z |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | W |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | L |
+    ( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ),    -- | H |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE )   -- | D |
+    );
+
+    FUNCTION gt  ( l, r : std_logic ) RETURN BOOLEAN IS
+        -- Greater-than for two logic types
+        VARIABLE result : BOOLEAN ;
+        ATTRIBUTE synthesis_return OF result:VARIABLE IS "GT" ; 
+    BEGIN
+        result := gtb_table( l, r );
+        RETURN result ;
+    END ;
+
+    FUNCTION gt  ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
+        CONSTANT ml  : INTEGER := maximum( l'length, r'length );
+        VARIABLE lt  : STD_ULOGIC_VECTOR ( 1 TO ml );
+        VARIABLE rt  : STD_ULOGIC_VECTOR ( 1 TO ml );
+        -- Greater-than for two logic unsigned vectors
+        VARIABLE result : BOOLEAN ;
+        ATTRIBUTE synthesis_return OF result:VARIABLE IS "GT" ; 
+    BEGIN
+        lt := zxt( l, ml );
+        rt := zxt( r, ml );
+        FOR i IN lt'range LOOP
+            IF NOT eq( lt(i), rt(i) ) THEN
+               result := gt( lt(i), rt(i) );
+               RETURN result ;
+            END IF;
+        END LOOP;
+        RETURN FALSE;
+    END;
+
+--
+-- Less Than functions.
+--
+    CONSTANT ltb_table : stdlogic_boolean_table := (
+    --
+     ----------------------------------------------------------------------------
+    --      |  U       X      0     1      Z      W      L      H      D |   |
+    --
+     ----------------------------------------------------------------------------
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | U |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | X |
+    ( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ),    -- | 0 |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | 1 |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | Z |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | W |
+    ( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ),    -- | L |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ),  -- | H |
+    ( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE )   -- | D |
+    );
+
+    FUNCTION lt  ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
+        -- Less-than for two logic types
+        VARIABLE result : BOOLEAN ;
+        ATTRIBUTE synthesis_return OF result:VARIABLE IS "LT" ; 
+    BEGIN
+        result := ltb_table( l, r );
+        RETURN result ;
+    END;
+
+    FUNCTION lt  ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
+        CONSTANT ml  : INTEGER := maximum( l'length, r'length );
+        VARIABLE ltt  : STD_ULOGIC_VECTOR ( 1 TO ml );
+        VARIABLE rtt  : STD_ULOGIC_VECTOR ( 1 TO ml );
+        -- Less-than for two Unsigned vectors
+        VARIABLE result : BOOLEAN ;
+        ATTRIBUTE synthesis_return OF result:VARIABLE IS "LT" ; 
+    BEGIN
+        ltt := zxt( l, ml );
+        rtt := zxt( r, ml );
+        FOR i IN ltt'range LOOP
+            IF NOT eq( ltt(i), rtt(i) ) THEN
+               result := lt( ltt(i), rtt(i) );
+               RETURN result ;
+            END IF;
+        END LOOP;
+        RETURN FALSE;
+    END;
+
+    --------------------------------------------------------------------
+    -- "keep" Retain Last value when floated
+    --------------------------------------------------------------------
+    procedure keep(signal X: inout STD_LOGIC) is
+    begin
+		if(X = 'Z') then
+			if(X'last_value = '0') then
+				X <= 'L';
+			elsif(X'last_value = '1') then
+				X <= 'H';
+			else
+				X <= 'Z';
+			end if;
+		else
+			X <= 'Z';
+		end if;
+    end keep;
+
+	---------------------------------------------------------------------
+	-- log base 2 function
+	---------------------------------------------------------------------
+	function log2 ( A: in integer ) return integer is
+		variable B  : integer;
+		begin
+			B := 1;
+			for i in 0 to 31 loop
+				if not ( A > B ) then
+					return ( i );
+					exit;
+				end if;
+				B := B * 2;
+			end loop;
+	end log2;
+
+
+
+end UTIL;
+
--- a/hdl/testbench/spec/start_stop_gen.vhd
+++ b/hdl/testbench/spec/start_stop_gen.vhd
+-- Created by : G. Penacoba
+-- Creation Date: May 2011
+-- Description: generates start and stop pulses for test-bench
+-- Modified by:
+-- Modification Date:
+-- Modification consisted on:
+
+
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_textio.all;
+use std.textio.all;
+
+entity start_stop_gen is
+    port(
+        tstart_o                : out std_logic;
+        tstop1_o                : out std_logic;
+        tstop2_o                : out std_logic;
+        tstop3_o                : out std_logic;
+        tstop4_o                : out std_logic;
+        tstop5_o                : out std_logic
+    );
+end start_stop_gen;
+
+architecture behavioral of start_stop_gen is
+
+
+signal tstart               : std_logic:='0';
+signal tstop1               : std_logic:='0';
+signal tstop2               : std_logic:='0';
+signal tstop3               : std_logic:='0';
+signal tstop4               : std_logic:='0';
+signal tstop5               : std_logic:='0';
+
+signal pulse_channel        : integer;
+signal pulse_length         : time;
+
+begin
+	-- process reading the schedule of frame exchange from a text file
+	------------------------------------------------------------------
+	sequence: process
+	file sequence_file			: text open read_mode is "data_vectors/pulses.txt";
+	variable sequence_line		: line;
+	variable interval_time		: time;
+	variable coma				: string(1 to 1);
+	variable pulse_ch   		: integer;
+	variable pulse_lgth   		: time;
+	
+	begin
+			readline	        (sequence_file, sequence_line);
+			read		        (sequence_line, interval_time);
+			read		        (sequence_line, coma);
+			read		        (sequence_line, pulse_ch);
+			read		        (sequence_line, coma);
+			read		        (sequence_line, pulse_lgth);
+			wait for interval_time;
+            pulse_channel       <= pulse_ch;
+            pulse_length        <= pulse_lgth;
+
+			if endfile(sequence_file) then
+				file_close(sequence_file);
+                wait;
+			end if;
+	end process;
+    
+    start_extender: process
+    begin
+        wait until pulse_channel = 0;
+        tstart      <= '1';
+        wait for pulse_length;
+        tstart      <= '0';
+    end process;
+
+    stop1_extender: process
+    begin
+        wait until pulse_channel = 1;
+        tstop1      <= '1';
+        wait for pulse_length;
+        tstop1      <= '0';
+    end process;
+ 
+    stop2_extender: process
+    begin
+        wait until pulse_channel = 2;
+        tstop2      <= '1';
+        wait for pulse_length;
+        tstop2      <= '0';
+    end process;
+ 
+    stop3_extender: process
+    begin
+        wait until pulse_channel = 3;
+        tstop3      <= '1';
+        wait for pulse_length;
+        tstop3      <= '0';
+    end process;
+ 
+    stop4_extender: process
+    begin
+        wait until pulse_channel = 4;
+        tstop4      <= '1';
+        wait for pulse_length;
+        tstop4      <= '0';
+    end process;
+ 
+    stop5_extender: process
+    begin
+        wait until pulse_channel = 5;
+        tstop5      <= '1';
+        wait for pulse_length;
+        tstop5      <= '0';
+    end process;
+
+        tstart_o                <= tstart;
+        tstop1_o                <= tstop1;
+        tstop2_o                <= tstop2;
+        tstop3_o                <= tstop3;
+        tstop4_o                <= tstop4;
+        tstop5_o                <= tstop5;
+
+end behavioral;
--- a/hdl/testbench/spec/tb_tdc.vhd
+++ b/hdl/testbench/spec/tb_tdc.vhd
+----------------------------------------------------------------------------------------------------
+--  CERN-BE-CO-HT
+----------------------------------------------------------------------------------------------------
+--
+--  unit name   : TDC test-bench (tb_tdc)
+--  author      : G. Penacoba
+--  date        : May 2011
+--  version     : Revision 1
+--  description : top module for test-bench
+--  dependencies:
+--  references  :
+--  modified by :
+--
+----------------------------------------------------------------------------------------------------
+--  last changes:
+----------------------------------------------------------------------------------------------------
+--  to do:
+----------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity tb_tdc is
+end tb_tdc;
+
+architecture behavioral of tb_tdc is
+
+    component top_tdc
+    generic(
+        g_span                  : integer :=32;
+        g_width                 : integer :=32;
+        values_for_simulation   : boolean :=FALSE
+    );
+    port(
+        -- interface with GNUM circuit
+        rst_n_a_i      : in  std_logic;
+        -- P2L Direction
+        p2l_clk_p_i : in  std_logic;                      -- Receiver Source Synchronous Clock+
+        p2l_clk_n_i : in  std_logic;                      -- Receiver Source Synchronous Clock-
+        p2l_data_i  : in  std_logic_vector(15 downto 0);  -- Parallel receive data
+        p2l_dframe_i: in  std_logic;                      -- Receive Frame
+        p2l_valid_i : in  std_logic;                      -- Receive Data Valid
+        p2l_rdy_o   : out std_logic;                      -- Rx Buffer Full Flag
+        p_wr_req_i  : in  std_logic_vector(1 downto 0);   -- PCIe Write Request
+        p_wr_rdy_o  : out std_logic_vector(1 downto 0);   -- PCIe Write Ready
+        rx_error_o  : out std_logic;                      -- Receive Error
+        vc_rdy_i    : in  std_logic_vector(1 downto 0);   -- Virtual channel ready
+        -- L2P Direction
+        l2p_clk_p_o : out std_logic;                      -- Transmitter Source Synchronous Clock+
+        l2p_clk_n_o : out std_logic;                      -- Transmitter Source Synchronous Clock-
+        l2p_data_o  : out std_logic_vector(15 downto 0);  -- Parallel transmit data
+        l2p_dframe_o: out std_logic;                      -- Transmit Data Frame
+        l2p_valid_o : out std_logic;                      -- Transmit Data Valid
+        l2p_edb_o   : out std_logic;                      -- Packet termination and discard
+        l2p_rdy_i   : in  std_logic;                      -- Tx Buffer Full Flag
+        l_wr_rdy_i  : in  std_logic_vector(1 downto 0);   -- Local-to-PCIe Write
+        p_rd_d_rdy_i: in  std_logic_vector(1 downto 0);   -- PCIe-to-Local Read Response Data Ready
+        tx_error_i  : in  std_logic;                      -- Transmit Error
+        irq_p_o     : out std_logic;                      -- Interrupt request pulse to GN4124 GPIO
+        spare_o     : out std_logic;
+
+       -- interface signals with PLL circuit
+        acam_refclk_i           : in std_logic;
+        pll_ld_i                : in std_logic;
+        pll_refmon_i            : in std_logic;
+        pll_sdo_i               : in std_logic;
+        pll_status_i            : in std_logic;
+        
+        pll_cs_o                : out std_logic;
+        pll_dac_sync_o          : out std_logic;
+        pll_sdi_o               : out std_logic;
+        pll_sclk_o              : out std_logic;
+        tdc_clk_p_i             : in std_logic;
+        tdc_clk_n_i             : in std_logic;
+
+        -- interface signals with acam (timing)
+        err_flag_i              : in std_logic;
+        int_flag_i              : in std_logic;
+
+        start_dis_o             : out std_logic;
+        start_from_fpga_o       : out std_logic;
+        stop_dis_o              : out std_logic;
+
+        -- interface signals with acam (data)
+        data_bus_io             : inout std_logic_vector(27 downto 0);
+        ef1_i                   : in std_logic;
+        ef2_i                   : in std_logic;
+        lf1_i                   : in std_logic;
+        lf2_i                   : in std_logic;
+
+        address_o               : out std_logic_vector(3 downto 0);
+        cs_n_o                  : out std_logic;
+        oe_n_o                  : out std_logic;
+        rd_n_o                  : out std_logic;
+        wr_n_o                  : out std_logic;
+
+        -- other signals on the tdc card
+        tdc_in_fpga_5_i         : in std_logic;
+
+        mute_inputs_o           : out std_logic;
+        tdc_led_status_o        : out std_logic;
+        tdc_led_trig1_o         : out std_logic;
+        tdc_led_trig2_o         : out std_logic;
+        tdc_led_trig3_o         : out std_logic;
+        tdc_led_trig4_o         : out std_logic;
+        tdc_led_trig5_o         : out std_logic;
+        
+        -- other signals on the spec card
+        spec_aux0_i             : in std_logic;
+        spec_aux1_i             : in std_logic;
+        spec_aux2_o             : out std_logic;
+        spec_aux3_o             : out std_logic;
+        spec_aux4_o             : out std_logic;
+        spec_aux5_o             : out std_logic;
+        spec_led_green_o        : out std_logic;
+        spec_led_red_o          : out std_logic;
+        spec_clk_i              : in std_logic
+    );
+    end component;
+
+    component acam_model
+    generic(
+        start_retrig_period     : time:= 3200 ns;
+        refclk_period           : time:= 32 ns
+    );
+    port(
+        tstart_i                : in std_logic;
+        tstop1_i                : in std_logic;
+        tstop2_i                : in std_logic;
+        tstop3_i                : in std_logic;
+        tstop4_i                : in std_logic;
+        tstop5_i                : in std_logic;
+        startdis_i              : in std_logic;
+        stopdis_i               : in std_logic;
+
+        int_flag_o              : out std_logic;
+        err_flag_o              : out std_logic;
+
+        address_i               : in std_logic_vector(3 downto 0);
+        cs_n_i                  : in std_logic;
+        oe_n_i                  : in std_logic;
+        rd_n_i                  : in std_logic;
+        wr_n_i                  : in std_logic;
+       
+        data_bus_io             : inout std_logic_vector(27 downto 0);
+        ef1_o                   : out std_logic;
+        ef2_o                   : out std_logic;
+        lf1_o                   : out std_logic;
+        lf2_o                   : out std_logic
+    );
+    end component;
+
+    component start_stop_gen
+    port(
+        tstart_o                : out std_logic;
+        tstop1_o                : out std_logic;
+        tstop2_o                : out std_logic;
+        tstop3_o                : out std_logic;
+        tstop4_o                : out std_logic;
+        tstop5_o                : out std_logic
+    );
+    end component;
+
+-----------------------------------------------------------------------------
+-- GN4124 Local Bus Model
+-----------------------------------------------------------------------------
+  component GN412X_BFM
+    generic
+      (
+        STRING_MAX     : integer := 256;           -- Command string maximum length
+        T_LCLK         : time    := 10 ns;         -- Local Bus Clock Period
+        T_P2L_CLK_DLY  : time    := 2 ns;          -- Delay from LCLK to P2L_CLK
+        INSTANCE_LABEL : string  := "GN412X_BFM";  -- Label string to be used as a prefix for messages from the model
+        MODE_PRIMARY   : boolean := true           -- TRUE for BFM acting as GN412x, FALSE for BFM acting as the DUT
+        );
+    port
+      (
+        --=========================================================--
+        -------------------------------------------------------------
+        -- CMD_ROUTER Interface
+        --
+        CMD                : in    string(1 to STRING_MAX);
+        CMD_REQ            : in    bit;
+        CMD_ACK            : out   bit;
+        CMD_CLOCK_EN       : in    boolean;
+        --=========================================================--
+        -------------------------------------------------------------
+        -- GN412x Signal I/O
+        -------------------------------------------------------------
+        -- This is the reset input to the BFM
+        --
+        RSTINn             : in    std_logic;
+        -------------------------------------------------------------
+        -- Reset outputs to DUT
+        --
+        RSTOUT18n          : out   std_logic;
+        RSTOUT33n          : out   std_logic;
+        -------------------------------------------------------------
+        ----------------- Local Bus Clock ---------------------------
+        -------------------------------------------------------------  __ Direction for primary mode
+        --                                                            / \
+        LCLK, LCLKn        : inout std_logic;      -- Out
+        -------------------------------------------------------------
+        ----------------- Local-to-PCI Dataflow ---------------------
+        -------------------------------------------------------------
+        -- Transmitter Source Synchronous Clock.
+        --
+        L2P_CLKp, L2P_CLKn : inout std_logic;      -- In  
+        -------------------------------------------------------------
+        -- L2P DDR Link
+        --
+        L2P_DATA           : inout std_logic_vector(15 downto 0);  -- In  -- Parallel Transmit Data.
+        L2P_DFRAME         : inout std_logic;  -- In  -- Transmit Data Frame.
+        L2P_VALID          : inout std_logic;  -- In  -- Transmit Data Valid. 
+        L2P_EDB            : inout std_logic;  -- In  -- End-of-Packet Bad Flag.
+        -------------------------------------------------------------
+        -- L2P SDR Controls
+        --
+        L_WR_RDY           : inout std_logic_vector(1 downto 0);  -- Out -- Local-to-PCIe Write.
+        P_RD_D_RDY         : inout std_logic_vector(1 downto 0);  -- Out -- PCIe-to-Local Read Response Data Ready.
+        L2P_RDY            : inout std_logic;  -- Out -- Tx Buffer Full Flag.
+        TX_ERROR           : inout std_logic;  -- Out -- Transmit Error.
+        -------------------------------------------------------------
+        ----------------- PCIe-to-Local Dataflow ---------------------
+        -------------------------------------------------------------
+        -- Transmitter Source Synchronous Clock.
+        --
+        P2L_CLKp, P2L_CLKn : inout std_logic;  -- Out -- P2L Source Synchronous Clock.
+        -------------------------------------------------------------
+        -- P2L DDR Link
+        --
+        P2L_DATA           : inout std_logic_vector(15 downto 0);  -- Out -- Parallel Receive Data.
+        P2L_DFRAME         : inout std_logic;  -- Out -- Receive Frame.
+        P2L_VALID          : inout std_logic;  -- Out -- Receive Data Valid.
+        -------------------------------------------------------------
+        -- P2L SDR Controls
+        --
+        P2L_RDY            : inout std_logic;  -- In  -- Rx Buffer Full Flag.
+        P_WR_REQ           : inout std_logic_vector(1 downto 0);  -- Out -- PCIe Write Request.
+        P_WR_RDY           : inout std_logic_vector(1 downto 0);  -- In  -- PCIe Write Ready.
+        RX_ERROR           : inout std_logic;  -- In  -- Receive Error.
+        VC_RDY             : inout std_logic_vector(1 downto 0);  -- Out -- Virtual Channel Ready Status.
+        -------------------------------------------------------------
+        -- GPIO signals
+        --
+        GPIO               : inout std_logic_vector(15 downto 0)
+        );
+  end component;  --GN412X_BFM;
+
+-----------------------------------------------------------------------------
+-- CMD_ROUTER component
+-----------------------------------------------------------------------------
+  component cmd_router
+    generic(N_BFM      : integer := 8;
+            N_FILES    : integer := 3;
+            FIFO_DEPTH : integer := 8;
+            STRING_MAX : integer := 256
+            );
+    port(CMD          : out string(1 to STRING_MAX);
+         CMD_REQ      : out bit_vector(N_BFM-1 downto 0);
+         CMD_ACK      : in  bit_vector(N_BFM-1 downto 0);
+         CMD_ERR      : in  bit_vector(N_BFM-1 downto 0);
+         CMD_CLOCK_EN : out boolean
+         );
+  end component;  --cmd_router;
+
+constant pll_clk_period         : time:= 8 ns;
+constant g_width                : integer:= 32;
+constant g_span                 : integer:= 32;
+constant spec_clk_period        : time:= 50 ns;
+constant start_retrig_period    : time:= 512 ns;
+
+  -- Number of Models receiving commands
+  constant N_BFM      : integer                      := 1;  -- 0 : GN412X_BFM in Model Mode
+  --                                                        -- 1 : GN412X_BFM in DUT mode
+  -- Number of files to feed BFMs
+  constant N_FILES    : integer                      := 1;
+  --
+  -- Depth of the command FIFO for each model
+  constant FIFO_DEPTH : integer                      := 16;
+  --
+  -- Maximum width of a command string
+  constant STRING_MAX : integer                      := 256;
+
+signal acam_refclk_i        : std_logic:='0';
+signal tdc_clk_p_i          : std_logic:='0';
+signal tdc_clk_n_i          : std_logic:='1';
+signal spec_clk_i           : std_logic:='0';
+
+signal pll_ld_i             : std_logic;
+signal pll_refmon_i         : std_logic;
+signal pll_sdo_i            : std_logic;
+signal pll_status_i         : std_logic;
+        
+signal pll_cs_o             : std_logic;
+signal pll_dac_sync_o       : std_logic;
+signal pll_sdi_o            : std_logic;
+signal pll_sclk_o           : std_logic;
+
+signal mute_inputs          : std_logic;
+
+signal address_o            : std_logic_vector(3 downto 0);
+signal cs_n_o               : std_logic;
+signal data_bus_io          : std_logic_vector(27 downto 0);
+signal ef1_i                : std_logic;
+signal ef2_i                : std_logic;
+signal err_flag_i           : std_logic;
+signal int_flag_i           : std_logic;
+signal lf1_i                : std_logic;
+signal lf2_i                : std_logic;
+signal oe_n_o               : std_logic;
+signal rd_n_o               : std_logic;
+signal start_dis_o          : std_logic;
+signal start_from_fpga_o    : std_logic;
+signal stop_dis_o           : std_logic;
+signal wr_n_o               : std_logic;
+
+--signal tstart               : std_logic;
+signal tstop1               : std_logic;
+signal tstop2               : std_logic;
+signal tstop3               : std_logic;
+signal tstop4               : std_logic;
+signal tstop5               : std_logic;
+signal dummy_tstop5         : std_logic;
+
+signal tdc_in_fpga_5        : std_logic;
+
+signal tdc_led_status       : std_logic;
+signal tdc_led_trig1        : std_logic;
+signal tdc_led_trig2        : std_logic;
+signal tdc_led_trig3        : std_logic;
+signal tdc_led_trig4        : std_logic;
+signal tdc_led_trig5        : std_logic;
+signal spec_aux0_i          : std_logic;
+signal spec_aux1_i          : std_logic;
+signal spec_aux2_o          : std_logic;
+signal spec_aux3_o          : std_logic;
+signal spec_aux4_o          : std_logic;
+signal spec_aux5_o          : std_logic;
+signal spec_led_green       : std_logic;
+signal spec_led_red         : std_logic;
+
+  -- GN4124 interface
+signal rst_n                : std_logic;
+signal irq_p                : std_logic;
+signal spare                : std_logic;
+
+  signal RSTINn             : std_logic;
+  signal RSTOUT18n          : std_logic;
+  signal RSTOUT33n          : std_logic;
+  signal LCLK, LCLKn        : std_logic;
+
+  signal P2L_CLKp, P2L_CLKn : std_logic;
+  signal P2L_DATA           : std_logic_vector(15 downto 0);
+  signal P2L_DATA_32        : std_logic_vector(31 downto 0);  -- For monitoring use
+  signal P2L_DFRAME         : std_logic;
+  signal P2L_VALID          : std_logic;
+  signal P2L_RDY            : std_logic;
+  signal P_WR_REQ           : std_logic_vector(1 downto 0);
+  signal P_WR_RDY           : std_logic_vector(1 downto 0);
+  signal RX_ERROR           : std_logic;
+  signal VC_RDY             : std_logic_vector(1 downto 0);
+  signal L2P_CLKp, L2P_CLKn : std_logic;
+  signal L2P_DATA           : std_logic_vector(15 downto 0);
+  signal L2P_DATA_32        : std_logic_vector(31 downto 0);  -- For monitoring use
+  signal L2P_DFRAME         : std_logic;
+  signal L2P_VALID          : std_logic;
+  signal L2P_EDB            : std_logic;
+  signal L2P_RDY            : std_logic;
+  signal L_WR_RDY           : std_logic_vector(1 downto 0);
+  signal P_RD_D_RDY         : std_logic_vector(1 downto 0);
+  signal TX_ERROR           : std_logic;
+  signal GPIO               : std_logic_vector(15 downto 0);
+
+
+-----------------------------------------------------------------------------
+-- Command Router Signals
+-----------------------------------------------------------------------------
+  signal CMD          : string(1 to STRING_MAX);
+  signal CMD_REQ      : bit_vector(N_BFM-1 downto 0);
+  signal CMD_ACK      : bit_vector(N_BFM-1 downto 0);
+  signal CMD_ERR      : bit_vector(N_BFM-1 downto 0);
+  signal CMD_CLOCK_EN : boolean;
+
+begin
+
+    dut: top_tdc
+    generic map(
+        g_span                  => 32,
+        g_width                 => 32,
+        values_for_simulation   => TRUE
+    )
+    port map(
+        -- interface with GNUM circuit
+        rst_n_a_i               => rst_n,
+        p2l_clk_p_i             => p2l_clkp,
+        p2l_clk_n_i             => p2l_clkn,
+        p2l_data_i              => p2l_data,
+        p2l_dframe_i            => p2l_dframe,
+        p2l_valid_i             => p2l_valid,
+        p2l_rdy_o               => p2l_rdy,
+        p_wr_req_i              => p_wr_req,
+        p_wr_rdy_o              => p_wr_rdy,
+        rx_error_o              => rx_error,
+        vc_rdy_i                => vc_rdy,
+        l2p_clk_p_o             => l2p_clkp,
+        l2p_clk_n_o             => l2p_clkn,
+        l2p_data_o              => l2p_data,
+        l2p_dframe_o            => l2p_dframe,
+        l2p_valid_o             => l2p_valid,
+        l2p_edb_o               => l2p_edb,
+        l2p_rdy_i               => l2p_rdy,
+        l_wr_rdy_i              => l_wr_rdy,
+        p_rd_d_rdy_i            => p_rd_d_rdy,
+        tx_error_i              => tx_error,
+        irq_p_o                 => irq_p,
+        spare_o                 => spare,
+        
+        -- interface with PLL circuit
+        acam_refclk_i           => acam_refclk_i,
+        pll_ld_i                => pll_ld_i,
+        pll_refmon_i            => pll_refmon_i,
+        pll_sdo_i               => pll_sdo_i,
+        pll_status_i            => pll_status_i,
+        
+        pll_cs_o                => pll_cs_o,
+        pll_dac_sync_o          => pll_dac_sync_o,
+        pll_sdi_o               => pll_sdi_o,
+        pll_sclk_o              => pll_sclk_o,
+        tdc_clk_p_i	            => tdc_clk_p_i,
+        tdc_clk_n_i	            => tdc_clk_n_i,
+        
+        -- interface signals with acam (timing)
+        int_flag_i          => int_flag_i,
+        err_flag_i          => err_flag_i,
+
+        start_dis_o         => start_dis_o,
+        start_from_fpga_o   => start_from_fpga_o,
+        stop_dis_o          => stop_dis_o,
+        
+        -- interface signals with acam (data)
+        data_bus_io         => data_bus_io,
+        ef1_i               => ef1_i,
+        ef2_i               => ef2_i,
+        lf1_i               => lf1_i,
+        lf2_i               => lf2_i,
+        
+        address_o           => address_o,
+        cs_n_o              => cs_n_o,
+        oe_n_o              => oe_n_o,
+        rd_n_o              => rd_n_o,
+        wr_n_o              => wr_n_o,
+        
+        -- other signals on the tdc card
+        tdc_in_fpga_5_i     => tdc_in_fpga_5,
+
+        mute_inputs_o       => mute_inputs,
+        tdc_led_status_o    => tdc_led_status,
+        tdc_led_trig1_o     => tdc_led_trig1,
+        tdc_led_trig2_o     => tdc_led_trig2,
+        tdc_led_trig3_o     => tdc_led_trig3,
+        tdc_led_trig4_o     => tdc_led_trig4,
+        tdc_led_trig5_o     => tdc_led_trig5,
+        
+        -- other signals on the spec card
+        spec_aux0_i         => spec_aux0_i,
+        spec_aux1_i         => spec_aux1_i,
+        spec_aux2_o         => spec_aux2_o,
+        spec_aux3_o         => spec_aux3_o,
+        spec_aux4_o         => spec_aux4_o,
+        spec_aux5_o         => spec_aux5_o,
+        spec_led_green_o    => spec_led_green,
+        spec_led_red_o      => spec_led_red,
+        spec_clk_i          => spec_clk_i
+    );
+    
+    acam: acam_model
+    generic map(
+        start_retrig_period     => start_retrig_period,
+        refclk_period           => pll_clk_period/4
+    )
+    port map(
+        tstart_i                => start_from_fpga_o,
+        tstop1_i                => tstop1,
+        tstop2_i                => tstop2,
+        tstop3_i                => tstop3,
+        tstop4_i                => tstop4,
+        tstop5_i                => tstop5,
+--        tstop5_i                => dummy_tstop5,
+        startdis_i              => start_dis_o,
+        stopdis_i               => stop_dis_o,
+        
+        int_flag_o              => int_flag_i,
+        
+        address_i               => address_o,
+        cs_n_i                  => cs_n_o,
+        oe_n_i                  => oe_n_o,
+        rd_n_i                  => rd_n_o,
+        wr_n_i                  => wr_n_o,
+        
+        data_bus_io             => data_bus_io,
+        ef1_o                   => ef1_i,
+        ef2_o                   => ef2_i,
+        err_flag_o              => err_flag_i,
+        lf1_o                   => lf1_i,
+        lf2_o                   => lf2_i
+    );
+        
+    pulses_generator: start_stop_gen
+    port map(
+        tstart_o            => open,
+        tstop1_o            => tstop1,
+        tstop2_o            => tstop2,
+        tstop3_o            => tstop3,
+        tstop4_o            => tstop4,
+        tstop5_o            => tstop5
+    );
+    
+  CMD_ERR <= (others => '0');
+
+  UC : cmd_router
+    generic map
+    (N_BFM      => N_BFM,
+     N_FILES    => N_FILES,
+     FIFO_DEPTH => FIFO_DEPTH,
+     STRING_MAX => STRING_MAX
+     )
+    port map
+    (CMD          => CMD,
+     CMD_REQ      => CMD_REQ,
+     CMD_ACK      => CMD_ACK,
+     CMD_ERR      => CMD_ERR,
+     CMD_CLOCK_EN => CMD_CLOCK_EN
+     );
+
+-----------------------------------------------------------------------------
+-- GN412x BFM - PRIMARY
+-----------------------------------------------------------------------------
+
+  U0 : gn412x_bfm
+    generic map
+    (
+      STRING_MAX     => STRING_MAX,
+--      T_LCLK         => 5 ns,
+--      T_LCLK         => 10 ns,
+      T_LCLK         => 6.25 ns,
+      T_P2L_CLK_DLY  => 2 ns,
+      INSTANCE_LABEL => "U0(Primary GN412x): ",
+      MODE_PRIMARY   => true
+      )
+    port map
+    (
+      --=========================================================--
+      -------------------------------------------------------------
+      -- CMD_ROUTER Interface
+      --
+      CMD          => CMD,
+      CMD_REQ      => CMD_REQ(0),
+      CMD_ACK      => CMD_ACK(0),
+      CMD_CLOCK_EN => CMD_CLOCK_EN,
+      --=========================================================--
+      -------------------------------------------------------------
+      -- GN412x Signal I/O
+      -------------------------------------------------------------
+      -- This is the reset input to the BFM
+      --
+      RSTINn       => RSTINn,
+      -------------------------------------------------------------
+      -- Reset outputs to DUT
+      --
+      RSTOUT18n    => RSTOUT18n,
+      RSTOUT33n    => RSTOUT33n,
+      -------------------------------------------------------------
+      ----------------- Local Bus Clock ---------------------------
+      ------------------------------------------------------------- 
+      --
+      LCLK         => LCLK,
+      LCLKn        => LCLKn,
+      -------------------------------------------------------------
+      ----------------- Local-to-PCI Dataflow ---------------------
+      -------------------------------------------------------------
+      -- Transmitter Source Synchronous Clock.
+      --
+      L2P_CLKp     => L2P_CLKp,
+      L2P_CLKn     => L2P_CLKn,
+      -------------------------------------------------------------
+      -- L2P DDR Link
+      --
+      L2P_DATA     => L2P_DATA,
+      L2P_DFRAME   => L2P_DFRAME,
+      L2P_VALID    => L2P_VALID,
+      L2P_EDB      => L2P_EDB,
+      -------------------------------------------------------------
+      -- L2P SDR Controls
+      --
+      L_WR_RDY     => L_WR_RDY,
+      P_RD_D_RDY   => P_RD_D_RDY,
+      L2P_RDY      => L2P_RDY,
+      TX_ERROR     => TX_ERROR,
+      -------------------------------------------------------------
+      ----------------- PCIe-to-Local Dataflow ---------------------
+      -------------------------------------------------------------
+      -- Transmitter Source Synchronous Clock.
+      --
+      P2L_CLKp     => P2L_CLKp,
+      P2L_CLKn     => P2L_CLKn,
+      -------------------------------------------------------------
+      -- P2L DDR Link
+      --
+      P2L_DATA     => P2L_DATA,
+      P2L_DFRAME   => P2L_DFRAME,
+      P2L_VALID    => P2L_VALID,
+      -------------------------------------------------------------
+      -- P2L SDR Controls
+      --
+      P2L_RDY      => P2L_RDY,
+      P_WR_REQ     => P_WR_REQ,
+      P_WR_RDY     => P_WR_RDY,
+      RX_ERROR     => RX_ERROR,
+      VC_RDY       => VC_RDY,
+      GPIO         => gpio
+      );                                -- GN412X_BFM;
+
+    tdc_pll_clock: process
+    begin
+        if pll_cs_o ='1' and rst_n ='1' then
+            tdc_clk_p_i         <= not (tdc_clk_p_i) after 1 ns;
+            tdc_clk_n_i         <= not (tdc_clk_n_i) after 1 ns;
+        end if;
+        wait for pll_clk_period/2;
+    end process;
+
+    tdc_ref_clock: process
+    begin
+        if pll_cs_o ='1' and rst_n ='1' then
+            acam_refclk_i   <= not (acam_refclk_i) after 3 ns;
+        end if;
+        wait for pll_clk_period*2;
+    end process;
+    
+    spec_clock: process
+    begin
+        spec_clk_i           <= not (spec_clk_i) after 1 ns;
+        wait for spec_clk_period/2;
+    end process;
+
+    rst_n               <= RSTOUT18n;
+    GPIO(0)             <= irq_p;
+    GPIO(1)             <= spare;
+    
+    tdc_in_fpga_5       <= tstop5;
+    
+    spec_aux0_i         <= '1';
+    spec_aux1_i         <= '1';
+
+end behavioral;
--- a/hdl/testbench/svec/Manifest.py
+++ b/hdl/testbench/svec/Manifest.py
+action = "simulation"
+target = "xilinx"
+fetchto = "../../ip_cores"
+vlog_opt="+incdir+../../sim/wb +incdir+../../sim/vme64x_bfm +incdir+../../sim"
+
+files = [ "main.sv" ]
+
+modules = { "local" :  [ "../../top/svec" ] }
+
--- a/hdl/testbench/svec/main.sv
+++ b/hdl/testbench/svec/main.sv
+`include "vme64x_bfm.svh"
+`include "svec_vme_buffers.svh"
+
+module main;
+
+   reg rst_n = 0;
+   reg clk_125m = 0, clk_20m = 0, acam_refclk = 0;
+
+   always #4ns clk_125m <= ~clk_125m;
+   always #16ns acam_refclk <= ~acam_refclk;
+   always #25ns clk_20m <= ~clk_20m;
+
+   
+   
+   initial begin
+      repeat(20) @(posedge clk_125m);
+      rst_n = 1;
+   end
+   
+   IVME64X VME(rst_n);
+
+   `DECLARE_VME_BUFFERS(VME.slave);
+
+   reg acam_ef =1;
+   wire acam_rd;
+   
+   
+   top_tdc #(
+              .values_for_simul(1)
+              ) DUT (
+		     .clk_20m_vcxo_i(clk_20m),
+                     .por_n_i (rst_n),
+                     
+                     .ft0_tdc_125m_clk_p_i(clk_125m),
+                     .ft0_tdc_125m_clk_n_i(~clk_125m),
+                     .ft0_acam_refclk_p_i(acam_refclk),
+                     .ft0_acam_refclk_n_i(~acam_refclk),
+                     .ft0_pll_status_i(1'b1),
+                     .ft0_rd_n_o(acam_rd),
+                     .ft0_ef1_i(acam_ef),
+                     .ft0_ef2_i(1'b1),
+                     
+                     .ft1_tdc_125m_clk_p_i(clk_125m),
+                     .ft1_tdc_125m_clk_n_i(~clk_125m),
+                     .ft1_pll_status_i(1'b1),
+		     
+		     `WIRE_VME_PINS(8)
+	         );
+
+   initial begin
+      #500us;
+      forever begin
+      acam_ef = 0;
+      wait(!acam_rd);
+      #10ns;
+      acam_ef = 1;
+      #50us;
+         
+      end
+   end
+   
+
+   task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
+      /* map func0 to 0x80000000, A32 */
+      acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
+      acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
+      acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
+
+   endtask // init_vme64x_core
+   
+   initial begin
+      CBusAccessor_VME64x acc = new(VME.master);
+      CBusAccessor acc_casted = CBusAccessor'(acc);
+      uint64_t d;
+
+      #30us;
+
+      init_vme64x_core(acc);
+      acc_casted.set_default_xfer_size(A32|SINGLE|D32);
+      
+      acc.read('h80000000, d, D32|A32|SINGLE);
+      $display("Master SDB 0 = %x. Un-resetting TDC cores.", d);
+
+      acc.write('h80020008, 'hff , D32|A32|SINGLE);
+
+      // wait for the PLLs to settle up
+      #300us;
+
+
+      acc.read('h80040000, d, D32|A32|SINGLE);
+      $display("SDB core 0 = %x", d);
+      acc.read('h80060000, d, D32|A32|SINGLE);
+      $display("SDB core 1 = %x", d);
+
+      acc.write('h800500fc, 1, D32|A32|SINGLE); // init acquisition
+   
+      forever begin
+         acc.read('h800500a8, d, D32|A32|SINGLE); // init acquisition
+         $display("wr-ptr %x", d);
+         #10us;
+         
+      end
+      
+   end // initial begin
+   
+
+  
+endmodule // main
+
+
+
+
--- a/hdl/testbench/svec/run.do
+++ b/hdl/testbench/svec/run.do
+vlog -sv main.sv +incdir+. +incdir+../../sim/wb +incdir+../../sim/vme64x_bfm +incdir+../../sim
+vsim work.main -voptargs=+acc
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+
+do wave.do
+radix -hexadecimal
+run 100us
\ No newline at end of file
--- a/hdl/testbench/svec/wave.do
+++ b/hdl/testbench/svec/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/clk_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/rst_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_adr_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_cyc_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_dat_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_stb_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_we_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_config_rdbk_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_status_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_ififo1_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_ififo2_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_start01_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/wr_index_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/local_utc_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/core_status_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/irq_code_i
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_ack_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_dat_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_config_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/activate_acq_p_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/deactivate_acq_p_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_wr_config_p_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_rdbk_config_p_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_rst_p_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_rdbk_status_p_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_rdbk_ififo1_p_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_rdbk_ififo2_p_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_rdbk_start01_p_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/dacapo_c_rst_p_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/send_dac_word_p_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/dac_word_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/load_utc_p_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/starting_utc_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/irq_tstamp_threshold_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/irq_time_threshold_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/one_hz_phase_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_inputs_en_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/start_phase_o
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_config
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/reg_adr
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/reg_adr_pipe0
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/starting_utc
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_inputs_en
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/start_phase
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/ctrl_reg
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/one_hz_phase
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/irq_tstamp_threshold
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/irq_time_threshold
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/clear_ctrl_reg
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/send_dac_word_p
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/dac_word
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/pulse_extender_en
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/pulse_extender_c
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/dat_out
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/dat_out_pipe0
+add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_ack_o_pipe0
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {505599788 ps} 0}
+configure wave -namecolwidth 177
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {441541177 ps} {657429313 ps}