rtl/data_formatting: clean up temporary debugging code

70171d13 · Tomasz Wlostowski · 2dcf1100 · 70171d13
Commit 70171d13 authored Sep 11, 2018 by Tomasz Wlostowski
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Showing with 38 additions and 27 deletions

data_formatting.vhd hdl/rtl/data_formatting.vhd +38 -27

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--- a/hdl/rtl/data_formatting.vhd
+++ b/hdl/rtl/data_formatting.vhd
@@ -105,7 +105,7 @@ entity data_formatting is
     -- OUTPUTS
-     timestamp_o       : out t_raw_acam_timestamp;
+     timestamp_o       : out t_acam_timestamp;
     timestamp_valid_o : out std_logic
     );
@@ -128,7 +128,6 @@ architecture rtl of data_formatting is
  signal un_nb_of_cycles, un_retrig_from_roll_over            : unsigned(31 downto 0);
  signal acam_start_nb_32                                     : unsigned(31 downto 0);
  -- final timestamp fields
-  signal full_timestamp                                       : std_logic_vector(127 downto 0);
  signal metadata, utc, coarse_time, fine_time                : std_logic_vector(31 downto 0);
  -- coarse time calculations
  signal tstamp_on_first_retrig_case1                         : std_logic;
@@ -143,8 +142,6 @@ architecture rtl of data_formatting is
  signal previous_utc                                         : std_logic_vector(31 downto 0);
  signal timestamp_valid_int                                  : std_logic;
-  signal raw_seq : unsigned(27 downto 0);
  signal fake_cnt_coarse : unsigned(27 downto 0);
  signal fake_cnt_period : unsigned(27 downto 0);
  signal fake_cnt_tai    : unsigned(31 downto 0);
@@ -152,12 +149,13 @@ architecture rtl of data_formatting is
  signal timestamp_valid_int_d : std_logic;
+  signal raw_ts, raw_ts_d : t_raw_acam_timestamp;
 --=================================================================================================
 --                                       architecture begin
 --=================================================================================================
 begin
  p_gen_timestamp_valid : process (clk_i)
  begin
    if rising_edge (clk_i) then
@@ -225,6 +223,26 @@ begin
    end if;
  end process;
+  p_tstamp_raw_latch : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if timestamp_valid_int = '1' then
+        raw_ts.seconds       <= utc_i;
+        raw_ts.acam_bins     <= acam_fine_timestamp;
+        raw_ts.acam_start_nb <= std_logic_vector(acam_start_nb);
+        raw_ts.slope         <= acam_slope;
+        raw_ts.channel       <= acam_channel;
+        raw_ts.roll_over_incr_recent <= roll_over_incr_recent_i;
+        raw_ts.clk_i_cycles_offset <= clk_i_cycles_offset_i(7 downto 0);
+        raw_ts.roll_over_nb <= roll_over_nb_i(15 downto 0);
+        raw_ts.retrig_nb_offset <= retrig_nb_offset_i(8 downto 0);
+        raw_ts.current_retrig_nb <= current_retrig_nb_i(8 downto 0);
+      end if;
+      raw_ts_d <= raw_ts;
+    end if;
+  end process;
  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  reg_info_of_previous_sec : process (clk_i)
  begin
@@ -344,11 +362,6 @@ begin
              acam_slope & roll_over_incr_recent_i & acam_channel;  -- 5 LSbits used for slope and acam_channel
  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  full_timestamp(31 downto 0)   <= fine_time;
-  full_timestamp(63 downto 32)  <= coarse_time;
-  full_timestamp(95 downto 64)  <= utc;
-  full_timestamp(127 downto 96) <= metadata;
  process(clk_i)
@@ -382,7 +395,6 @@ begin
  begin
    if rising_edge(clk_i) then
      if rst_i = '1' then
-        raw_seq <= (others => '0');
      else
        if(gen_fake_ts_enable_i = '1' and fake_ts_valid = '1')then
          timestamp_o.slope   <= '1';
@@ -390,18 +402,17 @@ begin
          timestamp_o.n_bins  <= (others => '0');
          timestamp_o.coarse  <= std_logic_vector(resize(fake_cnt_coarse, 32));
          timestamp_o.tai     <= std_logic_vector(fake_cnt_tai);
-          timestamp_o.seq     <= std_logic_vector(raw_seq);
          timestamp_valid_o   <= '1';
-          raw_seq             <= raw_seq + 1;
        elsif(timestamp_valid_int_d = '1') then
+          timestamp_o.raw <= raw_ts_d;
          timestamp_o.slope   <= acam_slope;
          timestamp_o.channel <= acam_channel;
          timestamp_o.n_bins  <= fine_time(16 downto 0);
          timestamp_o.coarse  <= coarse_time;
-          timestamp_o.tai     <= utc; 
+          timestamp_o.tai     <= utc(31 downto 0);
-          timestamp_o.seq     <= std_logic_vector(raw_seq);
+          timestamp_o.meta <= x"000" & std_logic_vector(acam_start_nb(6 downto 0)) & fine_time(12 downto 0);
          timestamp_valid_o   <= '1';
-          raw_seq             <= raw_seq + 1;
        else
          timestamp_valid_o <= '0';
        end if;