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FMC TDC 1ns 5cha - Gateware
Commit 7bb56989 authored by egousiou's avatar egousiou
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added missing ip_cores:-/

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hdl/ip_cores/common/gc_big_adder.vhd 0 → 100644
View file @ 7bb56989
--! @file gc_big_adder.vhd
--! @brief Formerly eca_adder.vhd A pipelined adder for fast and wide arithmetic
--! @author Wesley W. Terpstra <w.terpstra@gsi.de>
--!
--! Copyright (C) 2013 GSI Helmholtz Centre for Heavy Ion Research GmbH
--!
--! The pipeline has three stages: partial sum, propogate carry, full sum
--! The inputs should be registers.
--! The outputs are provided at the end of each stage and should be registered.
--! The high carry bit is available one pipeline stage earlier than the full sum.
--! The high carry bit can be used to implement a comparator.
--!
--------------------------------------------------------------------------------
-- Renamed and moved to common -Mathias Kreider
--
--! This library is free software; you can redistribute it and/or
--! modify it under the terms of the GNU Lesser General Public
--! License as published by the Free Software Foundation; either
--! version 3 of the License, or (at your option) any later version.
--!
--! This library is distributed in the hope that it will be useful,
--! but WITHOUT ANY WARRANTY; without even the implied warranty of
--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--! Lesser General Public License for more details.
--!
--! You should have received a copy of the GNU Lesser General Public
--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
-- Expects registers for inputs. Async outputs.
-- c1_o is available after 1 cycle (2 once registered)
-- c2_o, x2_o are available after 2 cycles (3 once registered)
entity gc_big_adder is
generic(
g_data_bits : natural := 64;
g_parts : natural := 4);
port(
clk_i : in std_logic;
stall_i : in std_logic := '0';
a_i : in std_logic_vector(g_data_bits-1 downto 0);
b_i : in std_logic_vector(g_data_bits-1 downto 0);
c_i : in std_logic := '0';
c1_o : out std_logic;
x2_o : out std_logic_vector(g_data_bits-1 downto 0);
c2_o : out std_logic);
end gc_big_adder;
architecture rtl of gc_big_adder is
-- Out of principle, tell quartus to leave my design alone.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_parts : natural := g_parts; -- Must divide g_data_bits
constant c_sub_bits : natural := g_data_bits / c_parts;
subtype t_part is std_logic_vector(c_sub_bits-1 downto 0);
subtype t_carry is std_logic_vector(c_parts -1 downto 0);
type t_part_array is array(c_parts-1 downto 0) of t_part;
constant c_zeros : t_part := (others => '0');
-- Pipeline:
-- s1: partial sums / prop+gen
-- s2: carry bits
-- s3: full sum
-- Registers
signal r1_sum0 : t_part_array;
--signal r1_sum1 : t_part_array;
signal r1_p : t_carry;
signal r1_g : t_carry;
signal r1_c : std_logic;
signal r2_sum0 : t_part_array;
--signal r2_sum1 : t_part_array;
signal r2_c : t_carry;
signal r2_cH : std_logic;
-- Signals
signal s1_r : std_logic_vector(c_parts downto 0);
begin
s1_r <= f_big_ripple(r1_p, r1_g, r1_c);
main : process(clk_i) is
variable sum0, sum1 : std_logic_vector(c_sub_bits downto 0);
begin
if rising_edge(clk_i) then
if stall_i = '0' then
for i in 0 to c_parts-1 loop
sum0 := f_big_ripple(a_i((i+1)*c_sub_bits-1 downto i*c_sub_bits),
b_i((i+1)*c_sub_bits-1 downto i*c_sub_bits), '0');
sum1 := f_big_ripple(a_i((i+1)*c_sub_bits-1 downto i*c_sub_bits),
b_i((i+1)*c_sub_bits-1 downto i*c_sub_bits), '1');
r1_sum0(i) <= sum0(c_sub_bits-1 downto 0);
--r1_sum1(i) <= sum1(c_sub_bits-1 downto 0);
r1_g(i) <= sum0(c_sub_bits);
r1_p(i) <= sum1(c_sub_bits);
end loop;
r1_c <= c_i;
r2_c <= s1_r(c_parts-1 downto 0) xor (r1_p xor r1_g);
r2_cH <= s1_r(c_parts);
r2_sum0 <= r1_sum0;
--r2_sum1 <= r1_sum1;
end if;
end if;
end process;
c1_o <= s1_r(c_parts);
c2_o <= r2_cH;
output : for i in 0 to c_parts-1 generate
-- save the sum1 registers by using an adder instead of MUX
x2_o((i+1)*c_sub_bits-1 downto i*c_sub_bits) <=
f_big_ripple(r2_sum0(i), c_zeros, r2_c(i))
(c_sub_bits-1 downto 0);
-- r2_sum1(i) when r2_c(i)='1' else r2_sum0(i);
end generate;
end rtl;
hdl/ip_cores/common/gc_fsm_watchdog.vhd 0 → 100644
View file @ 7bb56989
--==============================================================================
-- CERN (BE-CO-HT)
-- Finite State Machine Watchdog Timer
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-11-22
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-11-22 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity gc_fsm_watchdog is
generic
(
-- Maximum value of watchdog timer in clk_i cycles
g_wdt_max : positive := 65535
);
port
(
-- Clock and active-low reset line
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Active-high watchdog timer reset line, synchronous to clk_i
wdt_rst_i : in std_logic;
-- Active-high reset output, synchronous to clk_i
fsm_rst_o : out std_logic
);
end entity gc_fsm_watchdog;
architecture behav of gc_fsm_watchdog is
--============================================================================
-- Signal declarations
--============================================================================
signal wdt : unsigned(f_log2_size(g_wdt_max)-1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Watchdog timer process
--============================================================================
p_wdt : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (wdt_rst_i = '1') then
wdt <= (others => '0');
fsm_rst_o <= '0';
else
wdt <= wdt + 1;
if (wdt = g_wdt_max-1) then
fsm_rst_o <= '1';
end if;
end if;
end if;
end process p_wdt;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/ip_cores/common/gc_glitch_filt.vhd 0 → 100644
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--==============================================================================
-- CERN (BE-CO-HT)
-- Glitch filter with selectable length
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-12
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-12 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity gc_glitch_filt is
generic
(
-- Length of glitch filter:
-- g_len = 1 => data width should be > 1 clk_i cycle
-- g_len = 2 => data width should be > 2 clk_i cycle
-- etc.
g_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data input
dat_i : in std_logic;
-- Data output
-- latency: g_len+1 clk_i cycles
dat_o : out std_logic
);
end entity gc_glitch_filt;
architecture behav of gc_glitch_filt is
--============================================================================
-- Signal declarations
--============================================================================
signal glitch_filt : std_logic_vector(g_len downto 0);
signal dat_synced : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Glitch filtration logic
--============================================================================
-- First, synchronize the data input in the clk_i domain
cmp_sync : gc_sync_ffs
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => dat_i,
synced_o => dat_synced,
npulse_o => open,
ppulse_o => open
);
-- Then, assign the current sample of the glitch filter
glitch_filt(0) <= dat_synced;
-- Generate glitch filter FFs when the filter length is > 0
gen_glitch_filt: if (g_len > 0) generate
p_glitch_filt: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
glitch_filt(g_len downto 1) <= (others => '0');
else
glitch_filt(g_len downto 1) <= glitch_filt(g_len-1 downto 0);
end if;
end if;
end process p_glitch_filt;
end generate gen_glitch_filt;
-- and set the data output based on the state of the glitch filter
p_output: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
dat_o <= '0';
elsif (glitch_filt = (glitch_filt'range => '1')) then
dat_o <= '1';
elsif (glitch_filt = (glitch_filt'range => '0')) then
dat_o <= '0';
end if;
end if;
end process p_output;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/ip_cores/common/gc_i2c_slave.vhd 0 → 100644
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hdl/ip_cores/common/gc_pulse_synchronizer2.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Title : Pulse synchronizer
-- Project : General Cores Library
-------------------------------------------------------------------------------
-- File : gc_pulse_synchronizer2.vhd
-- Author : Tomasz Wlostowski, Wesley Terpstra
-- Company : CERN BE-CO-HT
-- Created : 2012-01-10
-- Last update: 2012-08-29
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Full feedback pulse synchronizer (works independently of the
-- input/output clock domain frequency ratio)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-01-12 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencores_pkg.all;
entity gc_pulse_synchronizer2 is
port (
-- pulse input clock
clk_in_i : in std_logic;
rst_in_n_i : in std_logic;
-- pulse output clock
clk_out_i : in std_logic;
rst_out_n_i : in std_logic;
-- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
-- correctly transferred to q_p_o.
d_ready_o : out std_logic;
-- pulse input (clk_in_i domain)
d_p_i : in std_logic;
-- pulse output (clk_out_i domain)
q_p_o : out std_logic);
end gc_pulse_synchronizer2;
architecture rtl of gc_pulse_synchronizer2 is
constant c_sync_stages : integer := 3;
signal ready, d_p_d0 : std_logic;
signal in_ext, out_ext : std_logic;
signal out_feedback : std_logic;
signal d_in2out : std_logic_vector(c_sync_stages-1 downto 0);
signal d_out2in : std_logic_vector(c_sync_stages-1 downto 0);
begin -- rtl
process(clk_out_i, rst_out_n_i)
begin
if rst_out_n_i = '0' then
d_in2out <= (others => '0');
out_ext <= '0';
elsif rising_edge(clk_out_i) then
d_in2out <= d_in2out(c_sync_stages-2 downto 0) & in_ext;
out_ext <= d_in2out(c_sync_stages-1);
end if;
end process;
process(clk_in_i, rst_in_n_i)
begin
if rst_in_n_i = '0' then
d_out2in <= (others => '0');
elsif rising_edge(clk_in_i) then
d_out2in <= d_out2in(c_sync_stages-2 downto 0) & out_ext;
end if;
end process;
out_feedback <= d_out2in(c_sync_stages-1);
p_input_ack : process(clk_in_i, rst_in_n_i)
begin
if rst_in_n_i = '0' then
ready <= '1';
in_ext <= '0';
d_p_d0 <= '0';
elsif rising_edge(clk_in_i) then
d_p_d0 <= d_p_i;
if(ready = '1' and d_p_i = '1' and d_p_d0 = '0') then
in_ext <= not in_ext;
ready <= '0';
elsif(in_ext = out_feedback) then
ready <= '1';
end if;
end if;
end process;
p_drive_output : process(clk_out_i, rst_out_n_i)
begin
if rst_out_n_i = '0' then
q_p_o <= '0';
elsif rising_edge(clk_out_i) then
q_p_o <= out_ext xor d_in2out(c_sync_stages-1);
end if;
end process;
d_ready_o <= ready;
end rtl;
hdl/ip_cores/genrams/.gitignore 0 → 100644
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coregen_ip
\ No newline at end of file
hdl/ip_cores/genrams/Manifest.py 0 → 100644
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files = [
"genram_pkg.vhd",
"memory_loader_pkg.vhd",
"generic_shiftreg_fifo.vhd",
"inferred_sync_fifo.vhd",
"inferred_async_fifo.vhd"];
if (target == "altera"):
modules = {"local" : "altera"}
elif (target == "xilinx" and syn_device[0:4].upper()=="XC6V"):
modules = {"local" : ["xilinx", "xilinx/virtex6"]}
elif (target == "xilinx"):
modules = {"local" : ["xilinx", "generic"]}
hdl/ip_cores/genrams/altera/Manifest.py 0 → 100644
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files = [
"generic_async_fifo.vhd",
"generic_simple_dpram.vhd",
"generic_dpram.vhd",
"generic_spram.vhd",
"generic_sync_fifo.vhd",
"gc_shiftreg.vhd"]
hdl/ip_cores/genrams/altera/gc_shiftreg.vhd 0 → 100644
View file @ 7bb56989
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.genram_pkg.all;
entity gc_shiftreg is
generic (
g_size : integer);
port (
clk_i : in std_logic;
en_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0));
end gc_shiftreg;
architecture rtl of gc_shiftreg is
signal a : std_logic_vector(4 downto 0);
signal sr : std_logic_vector(g_size-1 downto 0);
begin
a <= std_logic_vector(resize(unsigned(a_i), 5));
p_srl : process(clk_i)
begin
if rising_edge(clk_i) then
if en_i = '1' then
sr <= sr(sr'left - 1 downto 0) & d_i;
end if;
end if;
end process;
q_o <= sr(TO_INTEGER(unsigned(a_i)));
end rtl;
hdl/ip_cores/genrams/altera/generic_async_fifo.vhd 0 → 100644
View file @ 7bb56989
-------------------------------------------------------------------------------
-- Title : Parametrizable asynchronous FIFO (Altera version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_async_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2011-01-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual-clock asynchronous FIFO.
-- - configurable data width and size
-- - "show ahead" mode
-- - configurable full/empty/almost full/almost empty/word count signals
-- Todo:
-- - optimize almost empty / almost full flags generation for speed
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
use work.genram_pkg.all;
entity generic_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_rd_empty : boolean := true; -- with empty flag
g_with_rd_full : boolean := false; -- with full flag
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; -- with words counter
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
-- write port
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- read port
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end generic_async_fifo;
architecture syn of generic_async_fifo is
component dcfifo
generic (
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
rdsync_delaypipe : natural;
underflow_checking : string;
use_eab : string;
read_aclr_synch : string;
write_aclr_synch : string;
wrsync_delaypipe : natural
);
port (
wrclk : in std_logic;
rdempty : out std_logic;
wrempty : out std_logic;
rdreq : in std_logic;
aclr : in std_logic;
rdfull : out std_logic;
wrfull : out std_logic;
rdclk : in std_logic;
q : out std_logic_vector (g_data_width-1 downto 0);
wrreq : in std_logic;
data : in std_logic_vector (g_data_width-1 downto 0);
wrusedw : out std_logic_vector (f_log2_size(g_size)-1 downto 0);
rdusedw : out std_logic_vector (f_log2_size(g_size)-1 downto 0)
);
end component;
function f_bool_2_string (x : boolean) return string is
begin
if(x) then
return "ON";
else
return "OFF";
end if;
end f_bool_2_string;
signal rdempty : std_logic;
signal wrempty : std_logic;
signal aclr : std_logic;
signal rdfull : std_logic;
signal wrfull : std_logic;
signal wrusedw : std_logic_vector (f_log2_size(g_size)-1 downto 0);
signal rdusedw : std_logic_vector (f_log2_size(g_size)-1 downto 0);
begin -- syn
aclr <= not rst_n_i;
dcfifo_inst : dcfifo
generic map (
lpm_numwords => g_size,
lpm_showahead => f_bool_2_string(g_show_ahead),
lpm_type => "dcfifo",
lpm_width => g_data_width,
lpm_widthu => f_log2_size(g_size),
overflow_checking => "ON",
rdsync_delaypipe => 5, -- 2 sync stages
underflow_checking => "ON",
use_eab => "ON",
read_aclr_synch => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 5 -- 2 sync stages
)
port map (
wrclk => clk_wr_i,
rdempty => rdempty,
wrempty => wrempty,
rdreq => rd_i,
aclr => aclr,
rdfull => rdfull,
wrfull => wrfull,
rdclk => clk_rd_i,
q => q_o,
wrreq => we_i,
data => d_i,
wrusedw => wrusedw,
rdusedw => rdusedw);
wr_count_o <= wrusedw;
rd_count_o <= rdusedw;
wr_empty_o <= wrempty;
rd_empty_o <= rdempty;
wr_full_o <= wrfull;
rd_full_o <= rdfull;
wr_almost_empty_o <= '1' when unsigned(wrusedw) < to_unsigned(g_almost_empty_threshold, wrusedw'length) else '0';
rd_almost_empty_o <= '1' when unsigned(rdusedw) < to_unsigned(g_almost_empty_threshold, rdusedw'length) else '0';
wr_almost_full_o <= '1' when unsigned(wrusedw) > to_unsigned(g_almost_full_threshold, wrusedw'length) else '0';
rd_almost_full_o <= '1' when unsigned(rdusedw) > to_unsigned(g_almost_full_threshold,rdusedw'length) else '0';
end syn;
hdl/ip_cores/genrams/altera/generic_dpram.vhd 0 → 100644
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hdl/ip_cores/genrams/altera/generic_simple_dpram.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Altera version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_simple_dpram.vhd
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-03-04
-- Last update: 2013-03-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Simple dual-port synchronous RAM for Altera FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-------------------------------------------------------------------------------
-- Copyright (c) 2013 GSI
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-04 1.0 wterpstra Adapted from generic_dpram.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity generic_simple_dpram is
generic(
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_dual_clock : boolean := true);
port(
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_simple_dpram;
architecture syn of generic_simple_dpram is
function f_diffport_order(x : string) return string is
begin
if x = "read_first" then
return "OLD_DATA";
elsif x = "write_first" then
return "DONT_CARE"; -- "NEW_DATA" is unsupported; we use a bypass MUX in this case
elsif x = "dont_care" then
return "DONT_CARE";
else
assert (false) report "generic_simple_dpram: g_addr_conflict_resolution must be: read_first, write_first, dont_care" severity failure;
return "DONT_CARE";
end if;
end f_diffport_order;
function f_filename(x : string) return string is
begin
if x'length = 0 or x = "none" then
return "UNUSED";
else
return x;
end if;
end f_filename;
constant c_num_bytes : integer := (g_data_width+7)/8;
constant c_addr_width : integer := f_log2_size(g_size);
constant diffport_order : string := f_diffport_order(g_addr_conflict_resolution);
constant c_init_file : string := f_filename(g_init_file);
signal qb : std_logic_vector(g_data_width-1 downto 0);
signal da : std_logic_vector(g_data_width-1 downto 0);
signal nbb : boolean;
begin
assert (g_addr_conflict_resolution /= "write_first" or (g_dual_clock = false and g_with_byte_enable = false))
report "generic_simple_dpram: write_first is only possible when dual_clock and g_with_byte_enable are false"
severity failure;
assert (g_addr_conflict_resolution /= "read_first" or g_dual_clock = false)
report "generic_simple_dpram: read_first is only possible when dual_clock is false"
severity failure;
assert (g_addr_conflict_resolution /= "write_first")
report "generic_simple_dpram: write_first requires a bypass MUX"
severity note;
case_qb_raw : if (g_addr_conflict_resolution /= "write_first") generate
qb_o <= qb;
end generate;
case_qb_bypass : if (g_addr_conflict_resolution = "write_first") generate
qb_o <= qb when nbb else da;
memoize : process(clka_i) is
begin
if rising_edge(clka_i) then
nbb <= aa_i /= ab_i or wea_i = '0';
da <= da_i;
end if;
end process;
end generate;
case_be_dual : if (g_with_byte_enable = true and g_dual_clock = true) generate
memory : altsyncram
generic map(
byte_size => 8,
numwords_a => g_size,
numwords_b => g_size,
widthad_a => c_addr_width,
widthad_b => c_addr_width,
width_a => g_data_width,
width_b => g_data_width,
width_byteena_a => c_num_bytes,
operation_mode => "DUAL_PORT",
read_during_write_mode_mixed_ports => diffport_order,
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
address_reg_b => "CLOCK1",
wrcontrol_wraddress_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
indata_reg_b => "CLOCK1",
rdcontrol_reg_b => "CLOCK1",
init_file => c_init_file)
port map(
clock0 => clka_i,
wren_a => wea_i,
address_a => aa_i,
data_a => da_i,
byteena_a => bwea_i,
clock1 => clkb_i,
address_b => ab_i,
q_b => qb);
end generate;
case_be_single : if (g_with_byte_enable = true and g_dual_clock = false) generate
memory : altsyncram
generic map(
byte_size => 8,
numwords_a => g_size,
numwords_b => g_size,
widthad_a => c_addr_width,
widthad_b => c_addr_width,
width_a => g_data_width,
width_b => g_data_width,
width_byteena_a => c_num_bytes,
operation_mode => "DUAL_PORT",
read_during_write_mode_mixed_ports => diffport_order,
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
address_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
indata_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
init_file => c_init_file)
port map(
clock0 => clka_i,
wren_a => wea_i,
address_a => aa_i,
data_a => da_i,
byteena_a => bwea_i,
address_b => ab_i,
q_b => qb);
end generate;
case_nobe_dual : if (g_with_byte_enable = false and g_dual_clock = true) generate
memory : altsyncram
generic map(
byte_size => 8,
numwords_a => g_size,
numwords_b => g_size,
widthad_a => c_addr_width,
widthad_b => c_addr_width,
width_a => g_data_width,
width_b => g_data_width,
operation_mode => "DUAL_PORT",
read_during_write_mode_mixed_ports => diffport_order,
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
address_reg_b => "CLOCK1",
wrcontrol_wraddress_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
indata_reg_b => "CLOCK1",
rdcontrol_reg_b => "CLOCK1",
init_file => c_init_file)
port map(
clock0 => clka_i,
wren_a => wea_i,
address_a => aa_i,
data_a => da_i,
clock1 => clkb_i,
address_b => ab_i,
q_b => qb);
end generate;
case_nobe_single : if (g_with_byte_enable = false and g_dual_clock = false) generate
memory : altsyncram
generic map(
byte_size => 8,
numwords_a => g_size,
numwords_b => g_size,
widthad_a => c_addr_width,
widthad_b => c_addr_width,
width_a => g_data_width,
width_b => g_data_width,
operation_mode => "DUAL_PORT",
read_during_write_mode_mixed_ports => diffport_order,
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
address_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
indata_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
init_file => c_init_file)
port map(
clock0 => clka_i,
wren_a => wea_i,
address_a => aa_i,
data_a => da_i,
address_b => ab_i,
q_b => qb);
end generate;
end syn;
hdl/ip_cores/genrams/altera/generic_spram.vhd 0 → 100644
View file @ 7bb56989
-------------------------------------------------------------------------------
-- Title : Parametrizable single-port synchronous RAM (Altera version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_spram.vhd
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2011-01-25
-- Last update: 2013-03-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Single-port synchronous RAM for Altera FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-- 2013-03-04 2.0 wterpstra Rewrote using altsyncram
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity generic_spram is
generic(
g_data_width : natural := 32;
g_size : natural := 1024;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "");
port(
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end generic_spram;
architecture syn of generic_spram is
function f_sameport_order(x : string) return string is
begin
if x = "read_first" then
return "OLD_DATA";
elsif x = "write_first" then
--return "NEW_DATA_NO_NBE_READ"; -- unwritten bytes='X'
return "NEW_DATA_WITH_NBE_READ"; -- unwritten bytes=OLD_DATA (ie: whole result = NEW_DATA)
elsif x = "dont_care" then
return "DONT_CARE";
else
assert (false) report "generic_spram: g_addr_conflict_resolution must be: read_first, write_first, dont_care" severity failure;
return "DONT_CARE";
end if;
end f_sameport_order;
function f_filename(x : string) return string is
begin
if x'length = 0 or x = "none" then
return "UNUSED";
else
return x;
end if;
end f_filename;
constant c_num_bytes : integer := (g_data_width+7)/8;
constant c_addr_width : integer := f_log2_size(g_size);
constant sameport_order : string := f_sameport_order(g_addr_conflict_resolution);
constant c_init_file : string := f_filename(g_init_file);
begin
case_be : if (g_with_byte_enable = true) generate
memory : altsyncram
generic map(
byte_size => 8,
numwords_a => g_size,
widthad_a => c_addr_width,
width_a => g_data_width,
width_byteena_a => c_num_bytes,
operation_mode => "SINGLE_PORT",
read_during_write_mode_port_a => sameport_order,
outdata_reg_a => "UNREGISTERED",
init_file => c_init_file)
port map(
clock0 => clk_i,
wren_a => we_i,
address_a => a_i,
data_a => d_i,
byteena_a => bwe_i,
q_a => q_o);
end generate;
case_nobe : if (g_with_byte_enable = false) generate
memory : altsyncram
generic map(
byte_size => 8,
numwords_a => g_size,
widthad_a => c_addr_width,
width_a => g_data_width,
operation_mode => "SINGLE_PORT",
read_during_write_mode_port_a => sameport_order,
outdata_reg_a => "UNREGISTERED",
init_file => c_init_file)
port map(
clock0 => clk_i,
wren_a => we_i,
address_a => a_i,
data_a => d_i,
q_a => q_o);
end generate;
end syn;
hdl/ip_cores/genrams/altera/generic_sync_fifo.vhd 0 → 100644
View file @ 7bb56989
-------------------------------------------------------------------------------
-- Title : Parametrizable synchronous FIFO (Altera version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_sync_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2011-01-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Single-clock FIFO.
-- - configurable data width and size
-- - "show ahead" mode
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
use work.genram_pkg.all;
entity generic_sync_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_empty : boolean := true; -- with empty flag
g_with_full : boolean := true; -- with full flag
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false; -- with words counter
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end generic_sync_fifo;
architecture syn of generic_sync_fifo is
component scfifo
generic (
add_ram_output_register : string;
almost_empty_value : natural;
almost_full_value : natural;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
underflow_checking : string;
use_eab : string);
port (
clock : in std_logic;
sclr : in std_logic;
usedw : out std_logic_vector (f_log2_size(g_size)-1 downto 0);
empty : out std_logic;
full : out std_logic;
q : out std_logic_vector (g_data_width-1 downto 0);
wrreq : in std_logic;
almost_empty : out std_logic;
almost_full : out std_logic;
data : in std_logic_vector (g_data_width-1 downto 0);
rdreq : in std_logic);
end component;
function f_bool_2_string (x : boolean) return string is
begin
if(x) then
return "ON";
else
return "OFF";
end if;
end f_bool_2_string;
signal empty : std_logic;
signal almost_empty : std_logic;
signal almost_full : std_logic;
signal sclr : std_logic;
signal full : std_logic;
signal usedw : std_logic_vector (f_log2_size(g_size)-1 downto 0);
begin -- syn
sclr <= not rst_n_i;
scfifo_inst: scfifo
generic map (
add_ram_output_register => "OFF",
almost_empty_value => g_almost_empty_threshold,
almost_full_value => g_almost_full_threshold,
lpm_numwords => g_size,
lpm_showahead => f_bool_2_string(g_show_ahead),
lpm_type => "scfifo",
lpm_width => g_data_width,
lpm_widthu => f_log2_size(g_size),
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON" )
port map (
clock => clk_i,
sclr => sclr,
usedw => usedw,
empty => empty,
full => full,
q => q_o,
wrreq => we_i,
almost_empty => almost_empty,
almost_full => almost_full,
data => d_i,
rdreq => rd_i);
count_o <= usedw;
empty_o <= empty;
full_o <= full;
almost_empty_o <= almost_empty;
almost_full_o <= almost_full;
end syn;
hdl/ip_cores/genrams/generic/Manifest.py 0 → 100644
View file @ 7bb56989
files = ["generic_async_fifo.vhd",
"generic_sync_fifo.vhd"]
hdl/ip_cores/genrams/generic/generic_async_fifo.vhd 0 → 100644
View file @ 7bb56989
-------------------------------------------------------------------------------
-- Title : Parametrizable asynchronous FIFO (Generic version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_async_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-07-03
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual-clock asynchronous FIFO.
-- - configurable data width and size
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity generic_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_rd_empty : boolean := true; -- with empty flag
g_with_rd_full : boolean := false; -- with full flag
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; -- with words counter
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
-- write port
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- read port
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end generic_async_fifo;
architecture syn of generic_async_fifo is
component inferred_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_with_rd_empty : boolean;
g_with_rd_full : boolean;
g_with_rd_almost_empty : boolean;
g_with_rd_almost_full : boolean;
g_with_rd_count : boolean;
g_with_wr_empty : boolean;
g_with_wr_full : boolean;
g_with_wr_almost_empty : boolean;
g_with_wr_almost_full : boolean;
g_with_wr_count : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
begin -- syn
U_Inferred_FIFO : inferred_async_fifo
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_show_ahead => g_show_ahead,
g_with_rd_empty => g_with_rd_empty,
g_with_rd_full => g_with_rd_full,
g_with_rd_almost_empty => g_with_rd_almost_empty,
g_with_rd_almost_full => g_with_rd_almost_full,
g_with_rd_count => g_with_rd_count,
g_with_wr_empty => g_with_wr_empty,
g_with_wr_full => g_with_wr_full,
g_with_wr_almost_empty => g_with_wr_almost_empty,
g_with_wr_almost_full => g_with_wr_almost_full,
g_with_wr_count => g_with_wr_count,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold)
port map (
rst_n_i => rst_n_i,
clk_wr_i => clk_wr_i,
d_i => d_i,
we_i => we_i,
wr_empty_o => wr_empty_o,
wr_full_o => wr_full_o,
wr_almost_empty_o => wr_almost_empty_o,
wr_almost_full_o => wr_almost_full_o,
wr_count_o => wr_count_o,
clk_rd_i => clk_rd_i,
q_o => q_o,
rd_i => rd_i,
rd_empty_o => rd_empty_o,
rd_full_o => rd_full_o,
rd_almost_empty_o => rd_almost_empty_o,
rd_almost_full_o => rd_almost_full_o,
rd_count_o => rd_count_o);
end syn;
hdl/ip_cores/genrams/generic/generic_sync_fifo.vhd 0 → 100644
View file @ 7bb56989
-------------------------------------------------------------------------------
-- Title : Parametrizable synchronous FIFO (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_sync_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-07-03
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Single-clock FIFO.
-- - configurable data width and size
-- - "show ahead" mode
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity generic_sync_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_empty : boolean := true; -- with empty flag
g_with_full : boolean := true; -- with full flag
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false; -- with words counter
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer; -- threshold for almost full flag
g_register_flag_outputs : boolean := true
);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end generic_sync_fifo;
architecture syn of generic_sync_fifo is
component inferred_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_with_empty : boolean;
g_with_full : boolean;
g_with_almost_empty : boolean;
g_with_almost_full : boolean;
g_with_count : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer;
g_register_flag_outputs : boolean);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
begin -- syn
U_Inferred_FIFO : inferred_sync_fifo
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_show_ahead => g_show_ahead,
g_with_empty => g_with_empty,
g_with_full => g_with_full,
g_with_almost_empty => g_with_almost_empty,
g_with_almost_full => g_with_almost_full,
g_with_count => g_with_count,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold,
g_register_flag_outputs => g_register_flag_outputs)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => d_i,
we_i => we_i,
q_o => q_o,
rd_i => rd_i,
empty_o => empty_o,
full_o => full_o,
almost_empty_o => almost_empty_o,
almost_full_o => almost_full_o,
count_o => count_o);
end syn;
hdl/ip_cores/genrams/xilinx/Manifest.py 0 → 100644
View file @ 7bb56989
files = [
"generic_dpram.vhd",
"generic_dpram_sameclock.vhd",
"generic_dpram_dualclock.vhd",
"generic_simple_dpram.vhd",
"generic_spram.vhd",
"gc_shiftreg.vhd"]
hdl/ip_cores/genrams/xilinx/gc_shiftreg.vhd 0 → 100644
View file @ 7bb56989
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.genram_pkg.all;
entity gc_shiftreg is
generic (
g_size : integer);
port (
clk_i : in std_logic;
en_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0));
end gc_shiftreg;
architecture wrapper of gc_shiftreg is
component SRLC32E
port (
Q : out std_ulogic;
A : in std_logic_vector (4 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
D : in std_ulogic);
end component;
signal a : std_logic_vector(4 downto 0);
signal sr : std_logic_vector(g_size-1 downto 0);
begin -- wrapper
assert (g_size <= 32) report "gc_shiftreg[xilinx]: forced SRL32 implementation can be done only for 32-bit or smaller shift registers" severity warning;
a <= std_logic_vector(resize(unsigned(a_i), 5));
gen_srl32 : if(g_size <= 32) generate
U_SRLC32 : SRLC32E
port map (
Q => q_o,
A => a,
CE => en_i,
CLK => clk_i,
D => d_i);
end generate gen_srl32;
gen_inferred : if(g_size > 32) generate
p_srl : process(clk_i)
begin
if rising_edge(clk_i) then
if en_i = '1' then
sr <= sr(sr'left - 1 downto 0) & d_i;
end if;
end if;
end process;
q_o <= sr(TO_INTEGER(unsigned(a_i)));
end generate gen_inferred;
end wrapper;
hdl/ip_cores/genrams/xilinx/generic_dpram.vhd 0 → 100644
View file @ 7bb56989
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_dpram.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-03-16
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-- 2012-03-13 1.1 wterpstra Added initial value as array
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_dpram is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true;
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_dpram;
architecture syn of generic_dpram is
component generic_dpram_sameclock
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_fail_if_file_not_found : boolean);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram_dualclock
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_fail_if_file_not_found : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
begin
gen_single_clk : if(g_dual_clock = false) generate
U_RAM_SC: generic_dpram_sameclock
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_fail_if_file_not_found => g_fail_if_file_not_found)
port map (
rst_n_i => rst_n_i,
clk_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => qa_o,
bweb_i => bweb_i,
web_i => web_i,
ab_i => ab_i,
db_i => db_i,
qb_o => qb_o);
end generate gen_single_clk;
gen_dual_clk : if(g_dual_clock = true) generate
U_RAM_DC: generic_dpram_dualclock
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_fail_if_file_not_found => g_fail_if_file_not_found)
port map (
rst_n_i => rst_n_i,
clka_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => qa_o,
clkb_i => clkb_i,
bweb_i => bweb_i,
web_i => web_i,
ab_i => ab_i,
db_i => db_i,
qb_o => qb_o);
end generate gen_dual_clk;
end syn;
hdl/ip_cores/genrams/xilinx/generic_dpram_dualclock.vhd 0 → 100644
View file @ 7bb56989
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_dpram.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-03-28
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_dpram_dualclock is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_dpram_dualclock;
architecture syn of generic_dpram_dualclock is
constant c_num_bytes : integer := (g_data_width+7)/8;
type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
function f_memarray_to_ramtype(arr : t_meminit_array) return t_ram_type is
variable tmp : t_ram_type;
variable n, pos : integer;
begin
pos := 0;
while(pos < g_size)loop
n := 0;
-- avoid ISE loop iteration limit
while (pos < g_size and n < 4096) loop
for i in 0 to g_data_width-1 loop
tmp(pos)(i) := arr(pos, i);
end loop; -- i
n := n+1;
pos := pos + 1;
end loop;
end loop;
return tmp;
end f_memarray_to_ramtype;
function f_file_contents return t_meminit_array is
begin
return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
end f_file_contents;
shared variable ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_a : std_logic_vector(g_data_width-1 downto 0);
signal s_we_b : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_b : std_logic_vector(g_data_width-1 downto 0);
signal clka_int : std_logic;
signal clkb_int : std_logic;
signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
begin
wea_rep <= (others => wea_i);
web_rep <= (others => web_i);
s_we_a <= bwea_i and wea_rep;
s_we_b <= bweb_i and web_rep;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process (clka_i)
begin
if rising_edge(clka_i) then
qa_o <= ram(to_integer(unsigned(aa_i)));
for i in 0 to c_num_bytes-1 loop
if s_we_a(i) = '1' then
ram(to_integer(unsigned(aa_i)))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
end process;
process (clkb_i)
begin
if rising_edge(clkb_i) then
qb_o <= ram(to_integer(unsigned(ab_i)));
for i in 0 to c_num_bytes-1 loop
if s_we_b(i) = '1' then
ram(to_integer(unsigned(ab_i)))((i+1)*8-1 downto i*8)
:= db_i((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
end process;
end generate gen_with_byte_enable_readfirst;
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process(clka_i)
begin
if rising_edge(clka_i) then
qa_o <= ram(to_integer(unsigned(aa_i)));
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
end if;
end if;
end process;
process(clkb_i)
begin
if rising_edge(clkb_i) then
qb_o <= ram(to_integer(unsigned(ab_i)));
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
end if;
end if;
end process;
end generate gen_without_byte_enable_readfirst;
gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
process(clka_i)
begin
if rising_edge(clka_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
qa_o <= da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
end if;
end process;
process(clkb_i)
begin
if rising_edge(clkb_i) then
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
qb_o <= db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_writefirst;
gen_without_byte_enable_nochange : if(g_with_byte_enable = false and g_addr_conflict_resolution = "no_change") generate
process(clka_i)
begin
if rising_edge(clka_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
end if;
end process;
process(clkb_i)
begin
if rising_edge(clkb_i) then
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_nochange;
end syn;
hdl/ip_cores/genrams/xilinx/generic_dpram_sameclock.vhd 0 → 100644
View file @ 7bb56989
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_dpram_sameclock.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-07-09
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_dpram_sameclock is
generic (
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clk_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_dpram_sameclock;
architecture syn of generic_dpram_sameclock is
constant c_num_bytes : integer := (g_data_width+7)/8;
type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
function f_memarray_to_ramtype(arr : t_meminit_array) return t_ram_type is
variable tmp : t_ram_type;
variable n, pos : integer;
begin
pos := 0;
while(pos < g_size)loop
n := 0;
-- avoid ISE loop iteration limit
while (pos < g_size and n < 4096) loop
for i in 0 to g_data_width-1 loop
tmp(pos)(i) := arr(pos, i);
end loop; -- i
n := n+1;
pos := pos + 1;
end loop;
end loop;
return tmp;
end f_memarray_to_ramtype;
function f_file_contents return t_meminit_array is
begin
return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
end f_file_contents;
shared variable ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_a : std_logic_vector(g_data_width-1 downto 0);
signal s_we_b : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_b : std_logic_vector(g_data_width-1 downto 0);
signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
function f_check_bounds(x : integer; minx : integer; maxx : integer) return integer is
begin
if(x < minx) then
return minx;
elsif(x > maxx) then
return maxx;
else
return x;
end if;
end f_check_bounds;
begin
wea_rep <= (others => wea_i);
web_rep <= (others => web_i);
s_we_a <= bwea_i and wea_rep;
s_we_b <= bweb_i and web_rep;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process (clk_i)
begin
if rising_edge(clk_i) then
qa_o <= ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
qb_o <= ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
for i in 0 to c_num_bytes-1 loop
if s_we_a(i) = '1' then
ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
end if;
if(s_we_b(i) = '1') then
ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := db_i((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
end process;
end generate gen_with_byte_enable_readfirst;
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process(clk_i)
begin
if rising_edge(clk_i) then
qa_o <= ram(to_integer(unsigned(aa_i)));
qb_o <= ram(to_integer(unsigned(ab_i)));
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
end if;
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
end if;
end if;
end process;
end generate gen_without_byte_enable_readfirst;
gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
qa_o <= da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
qb_o <= db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_writefirst;
gen_without_byte_enable_nochange : if(g_with_byte_enable = false and g_addr_conflict_resolution = "no_change") generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_nochange;
end syn;
hdl/ip_cores/genrams/xilinx/generic_simple_dpram.vhd 0 → 100644
View file @ 7bb56989
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_simple_dpram.vhd
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-03-04
-- Last update: 2013-10-30
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-04 1.0 wterpstra Initial version: wrapper to generic_dpram
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_simple_dpram is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true;
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_simple_dpram;
architecture syn of generic_simple_dpram is
begin
-- Works well enough until a Xilinx guru can optimize it.
true_dp : generic_dpram
generic map(
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_dual_clock => g_dual_clock)
port map(
rst_n_i => rst_n_i,
clka_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => open,
clkb_i => clkb_i,
bweb_i => f_zeros((g_data_width+7)/8),
web_i => '0',
ab_i => ab_i,
db_i => f_zeros(g_data_width),
qb_o => qb_o);
end syn;
hdl/ip_cores/genrams/xilinx/generic_spram.vhd 0 → 100644
View file @ 7bb56989
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
entity generic_spram is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 1024;
-- if true, the user can write individual bytes by using bwe_i
g_with_byte_enable : boolean := false;
-- RAM read-on-write conflict resolution. Can be "read_first" (read-then-write)
-- or "write_first" (write-then-read)
g_addr_conflict_resolution : string := "write_first";
g_init_file : string := ""
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- byte write enable, actiwe when g_
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
-- global write enable (masked by bwe_i if g_with_byte_enable = true)
we_i : in std_logic;
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data input
d_i : in std_logic_vector(g_data_width-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_spram;
architecture syn of generic_spram is
constant c_num_bytes : integer := (g_data_width+7)/8;
type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
type t_string_file_type is file of string;
impure function f_bitstring_2_slv(s : string; num_bits : integer) return std_logic_vector is
begin
end function f_bitstring_2_slv;
impure function f_load_from_file(file_name : string) return t_ram_type is
file f : t_string_file_type;
variable fstatus : file_open_status;
begin
file_open(fstatus, f, file_name, read_mode);
if(fstatus /= open_ok) then
report "generic_spram: Cannot open memory initialization file: " & file_name severity failure;
end if;
end function f_load_from_file;
signal ram : t_ram_type;
signal s_we : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in : std_logic_vector(g_data_width-1 downto 0);
signal s_ram_out : std_logic_vector(g_data_width-1 downto 0);
begin
assert (g_init_file = "" or g_init_file = "none")
report "generic_spram: Memory initialization files not supported yet. Sorry :("
severity failure;
gen_with_byte_enable_writefirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "write_first") generate
s_we <= bwe_i when we_i = '1' else (others => '0');
process(s_we, d_i)
begin
for i in 0 to c_num_bytes-1 loop
if s_we(i) = '1' then
s_ram_in(8*i+7 downto 8*i) <= d_i(8*i+7 downto 8*i);
s_ram_out(8*i+7 downto 8*i) <= d_i(8*i+7 downto 8*i);
else
s_ram_in(8*i+7 downto 8*i) <= ram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
s_ram_out(8*i+7 downto 8*i) <= ram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
end if;
end loop; -- i
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
ram(conv_integer(unsigned(a_i))) <= s_ram_in;
q_o <= s_ram_out;
end if;
end process;
end generate gen_with_byte_enable_writefirst;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
s_we <= bwe_i when we_i = '1' else (others => '0');
process(s_we, d_i)
begin
for i in 0 to c_num_bytes-1 loop
if (s_we(i) = '1') then
s_ram_in(8*i+7 downto 8*i) <= d_i(8*i+7 downto 8*i);
else
s_ram_in(8*i+7 downto 8*i) <= ram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
end if;
end loop;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
ram(conv_integer(unsigned(a_i))) <= s_ram_in;
q_o <= ram(conv_integer(unsigned(a_i)));
end if;
end process;
end generate gen_with_byte_enable_readfirst;
gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(we_i = '1') then
ram(conv_integer(unsigned(a_i))) <= d_i;
q_o <= d_i;
else
q_o <= ram(conv_integer(unsigned(a_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_writefirst;
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(we_i = '1') then
ram(conv_integer(unsigned(a_i))) <= d_i;
end if;
q_o <= ram(conv_integer(unsigned(a_i)));
end if;
end process;
end generate gen_without_byte_enable_readfirst;
end syn;
hdl/ip_cores/genrams/xilinx/virtex6/Manifest.py 0 → 100644
View file @ 7bb56989
files =["v6_fifo_pkg.vhd", "v6_hwfifo_wrapper.vhd", "generic_async_fifo.vhd", "generic_sync_fifo.vhd"];
hdl/ip_cores/genrams/xilinx/virtex6/generic_async_fifo.vhd 0 → 100644
View file @ 7bb56989
-------------------------------------------------------------------------------
-- Title : Parametrizable asynchronous FIFO (Generic version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_async_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-07-03
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual-clock asynchronous FIFO.
-- - configurable data width and size
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.v6_fifo_pkg.all;
entity generic_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_rd_empty : boolean := true; -- with empty flag
g_with_rd_full : boolean := false; -- with full flag
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; -- with words counter
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
-- write port
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- read port
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end generic_async_fifo;
architecture syn of generic_async_fifo is
component inferred_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_with_rd_empty : boolean;
g_with_rd_full : boolean;
g_with_rd_almost_empty : boolean;
g_with_rd_almost_full : boolean;
g_with_rd_count : boolean;
g_with_wr_empty : boolean;
g_with_wr_full : boolean;
g_with_wr_almost_empty : boolean;
g_with_wr_almost_full : boolean;
g_with_wr_count : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component v6_hwfifo_wraper
generic (
g_data_width : natural;
g_size : natural;
g_dual_clock : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
clk_rd_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
wr_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
constant m : t_v6_fifo_mapping := f_v6_fifo_find_mapping(g_data_width, g_size);
begin -- syn
gen_inferred : if(m.d_width = 0 or g_with_wr_count or g_with_rd_count) generate
assert false report "generic_async_fifo[xilinx]: using inferred BRAM-based FIFO." severity note;
U_Inferred_FIFO: inferred_async_fifo
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_show_ahead => g_show_ahead,
g_with_rd_empty => g_with_rd_empty,
g_with_rd_full => g_with_rd_full,
g_with_rd_almost_empty => g_with_rd_almost_empty,
g_with_rd_almost_full => g_with_rd_almost_full,
g_with_rd_count => g_with_rd_count,
g_with_wr_empty => g_with_wr_empty,
g_with_wr_full => g_with_wr_full,
g_with_wr_almost_empty => g_with_wr_almost_empty,
g_with_wr_almost_full => g_with_wr_almost_full,
g_with_wr_count => g_with_wr_count,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold)
port map (
rst_n_i => rst_n_i,
clk_wr_i => clk_wr_i,
d_i => d_i,
we_i => we_i,
wr_empty_o => wr_empty_o,
wr_full_o => wr_full_o,
wr_almost_empty_o => wr_almost_empty_o,
wr_almost_full_o => wr_almost_full_o,
wr_count_o => wr_count_o,
clk_rd_i => clk_rd_i,
q_o => q_o,
rd_i => rd_i,
rd_empty_o => rd_empty_o,
rd_full_o => rd_full_o,
rd_almost_empty_o => rd_almost_empty_o,
rd_almost_full_o => rd_almost_full_o,
rd_count_o => rd_count_o);
end generate gen_inferred;
gen_native : if(m.d_width > 0 and not g_with_wr_count and not g_with_rd_count) generate
U_Native_FIFO: v6_hwfifo_wraper
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_dual_clock => true,
g_almost_empty_threshold => f_empty_thr(g_with_rd_almost_empty, g_almost_empty_threshold, g_size),
g_almost_full_threshold => f_empty_thr(g_with_wr_almost_full, g_almost_full_threshold, g_size))
port map (
rst_n_i => rst_n_i,
clk_wr_i => clk_wr_i,
clk_rd_i => clk_rd_i,
d_i => d_i,
we_i => we_i,
q_o => q_o,
rd_i => rd_i,
rd_empty_o => rd_empty_o,
wr_full_o => wr_full_o,
rd_almost_empty_o => rd_almost_empty_o,
wr_almost_full_o => wr_almost_full_o,
rd_count_o => rd_count_o,
wr_count_o => wr_count_o);
end generate gen_native;
end syn;
hdl/ip_cores/genrams/xilinx/virtex6/generic_sync_fifo.vhd 0 → 100644
View file @ 7bb56989
-------------------------------------------------------------------------------
-- Title : Parametrizable synchronous FIFO (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_sync_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-07-03
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Single-clock FIFO.
-- - configurable data width and size
-- - "show ahead" mode
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.genram_pkg.all;
use work.v6_fifo_pkg.all;
entity generic_sync_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_empty : boolean := true; -- with empty flag
g_with_full : boolean := true; -- with full flag
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false; -- with words counter
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer; -- threshold for almost full flag
g_register_flag_outputs : boolean := true
);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end generic_sync_fifo;
architecture syn of generic_sync_fifo is
component inferred_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_with_empty : boolean;
g_with_full : boolean;
g_with_almost_empty : boolean;
g_with_almost_full : boolean;
g_with_count : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer;
g_register_flag_outputs : boolean);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component v6_hwfifo_wraper
generic (
g_data_width : natural;
g_size : natural;
g_dual_clock : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
clk_rd_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
wr_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
constant m : t_v6_fifo_mapping := f_v6_fifo_find_mapping(g_data_width, g_size);
begin -- syn
gen_inferred : if(m.d_width = 0) generate
assert false report "generic_sync_fifo[xilinx]: using inferred BRAM-based FIFO." severity note;
U_Inferred_FIFO : inferred_sync_fifo
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_show_ahead => g_show_ahead,
g_with_empty => g_with_empty,
g_with_full => g_with_full,
g_with_almost_empty => g_with_almost_empty,
g_with_almost_full => g_with_almost_full,
g_with_count => g_with_count,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold,
g_register_flag_outputs => g_register_flag_outputs)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => d_i,
we_i => we_i,
q_o => q_o,
rd_i => rd_i,
empty_o => empty_o,
full_o => full_o,
almost_empty_o => almost_empty_o,
almost_full_o => almost_full_o,
count_o => count_o);
end generate gen_inferred;
gen_native : if(m.d_width > 0) generate
U_Native_FIFO: v6_hwfifo_wraper
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_dual_clock => false,
g_almost_empty_threshold => f_empty_thr(g_with_almost_empty, g_almost_empty_threshold, g_size),
g_almost_full_threshold => f_empty_thr(g_with_almost_full, g_almost_full_threshold, g_size))
port map (
rst_n_i => rst_n_i,
clk_wr_i => clk_i,
clk_rd_i => clk_i,
d_i => d_i,
we_i => we_i,
q_o => q_o,
rd_i => rd_i,
rd_empty_o => empty_o,
wr_full_o => full_o,
rd_almost_empty_o => almost_empty_o,
wr_almost_full_o => almost_full_o,
rd_count_o => count_o,
wr_count_o => open);
end generate gen_native;
end syn;
hdl/ip_cores/genrams/xilinx/virtex6/v6_fifo_pkg.vhd 0 → 100644
View file @ 7bb56989
package v6_fifo_pkg is
type t_v6_fifo_mapping is record
d_width : integer;
dp_width : integer;
entries : integer;
is_36 : boolean;
end record;
type t_v6_fifo_mapping_array is array(integer range <>) of t_v6_fifo_mapping;
constant c_v6_fifo_mappings : t_v6_fifo_mapping_array (0 to 9) := (
0 => (d_width => 4, dp_width => 0, entries => 4096, is_36 => false),
1 => (d_width => 8, dp_width => 1, entries => 2048, is_36 => false),
2 => (d_width => 16, dp_width => 2, entries => 1024, is_36 => false),
3 => (d_width => 32, dp_width => 4, entries => 512, is_36 => false),
4 => (d_width => 32, dp_width => 4, entries => 1024, is_36 => true),
5 => (d_width => 4, dp_width => 0, entries => 8192, is_36 => true),
6 => (d_width => 8, dp_width => 1, entries => 4096, is_36 => true),
7 => (d_width => 16, dp_width => 2, entries => 2048, is_36 => true),
8 => (d_width => 32, dp_width => 4, entries => 1024, is_36 => true),
9 => (d_width => 64, dp_width => 8, entries => 512, is_36 => true));
impure function f_v6_fifo_find_mapping
(data_width : integer; size : integer) return t_v6_fifo_mapping;
function f_v6_fifo_mode (m : t_v6_fifo_mapping) return string;
function f_empty_thr(a: boolean; thr: integer; size:integer) return integer;
end v6_fifo_pkg;
package body v6_fifo_pkg is
impure function f_v6_fifo_find_mapping
(data_width : integer; size : integer) return t_v6_fifo_mapping is
variable tmp : t_v6_fifo_mapping;
begin
for i in 0 to c_v6_fifo_mappings'length-1 loop
if(c_v6_fifo_mappings(i).d_width + c_v6_fifo_mappings(i).dp_width >= data_width and c_v6_fifo_mappings(i).entries >= size) then
return c_v6_fifo_mappings(i);
end if;
end loop;
tmp.d_width := 0;
return tmp;
end f_v6_fifo_find_mapping;
function f_v6_fifo_mode (m : t_v6_fifo_mapping) return string is
begin
if(m.d_width = 64 and m.is_36 = true) then
return "FIFO36_72";
elsif(m.d_width = 32 and m.is_36 = false) then
return "FIFO18_36";
elsif(m.is_36 = true) then
return "FIFO36";
else
return "FIFO18";
end if;
return "";
end f_v6_fifo_mode;
function f_empty_thr
(a: boolean; thr: integer; size:integer) return integer is
begin
if(a = true) then
return thr;
else
return size/2;
end if;
end f_empty_thr;
end v6_fifo_pkg;
hdl/ip_cores/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd 0 → 100644
View file @ 7bb56989
-------------------------------------------------------------------------------
-- Title : Parametrizable synchronous FIFO (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_sync_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-10-02
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Single-clock FIFO.
-- - configurable data width and size
-- - "show ahead" mode
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.genram_pkg.all;
use work.v6_fifo_pkg.all;
entity v6_hwfifo_wraper is
generic (
g_data_width : natural;
g_size : natural;
g_dual_clock : boolean;
-- Read-side flag selection
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
clk_rd_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
wr_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end v6_hwfifo_wraper;
architecture syn of v6_hwfifo_wraper is
constant m : t_v6_fifo_mapping := f_v6_fifo_find_mapping(g_data_width, g_size);
signal di_wide_18, do_wide_18 : std_logic_vector(35 downto 0);
signal di_18, do_18 : std_logic_vector(31 downto 0);
signal dip_18, dop_18 : std_logic_vector(3 downto 0);
signal di_36, do_36 : std_logic_vector(63 downto 0);
signal dip_36, dop_36 : std_logic_vector(7 downto 0);
signal di_wide_36, do_wide_36 : std_logic_vector(79 downto 0);
signal srst, srstreg : std_logic;
signal rd_ptr, wr_ptr : std_logic_vector(12 downto 0);
function f_bool_2_int (x : boolean) return integer is
begin
if(x) then
return 1;
else
return 0;
end if;
end f_bool_2_int;
function f_clamp (x : integer; min_val : integer; max_val : integer)
return integer is
begin
if(x < min_val) then
return min_val;
elsif(x > max_val) then
return max_val;
else
return x;
end if;
end f_clamp;
begin -- syn
srst <= not rst_n_i;
srstreg <= '0' when g_dual_clock = true else srst;
gen_fifo36 : if(m.is_36 and m.d_width > 0) generate
assert false report "generic_sync_fifo[xilinx]: using FIFO36E1 primitive." severity note;
di_wide_36 <= std_logic_vector(resize(unsigned(d_i), di_wide_36'length));
di_36(m.d_width-1 downto 0) <= di_wide_36(m.d_width-1 downto 0);
dip_36(m.dp_width-1 downto 0) <= di_wide_36(m.dp_width + m.d_width-1 downto m.d_width);
do_wide_36 (m.d_width-1 downto 0) <= do_36(m.d_width-1 downto 0);
do_wide_36 (m.d_width + m.dp_width-1 downto m.d_width) <= dop_36(m.dp_width-1 downto 0);
q_o <= do_wide_36(g_data_width-1 downto 0);
U_Wrapped_FIFO36 : FIFO36E1
generic map (
ALMOST_FULL_OFFSET => to_bitvector(std_logic_vector(to_unsigned(g_almost_full_threshold, 16))),
ALMOST_EMPTY_OFFSET => to_bitvector(std_logic_vector(to_unsigned(g_almost_empty_threshold, 16))),
DATA_WIDTH => m.d_width + m.dp_width,
DO_REG => f_bool_2_int(g_dual_clock),
EN_SYN => not g_dual_clock,
FIFO_MODE => f_v6_fifo_mode(m),
FIRST_WORD_FALL_THROUGH => false)
port map (
ALMOSTEMPTY => rd_almost_empty_o,
ALMOSTFULL => wr_almost_full_o,
DO => do_36,
DOP => dop_36,
EMPTY => rd_empty_o,
FULL => wr_full_o,
RDCOUNT => rd_ptr(12 downto 0),
WRCOUNT => wr_ptr(12 downto 0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
DI => di_36,
DIP => dip_36,
RDCLK => clk_rd_i,
RDEN => rd_i,
REGCE => '1',
RST => srst,
RSTREG => srstreg,
WRCLK => clk_wr_i,
WREN => we_i);
end generate gen_fifo36;
gen_fifo18 : if(not m.is_36 and m.d_width > 0) generate
di_wide_18 <= std_logic_vector(resize(unsigned(d_i), di_wide_18'length));
di_18(m.d_width-1 downto 0) <= di_wide_18(m.d_width-1 downto 0);
dip_18(m.dp_width-1 downto 0) <= di_wide_18(m.dp_width + m.d_width-1 downto m.d_width);
do_wide_18 (m.d_width-1 downto 0) <= do_18(m.d_width-1 downto 0);
do_wide_18 (m.d_width + m.dp_width-1 downto m.d_width) <= dop_18(m.dp_width-1 downto 0);
q_o <= do_wide_18(g_data_width-1 downto 0);
assert false report "generic_sync_fifo[xilinx]: using FIFO18E1 primitive [dw=" & integer'image(g_data_width) &"]." severity note;
U_Wrapped_FIFO18 : FIFO18E1
generic map (
ALMOST_FULL_OFFSET => to_bitvector(std_logic_vector(to_unsigned(f_clamp(g_almost_full_threshold, 5, 2043), 16))),
ALMOST_EMPTY_OFFSET => to_bitvector(std_logic_vector(to_unsigned(f_clamp(g_almost_empty_threshold, 5, 2043), 16))),
DATA_WIDTH => m.d_width + m.dp_width,
DO_REG => f_bool_2_int(g_dual_clock),
EN_SYN => not g_dual_clock,
FIFO_MODE => f_v6_fifo_mode(m),
FIRST_WORD_FALL_THROUGH => false)
port map (
ALMOSTEMPTY => rd_almost_empty_o,
ALMOSTFULL => wr_almost_full_o,
DO => do_18,
DOP => dop_18,
EMPTY => rd_empty_o,
FULL => wr_full_o,
RDCOUNT => rd_ptr(11 downto 0),
WRCOUNT => wr_ptr(11 downto 0),
DI => di_18,
DIP => dip_18,
RDCLK => clk_rd_i,
RDEN => rd_i,
REGCE => '1',
RST => srst,
RSTREG => srstreg,
WRCLK => clk_wr_i,
WREN => we_i);
rd_ptr(12) <= '0';
wr_ptr(12) <= '0';
end generate gen_fifo18;
gen_pointers : if(g_dual_clock = false) generate
rd_count_o <= std_logic_vector(resize(unsigned(wr_ptr) - unsigned(rd_ptr), rd_count_o'length));
wr_count_o <= std_logic_vector(resize(unsigned(wr_ptr) - unsigned(rd_ptr), wr_count_o'length));
end generate gen_pointers;
end syn;
hdl/ip_cores/wishbone/wb_async_bridge/Manifest.py 0 → 100644
View file @ 7bb56989
files = ["wb_async_bridge.vhd", "xwb_async_bridge.vhd"]
hdl/ip_cores/wishbone/wb_async_bridge/wb_async_bridge.vhd 0 → 100644
View file @ 7bb56989
------------------------------------------------------------------------------
-- Title : Atmel EBI asynchronous bus <-> Wishbone bridge
-- Project : White Rabbit Switch
------------------------------------------------------------------------------
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2011-09-23
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: An interface between AT91SAM9x-series ARM CPU External Bus Interface
-- and FPGA-internal Wishbone bus:
-- - does clock domain synchronisation
-- - provides configurable number of independent WB master ports at fixed base addresses
-- TODO:
-- - implement write queueing and read prefetching (for speed improvement)
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-05-18 1.0 twlostow Created
-- 2011-09-21 1.1 twlostow Added support for pipelined mode
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity wb_async_bridge is
generic (
g_simulation : integer := 0;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_cpu_address_width : integer := 32);
port(
rst_n_i : in std_logic; -- global reset
clk_sys_i : in std_logic; -- system clock
-------------------------------------------------------------------------------
-- Atmel EBI bus
-------------------------------------------------------------------------------
cpu_cs_n_i : in std_logic;
-- async write, active LOW
cpu_wr_n_i : in std_logic;
-- async read, active LOW
cpu_rd_n_i : in std_logic;
-- byte select, active LOW (not used due to weird CPU pin layout - NBS2 line is
-- shared with 100 Mbps Ethernet PHY)
cpu_bs_n_i : in std_logic_vector(3 downto 0);
-- address input
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
-- data bus (bidirectional)
cpu_data_b : inout std_logic_vector(31 downto 0);
-- async wait, active LOW
cpu_nwait_o : out std_logic;
-------------------------------------------------------------------------------
-- Wishbone master I/F
-------------------------------------------------------------------------------
-- wishbone master address output (m->s, common for all slaves)
wb_adr_o : out std_logic_vector(c_wishbone_address_width - 1 downto 0);
-- wishbone master data output (m->s common for all slaves)
wb_dat_o : out std_logic_vector(31 downto 0);
-- wishbone cycle strobe (m->s, common for all slaves)
wb_stb_o : out std_logic;
-- wishbone write enable (m->s, common for all slaves)
wb_we_o : out std_logic;
-- wishbone byte select output (m->s, common for all slaves)
wb_sel_o : out std_logic_vector(3 downto 0);
-- wishbone cycle select (m->s)
wb_cyc_o : out std_logic;
-- wishbone master data input (s->m)
wb_dat_i : in std_logic_vector (c_wishbone_data_width-1 downto 0);
-- wishbone ACK input (s->m)
wb_ack_i : in std_logic;
wb_stall_i : in std_logic
);
end wb_async_bridge;
architecture behavioral of wb_async_bridge is
signal rw_sel, cycle_in_progress, cs_synced, rd_pulse, wr_pulse : std_logic;
signal cpu_data_reg : std_logic_vector(31 downto 0);
signal long_cycle : std_logic;
signal wb_in : t_wishbone_master_in;
signal wb_out : t_wishbone_master_out;
begin
U_Adapter : wb_slave_adapter
generic map (
g_master_use_struct => false,
g_master_mode => g_interface_mode,
g_master_granularity => g_address_granularity,
g_slave_use_struct => true,
g_slave_mode => CLASSIC,
g_slave_granularity => WORD)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => wb_out,
slave_o => wb_in,
ma_adr_o => wb_adr_o,
ma_dat_o => wb_dat_o,
ma_sel_o => wb_sel_o,
ma_cyc_o => wb_cyc_o,
ma_stb_o => wb_stb_o,
ma_we_o => wb_we_o,
ma_dat_i => wb_dat_i,
ma_ack_i => wb_ack_i,
ma_stall_i => wb_stall_i);
gen_sync_chains_nosim : if(g_simulation = 0) generate
sync_ffs_cs : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map
(rst_n_i => rst_n_i,
clk_i => clk_sys_i,
data_i => cpu_cs_n_i,
synced_o => cs_synced,
npulse_o => open
);
sync_ffs_wr : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => rst_n_i,
clk_i => clk_sys_i,
data_i => cpu_wr_n_i,
synced_o => open,
npulse_o => wr_pulse
);
sync_ffs_rd : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => rst_n_i,
clk_i => clk_sys_i,
data_i => cpu_rd_n_i,
synced_o => open,
npulse_o => rd_pulse
);
end generate gen_sync_chains_nosim;
gen_sim : if(g_simulation = 1) generate
wr_pulse <= not cpu_wr_n_i;
rd_pulse <= not cpu_rd_n_i;
cs_synced <= cpu_cs_n_i;
end generate gen_sim;
process(clk_sys_i)
begin
if(rising_edge(clk_sys_i)) then
if(rst_n_i = '0') then
cpu_data_reg <= (others => '0');
cycle_in_progress <= '0';
rw_sel <= '0';
cpu_nwait_o <= '1';
long_cycle <= '0';
wb_out.adr <= (others => '0');
wb_out.dat <= (others => '0');
wb_out.sel <= (others => '1');
wb_out.stb <= '0';
wb_out.we <= '0';
wb_out.cyc <= '0';
else
if(cs_synced = '0') then
wb_out.adr <= std_logic_vector(resize(unsigned(cpu_addr_i), c_wishbone_address_width));
if(cycle_in_progress = '1') then
if(wb_in.ack = '1') then
if(rw_sel = '0') then
cpu_data_reg <= wb_in.dat;
end if;
cycle_in_progress <= '0';
wb_out.cyc <= '0';
wb_out.sel <= (others => '1');
wb_out.stb <= '0';
wb_out.we <= '0';
cpu_nwait_o <= '1';
long_cycle <= '0';
else
cpu_nwait_o <= not long_cycle;
long_cycle <= '1';
end if;
elsif(rd_pulse = '1' or wr_pulse = '1') then
wb_out.cyc <= '1';
wb_out.stb <= '1';
wb_out.we <= wr_pulse;
long_cycle <= '0';
rw_sel <= wr_pulse;
if(wr_pulse = '1') then
wb_out.dat <= cpu_data_b;
end if;
cycle_in_progress <= '1';
end if;
end if;
end if;
end if;
end process;
process(cpu_cs_n_i, cpu_rd_n_i, cpu_data_reg)
begin
if(cpu_cs_n_i = '0' and cpu_rd_n_i = '0') then
cpu_data_b <= cpu_data_reg;
else
cpu_data_b <= (others => 'Z');
end if;
end process;
end behavioral;
hdl/ip_cores/wishbone/wb_async_bridge/xwb_async_bridge.vhd 0 → 100644
View file @ 7bb56989
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
entity xwb_async_bridge is
generic (
g_simulation : integer := 0;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_cpu_address_width: integer := 32);
port(
rst_n_i : in std_logic; -- global reset
clk_sys_i : in std_logic; -- system clock
-------------------------------------------------------------------------------
-- Atmel EBI bus
-------------------------------------------------------------------------------
cpu_cs_n_i : in std_logic;
-- async write, active LOW
cpu_wr_n_i : in std_logic;
-- async read, active LOW
cpu_rd_n_i : in std_logic;
-- byte select, active LOW (not used due to weird CPU pin layout - NBS2 line is
-- shared with 100 Mbps Ethernet PHY)
cpu_bs_n_i : in std_logic_vector(3 downto 0);
-- address input
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
-- data bus (bidirectional)
cpu_data_b : inout std_logic_vector(31 downto 0);
-- async wait, active LOW
cpu_nwait_o : out std_logic;
-------------------------------------------------------------------------------
-- Wishbone master I/F
-------------------------------------------------------------------------------
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in
);
end xwb_async_bridge;
architecture wrapper of xwb_async_bridge is
begin
U_Wrapped_Bridge : wb_async_bridge
generic map (
g_simulation => g_simulation,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_cpu_address_width => g_cpu_address_width)
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
cpu_cs_n_i => cpu_cs_n_i,
cpu_wr_n_i => cpu_wr_n_i,
cpu_rd_n_i => cpu_rd_n_i,
cpu_bs_n_i => cpu_bs_n_i,
cpu_addr_i => cpu_addr_i,
cpu_data_b => cpu_data_b,
cpu_nwait_o => cpu_nwait_o,
wb_adr_o => master_o.adr,
wb_dat_o => master_o.dat,
wb_stb_o => master_o.stb,
wb_we_o => master_o.we,
wb_sel_o => master_o.sel,
wb_cyc_o => master_o.cyc,
wb_dat_i => master_i.dat,
wb_ack_i => master_i.ack);
end wrapper;
hdl/ip_cores/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd 0 → 100644
View file @ 7bb56989
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity xwb_bus_fanout is
generic (
g_num_outputs : natural;
g_bits_per_slave : integer := 14;
g_address_granularity : t_wishbone_address_granularity;
g_slave_interface_mode : t_wishbone_interface_mode);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
master_i : in t_wishbone_master_in_array(0 to g_num_outputs-1);
master_o : out t_wishbone_master_out_array(0 to g_num_outputs-1)
);
end xwb_bus_fanout;
architecture rtl of xwb_bus_fanout is
function f_log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + f_log2_ceil(N/2);
else
return 1 + f_log2_ceil((N+1)/2);
end if;
end;
constant c_periph_addr_bits : integer := f_log2_ceil(g_num_outputs);
signal periph_addr : std_logic_vector(c_periph_addr_bits - 1 downto 0);
signal periph_addr_reg : std_logic_vector(c_periph_addr_bits - 1 downto 0);
signal periph_sel : std_logic_vector(2**c_periph_addr_bits-1 downto 0);
signal periph_sel_reg : std_logic_vector(2**c_periph_addr_bits-1 downto 0);
signal ack_muxed : std_logic;
signal data_in_muxed : std_logic_vector(31 downto 0);
signal cycle_in_progress : std_logic;
signal ack_prev : std_logic;
signal adp_in : t_wishbone_master_in;
signal adp_out : t_wishbone_master_out;
begin -- rtl
U_Slave_Adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => g_address_granularity,
g_slave_use_struct => true,
g_slave_mode => g_slave_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => slave_i,
slave_o => slave_o,
master_i => adp_in,
master_o => adp_out);
periph_addr <= adp_out.adr(g_bits_per_slave+c_periph_addr_bits-1 downto g_bits_per_slave);
onehot_decode : process (periph_addr) -- periph_sel <= onehot_decode(periph_addr)
variable temp1 : std_logic_vector (periph_sel'high downto 0);
variable temp2 : integer range 0 to periph_sel'high;
begin
temp1 := (others => '0');
temp2 := 0;
for i in periph_addr'range loop
if (periph_addr(i) = '1') then
temp2 := 2*temp2+1;
else
temp2 := 2*temp2;
end if;
end loop;
temp1(temp2) := '1';
periph_sel <= temp1;
end process;
ACK_MUX : process (periph_addr_reg, master_i)
begin
if(to_integer(unsigned(periph_addr_reg)) < g_num_outputs) then
ack_muxed <= master_i(to_integer(unsigned(periph_addr_reg))).ack;
else
ack_muxed <= '0';
end if;
end process;
DIN_MUX : process (periph_addr_reg, master_i)
begin
if(to_integer(unsigned(periph_addr_reg))) < g_num_outputs then
data_in_muxed <= master_i(to_integer(unsigned(periph_addr_reg))).dat;
else
data_in_muxed <= (others => 'X');
end if;
end process;
p_arbitrate : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
cycle_in_progress <= '0';
ack_prev <= '0';
periph_addr_reg <= (others => '0');
periph_sel_reg <= (others => '0');
adp_in.dat <= (others => '0');
adp_in.ack <= '0';
else
periph_sel_reg <= periph_sel;
periph_addr_reg <= periph_addr;
if(cycle_in_progress = '0') then
if(adp_out.cyc = '1' and adp_in.ack = '0') then
cycle_in_progress <= '1';
end if;
ack_prev <= '0';
adp_in.ack<='0';
else
adp_in.dat <= data_in_muxed;
ack_prev <= ack_muxed;
if(ack_prev = '0' and ack_muxed = '1') then
adp_in.ack <= '1';
else
adp_in.ack <= '0';
end if;
if(ack_muxed = '1') then
cycle_in_progress <= '0';
end if;
end if;
end if;
end if;
end process;
-- adp_in.ack <= ack_prev and adp_out.stb;
gen_outputs : for i in 0 to g_num_outputs-1 generate
master_o(i).cyc <= adp_out.cyc and periph_sel(i);
master_o(i).adr <= adp_out.adr;
master_o(i).dat <= adp_out.dat;
master_o(i).stb <= adp_out.stb and not (not cycle_in_progress and ack_prev);
master_o(i).we <= adp_out.we;
master_o(i).sel <= adp_out.sel;
end generate gen_outputs;
adp_in.err <= '0';
adp_in.stall <= '0';
adp_in.rty <= '0';
end rtl;
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END
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END
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END
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files = ["wb_conmax_pri_dec.vhd", "wb_conmax_pri_enc.vhd", "wb_conmax_arb.vhd", "wb_conmax_msel.vhd",
"wbconmax_pkg.vhd", "wb_conmax_slave_if.vhd", "wb_conmax_master_if.vhd", "wb_conmax_rf.vhd",
"xwb_conmax.vhd" ];
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-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_arb.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2011-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Simple arbiter with round robin. It does not use any prioritization for
-- WB Masters.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity wb_conmax_arb is
port(
clk_i : in std_logic;
rst_i : in std_logic;
--req_i(n) <- wb_cyc from n-th Master
req_i : in std_logic_vector(7 downto 0);
next_i : in std_logic;
--which master (0 to 7) is granted
gnt_o : out std_logic_vector(2 downto 0)
);
end wb_conmax_arb;
architecture behaviour of wb_conmax_arb is
type t_arb_states is (GRANT0, GRANT1, GRANT2, GRANT3, GRANT4, GRANT5,
GRANT6, GRANT7);
signal s_state : t_arb_states;
begin
--state transitions
process(clk_i)
begin
if(clk_i'event and clk_i='1') then
if(rst_i = '1') then
s_state <= GRANT0;
else
case s_state is
when GRANT0 =>
--if this req is dropped or next is asserted, check for other req's
if(req_i(0)='0' or next_i='1') then
if ( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
end if;
end if;
when GRANT1 =>
if(req_i(1)='0' or next_i='1') then
if ( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
end if;
end if;
when GRANT2 =>
if(req_i(2)='0' or next_i='1') then
if ( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
end if;
end if;
when GRANT3 =>
if(req_i(3)='0' or next_i='1') then
if ( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
end if;
end if;
when GRANT4 =>
if(req_i(4)='0' or next_i='1') then
if ( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
end if;
end if;
when GRANT5 =>
if(req_i(5)='0' or next_i='1') then
if ( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
end if;
end if;
when GRANT6 =>
if(req_i(6)='0' or next_i='1') then
if ( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
end if;
end if;
when GRANT7 =>
if(req_i(7)='0' or next_i='1') then
if ( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
end if;
end if;
when others =>
s_state <= GRANT0;
end case;
end if;
end if;
end process;
process(s_state)
begin
case(s_state) is
when GRANT0 => gnt_o <= "000";
when GRANT1 => gnt_o <= "001";
when GRANT2 => gnt_o <= "010";
when GRANT3 => gnt_o <= "011";
when GRANT4 => gnt_o <= "100";
when GRANT5 => gnt_o <= "101";
when GRANT6 => gnt_o <= "110";
when GRANT7 => gnt_o <= "111";
when others => gnt_o <= "000";
end case;
end process;
end behaviour;
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-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_pri_dec.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Simple Master's priority encoder
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
-- (eg. <if..generate> instead of pri_out_d0 and pri_out_d1)
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity wb_conmax_pri_dec is
generic(
-- :=1 means 2 priority levels, :=2 means 4 priority levels
g_pri_sel : integer := 0
);
port(
valid_i : in std_logic;
pri_i : in std_logic_vector(1 downto 0);
pri_o : out std_logic_vector(3 downto 0)
);
end wb_conmax_pri_dec;
architecture behaviour of wb_conmax_pri_dec is
signal pri_out_d0 : std_logic_vector(3 downto 0);
signal pri_out_d1 : std_logic_vector(3 downto 0);
begin
--4 priority levels
process(valid_i,pri_i)
begin
if( valid_i='0' ) then
pri_out_d1 <= "0001";
elsif( pri_i="00" ) then
pri_out_d1 <= "0001";
elsif( pri_i="01" ) then
pri_out_d1 <= "0010";
elsif( pri_i="10" ) then
pri_out_d1 <= "0100";
else
pri_out_d1 <= "1000";
end if;
end process;
--2 priority levels
process(valid_i, pri_i)
begin
if( valid_i='0' ) then
pri_out_d0 <= "0001";
elsif( pri_i="00" ) then
pri_out_d0 <= "0001";
else
pri_out_d0 <= "0010";
end if;
end process;
--select how many pririty levels
G1: if(g_pri_sel=0) generate
pri_o <= "0000";
end generate;
G2: if(g_pri_sel=1) generate
pri_o <= pri_out_d0;
end generate;
G3: if(g_pri_sel/=0 and g_pri_sel/=1) generate
pri_o <= pri_out_d1;
end generate;
end behaviour;
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"xwb_gpio_port.vhd"];
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files = ["wb_irq_timer.vhd",
"irqm_core.vhd",
"wb_irq_lm32.vhd",
"wb_irq_slave.vhd",
"wb_irq_master.vhd",
"wb_irq_pkg.vhd"]
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hdl/ip_cores/wishbone/wb_spi_flash/Manifest.py 0 → 100644
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hdl/ip_cores/wishbone/wb_spi_flash/wb_spi_flash.vhd 0 → 100644
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hdl/ip_cores/wishbone/wb_uart/Manifest.py 0 → 100644
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hdl/ip_cores/wishbone/wb_uart/build_wb.sh 0 → 100644
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hdl/ip_cores/wishbone/wb_uart/simple_uart_pkg.vhd 0 → 100644
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hdl/ip_cores/wishbone/wb_uart/simple_uart_wb.vhd 0 → 100644
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hdl/ip_cores/wishbone/wb_uart/simple_uart_wb.wb 0 → 100644
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hdl/ip_cores/wishbone/wb_uart/uart_async_rx.vhd 0 → 100644
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hdl/ip_cores/wishbone/wb_uart/uart_async_tx.vhd 0 → 100644
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hdl/ip_cores/wishbone/wb_uart/uart_baud_gen.vhd 0 → 100644
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hdl/ip_cores/wishbone/wb_uart/uart_wb_slave.vhd 0 → 100644
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hdl/ip_cores/wishbone/wb_uart/wb_simple_uart.vhd 0 → 100644
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hdl/ip_cores/wishbone/wb_uart/xwb_simple_uart.vhd 0 → 100644
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