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FMC TDC 1ns 5cha - Gateware
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FMC TDC 1ns 5cha - Gateware
Commits
7da2ad5a
Commit
7da2ad5a
authored
Oct 15, 2018
by
Tristan Gingold
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reg_ctrl: add a register to reduce timing pressure.
parent
f1aadd5f
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27 additions
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13 deletions
+27
-13
reg_ctrl.vhd
hdl/rtl/reg_ctrl.vhd
+27
-13
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hdl/rtl/reg_ctrl.vhd
View file @
7da2ad5a
...
...
@@ -157,7 +157,8 @@ architecture rtl of reg_ctrl is
signal
acam_config
:
config_vector
;
signal
reg_adr
,
reg_adr_pipe0
:
std_logic_vector
(
7
downto
0
);
signal
starting_utc
,
acam_inputs_en
,
start_phase
:
std_logic_vector
(
g_width
-1
downto
0
);
signal
ctrl_reg
,
one_hz_phase
,
irq_tstamp_threshold
:
std_logic_vector
(
g_width
-1
downto
0
);
signal
ctrl_reg
,
ctrl_reg_d
:
std_logic_vector
(
g_width
-1
downto
0
);
signal
one_hz_phase
,
irq_tstamp_threshold
:
std_logic_vector
(
g_width
-1
downto
0
);
signal
irq_time_threshold
:
std_logic_vector
(
g_width
-1
downto
0
);
signal
clear_ctrl_reg
,
send_dac_word_p
:
std_logic
;
signal
dac_word
:
std_logic_vector
(
23
downto
0
);
...
...
@@ -429,18 +430,31 @@ begin
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- --
activate_acq_p_o
<=
ctrl_reg
(
0
);
deactivate_acq_p_o
<=
ctrl_reg
(
1
);
acam_wr_config_p_o
<=
ctrl_reg
(
2
);
acam_rdbk_config_p_o
<=
ctrl_reg
(
3
);
acam_rdbk_status_p_o
<=
ctrl_reg
(
4
);
acam_rdbk_ififo1_p_o
<=
ctrl_reg
(
5
);
acam_rdbk_ififo2_p_o
<=
ctrl_reg
(
6
);
acam_rdbk_start01_p_o
<=
ctrl_reg
(
7
);
acam_rst_p_o
<=
ctrl_reg
(
8
);
load_utc_p_o
<=
ctrl_reg
(
9
);
send_dac_word_p
<=
ctrl_reg
(
11
);
-- Delay by one cycle to reduce timing constraints.
process
(
clk_tdc_i
)
begin
if
rising_edge
(
clk_tdc_i
)
then
if
rst_tdc_i
=
'1'
then
ctrl_reg_d
<=
(
others
=>
'0'
);
else
ctrl_reg_d
<=
ctrl_reg
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- --
activate_acq_p_o
<=
ctrl_reg_d
(
0
);
deactivate_acq_p_o
<=
ctrl_reg_d
(
1
);
acam_wr_config_p_o
<=
ctrl_reg_d
(
2
);
acam_rdbk_config_p_o
<=
ctrl_reg_d
(
3
);
acam_rdbk_status_p_o
<=
ctrl_reg_d
(
4
);
acam_rdbk_ififo1_p_o
<=
ctrl_reg_d
(
5
);
acam_rdbk_ififo2_p_o
<=
ctrl_reg_d
(
6
);
acam_rdbk_start01_p_o
<=
ctrl_reg_d
(
7
);
acam_rst_p_o
<=
ctrl_reg_d
(
8
);
load_utc_p_o
<=
ctrl_reg_d
(
9
);
send_dac_word_p
<=
ctrl_reg_d
(
11
);
-- ctrl_reg bits 12 to 31 not used for the moment!
-- -- -- -- -- -- -- -- -- -- -- --
...
...
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