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FMC TDC 1ns 5cha - Gateware
Commits
8b1ee79a
Commit
8b1ee79a
authored
Feb 20, 2015
by
Tomasz Wlostowski
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Plain Diff
fixes to accommodate interface changes by Eva
parent
2d2d830b
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2 changed files
with
566 additions
and
623 deletions
+566
-623
fmc_tdc_wrapper.vhd
hdl/wr_spec_tdc/hdl/top/spec/fmc_tdc_wrapper.vhd
+12
-2
tdc_core_pkg.vhd
hdl/wr_spec_tdc/hdl/top/spec/tdc_core_pkg.vhd
+554
-621
No files found.
hdl/wr_spec_tdc/hdl/top/spec/fmc_tdc_wrapper.vhd
View file @
8b1ee79a
...
...
@@ -226,6 +226,17 @@ end fmc_tdc_wrapper;
--=================================================================================================
architecture
rtl
of
fmc_tdc_wrapper
is
component
fmc_tdc_direct_readout
is
port
(
clk_tdc_i
:
in
std_logic
;
rst_tdc_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
rst_sys_n_i
:
in
std_logic
;
direct_timestamp_i
:
in
std_logic_vector
(
127
downto
0
);
direct_timestamp_wr_i
:
in
std_logic
;
direct_slave_i
:
in
t_wishbone_slave_in
;
direct_slave_o
:
out
t_wishbone_slave_out
);
end
component
fmc_tdc_direct_readout
;
-----------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
...
...
@@ -360,7 +371,6 @@ begin
wrabbit_time_valid_i
=>
tm_time_valid_i
,
wrabbit_cycles_i
=>
tm_cycles_i
,
wrabbit_utc_i
=>
tm_tai_i
(
31
downto
0
),
wrabbit_utc_p_o
=>
open
,
-- for debug
wrabbit_clk_aux_lock_en_o
=>
tm_clk_aux_lock_en_o
,
wrabbit_clk_aux_locked_i
=>
tm_clk_aux_locked_i
,
wrabbit_clk_dmtd_locked_i
=>
'1'
,
-- FIXME: fan out real signal from the WRCore
...
...
@@ -376,7 +386,7 @@ begin
i2c_scl_o
=>
tdc_scl_out
,
i2c_sda_o
=>
tdc_sda_out
,
-- 1-Wire on TDC mezzanine
one
_
wire_b
=>
mezz_one_wire_b
,
onewire_b
=>
mezz_one_wire_b
,
direct_timestamp_o
=>
direct_timestamp
,
direct_timestamp_stb_o
=>
direct_timestamp_wr
);
...
...
hdl/wr_spec_tdc/hdl/top/spec/tdc_core_pkg.vhd
View file @
8b1ee79a
...
...
@@ -49,12 +49,10 @@
--=================================================================================================
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
-- std_logic definitions
use
IEEE
.
NUMERIC_STD
.
all
;
-- conversion functions
use
IEEE
.
STD_LOGIC_1164
.
all
;
-- std_logic definitions
use
IEEE
.
NUMERIC_STD
.
all
;
-- conversion functions
use
work
.
wishbone_pkg
.
all
;
use
work
.
genram_pkg
.
all
;
--use work.sdb_meta_pkg.all;
use
work
.
gencores_pkg
.
all
;
--=================================================================================================
...
...
@@ -76,117 +74,117 @@ package tdc_core_pkg is
-- Devices sdb description
constant
c_ONEWIRE_SDB_DEVICE
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"0000000000000007"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000602"
,
-- "WB-Onewire.Control " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-Onewire.Control "
)));
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"0000000000000007"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000602"
,
-- "WB-Onewire.Control " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-Onewire.Control "
)));
constant
c_SPEC_INFO_SDB_DEVICE
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000001F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000603"
,
-- "WB-SPEC.CSR " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-SPEC.CSR "
)));
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000001F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000603"
,
-- "WB-SPEC.CSR " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-SPEC.CSR "
)));
constant
c_TDC_EIC_DEVICE
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000000F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000605"
,
-- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-FMC-TDC.EIC "
)));
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000000F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000605"
,
-- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-FMC-TDC.EIC "
)));
constant
c_I2C_SDB_DEVICE
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000001F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000606"
,
-- "WB-I2C.Control " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-I2C.Control "
)));
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000001F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000606"
,
-- "WB-I2C.Control " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-I2C.Control "
)));
constant
c_TDC_EIC_SDB
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000000F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"26ec6086"
,
-- "WB-FMC-TDC.EIC " | md5sum | cut -c1-8
device_id
=>
x"26ec6086"
,
-- "WB-FMC-TDC.EIC " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20131204"
,
name
=>
"WB-FMC-TDC.EIC "
)));
constant
c_TDC_CONFIG_SDB_DEVICE
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"00000000000000FF"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000604"
,
-- "WB-TDC-Core-Config " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20130429"
,
name
=>
"WB-TDC-Core-Config "
)));
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"00000000000000FF"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000604"
,
-- "WB-TDC-Core-Config " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20130429"
,
name
=>
"WB-TDC-Core-Config "
)));
constant
c_TDC_MEM_SDB_DEVICE
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"0000000000000FFF"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000601"
,
-- "WB-TDC-Mem " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-TDC-Mem "
)));
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"0000000000000FFF"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000601"
,
-- "WB-TDC-Mem " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-TDC-Mem "
)));
---------------------------------------------------------------------------------------------------
...
...
@@ -204,7 +202,7 @@ package tdc_core_pkg is
-- Vector with the 11 ACAM Configuration Registers --
---------------------------------------------------------------------------------------------------
subtype
config_register
is
std_logic_vector
(
31
downto
0
);
type
config_vector
is
array
(
10
downto
0
)
of
config_register
;
type
config_vector
is
array
(
10
downto
0
)
of
config_register
;
---------------------------------------------------------------------------------------------------
...
...
@@ -213,44 +211,44 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
-- Addresses of ACAM configuration registers to be written by the PCIe host
-- corresponds to:
constant
c_ACAM_REG0_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"00"
;
-- address 0x51000 of GN4124 BAR 0
constant
c_ACAM_REG1_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"01"
;
-- address 0x51004 of GN4124 BAR 0
constant
c_ACAM_REG2_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"02"
;
-- address 0x51008 of GN4124 BAR 0
constant
c_ACAM_REG3_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"03"
;
-- address 0x5100C of GN4124 BAR 0
constant
c_ACAM_REG4_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"04"
;
-- address 0x51010 of GN4124 BAR 0
constant
c_ACAM_REG5_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"05"
;
-- address 0x51014 of GN4124 BAR 0
constant
c_ACAM_REG6_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"06"
;
-- address 0x51018 of GN4124 BAR 0
constant
c_ACAM_REG7_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"07"
;
-- address 0x5101C of GN4124 BAR 0
constant
c_ACAM_REG11_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"0B"
;
-- address 0x5102C of GN4124 BAR 0
constant
c_ACAM_REG12_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"0C"
;
-- address 0x51030 of GN4124 BAR 0
constant
c_ACAM_REG14_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"0E"
;
-- address 0x51038 of GN4124 BAR 0
-- corresponds to:
constant
c_ACAM_REG0_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"00"
;
-- address 0x51000 of GN4124 BAR 0
constant
c_ACAM_REG1_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"01"
;
-- address 0x51004 of GN4124 BAR 0
constant
c_ACAM_REG2_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"02"
;
-- address 0x51008 of GN4124 BAR 0
constant
c_ACAM_REG3_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"03"
;
-- address 0x5100C of GN4124 BAR 0
constant
c_ACAM_REG4_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"04"
;
-- address 0x51010 of GN4124 BAR 0
constant
c_ACAM_REG5_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"05"
;
-- address 0x51014 of GN4124 BAR 0
constant
c_ACAM_REG6_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"06"
;
-- address 0x51018 of GN4124 BAR 0
constant
c_ACAM_REG7_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"07"
;
-- address 0x5101C of GN4124 BAR 0
constant
c_ACAM_REG11_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"0B"
;
-- address 0x5102C of GN4124 BAR 0
constant
c_ACAM_REG12_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"0C"
;
-- address 0x51030 of GN4124 BAR 0
constant
c_ACAM_REG14_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"0E"
;
-- address 0x51038 of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Addresses of ACAM read-only registers, to be written by the ACAM and used within the core to access ACAM timestamps
constant
c_ACAM_REG8_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"08"
;
-- not accessible for writing from PCI-e
constant
c_ACAM_REG9_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"09"
;
-- not accessible for writing from PCI-e
constant
c_ACAM_REG10_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"0A"
;
-- not accessible for writing from PCI-e
constant
c_ACAM_REG8_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"08"
;
-- not accessible for writing from PCI-e
constant
c_ACAM_REG9_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"09"
;
-- not accessible for writing from PCI-e
constant
c_ACAM_REG10_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"0A"
;
-- not accessible for writing from PCI-e
---------------------------------------------------------------------------------------------------
-- Addresses of ACAM configuration readback registers, to be written by the ACAM
-- corresponds to:
constant
c_ACAM_REG0_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"10"
;
-- address 0x51040 of the GN4124 BAR 0
constant
c_ACAM_REG1_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"11"
;
-- address 0x51044 of the GN4124 BAR 0
constant
c_ACAM_REG2_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"12"
;
-- address 0x51048 of the GN4124 BAR 0
constant
c_ACAM_REG3_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"13"
;
-- address 0x5104C of the GN4124 BAR 0
constant
c_ACAM_REG4_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"14"
;
-- address 0x51050 of the GN4124 BAR 0
constant
c_ACAM_REG5_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"15"
;
-- address 0x51054 of the GN4124 BAR 0
constant
c_ACAM_REG6_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"16"
;
-- address 0x51058 of the GN4124 BAR 0
constant
c_ACAM_REG7_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"17"
;
-- address 0x5105C of the GN4124 BAR 0
constant
c_ACAM_REG8_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"18"
;
-- address 0x51060 of the GN4124 BAR 0
constant
c_ACAM_REG9_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"19"
;
-- address 0x51064 of the GN4124 BAR 0
constant
c_ACAM_REG10_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"1A"
;
-- address 0x51068 of the GN4124 BAR 0
constant
c_ACAM_REG11_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"1B"
;
-- address 0x5106C of the GN4124 BAR 0
constant
c_ACAM_REG12_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"1C"
;
-- address 0x51070 of the GN4124 BAR 0
constant
c_ACAM_REG14_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"1E"
;
-- address 0x51078 of the GN4124 BAR 0
-- corresponds to:
constant
c_ACAM_REG0_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"10"
;
-- address 0x51040 of the GN4124 BAR 0
constant
c_ACAM_REG1_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"11"
;
-- address 0x51044 of the GN4124 BAR 0
constant
c_ACAM_REG2_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"12"
;
-- address 0x51048 of the GN4124 BAR 0
constant
c_ACAM_REG3_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"13"
;
-- address 0x5104C of the GN4124 BAR 0
constant
c_ACAM_REG4_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"14"
;
-- address 0x51050 of the GN4124 BAR 0
constant
c_ACAM_REG5_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"15"
;
-- address 0x51054 of the GN4124 BAR 0
constant
c_ACAM_REG6_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"16"
;
-- address 0x51058 of the GN4124 BAR 0
constant
c_ACAM_REG7_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"17"
;
-- address 0x5105C of the GN4124 BAR 0
constant
c_ACAM_REG8_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"18"
;
-- address 0x51060 of the GN4124 BAR 0
constant
c_ACAM_REG9_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"19"
;
-- address 0x51064 of the GN4124 BAR 0
constant
c_ACAM_REG10_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"1A"
;
-- address 0x51068 of the GN4124 BAR 0
constant
c_ACAM_REG11_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"1B"
;
-- address 0x5106C of the GN4124 BAR 0
constant
c_ACAM_REG12_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"1C"
;
-- address 0x51070 of the GN4124 BAR 0
constant
c_ACAM_REG14_RDBK_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"1E"
;
-- address 0x51078 of the GN4124 BAR 0
---------------------------------------------------------------------------------------------------
...
...
@@ -259,33 +257,36 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
-- Addresses of TDC core Configuration registers to be written by the PCIe host
-- corresponds to:
constant
c_STARTING_UTC_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"20"
;
-- address 0x51080 of GN4124 BAR 0
constant
c_ACAM_INPUTS_EN_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"21"
;
-- address 0x51084 of GN4124 BAR 0
constant
c_START_PHASE_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"22"
;
-- address 0x51088 of GN4124 BAR 0
constant
c_ONE_HZ_PHASE_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"23"
;
-- address 0x5108C of GN4124 BAR 0
-- corresponds to:
constant
c_STARTING_UTC_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"20"
;
-- address 0x51080 of GN4124 BAR 0
constant
c_ACAM_INPUTS_EN_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"21"
;
-- address 0x51084 of GN4124 BAR 0
constant
c_START_PHASE_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"22"
;
-- address 0x51088 of GN4124 BAR 0
constant
c_ONE_HZ_PHASE_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"23"
;
-- address 0x5108C of GN4124 BAR 0
constant
c_IRQ_TSTAMP_THRESH_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"24"
;
-- address 0x51090 of GN4124 BAR 0
constant
c_IRQ_TIME_THRESH_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"25"
;
-- address 0x51094 of GN4124 BAR 0
constant
c_DAC_WORD_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"26"
;
-- address 0x51098 of GN4124 BAR 0
constant
c_IRQ_TSTAMP_THRESH_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"24"
;
-- address 0x51090 of GN4124 BAR 0
constant
c_IRQ_TIME_THRESH_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"25"
;
-- address 0x51094 of GN4124 BAR 0
constant
c_DAC_WORD_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"26"
;
-- address 0x51098 of GN4124 BAR 0
constant
c_DEACT_CHAN_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"27"
;
-- address 0x5109C of GN4124 BAR 0
constant
c_DEACT_CHAN_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"27"
;
-- address 0x5109C of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Addresses of TDC core Status registers to be written by the different core units
-- corresponds to:
constant
c_LOCAL_UTC_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"28"
;
-- address 0x510A0 of GN4124 BAR 0
constant
c_IRQ_CODE_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"29"
;
-- address 0x510A4 of GN4124 BAR 0
constant
c_WR_INDEX_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"2A"
;
-- address 0x510A8 of GN4124 BAR 0
constant
c_CORE_STATUS_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"2B"
;
-- address 0x510AC of GN4124 BAR 0
-- corresponds to:
constant
c_LOCAL_UTC_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"28"
;
-- address 0x510A0 of GN4124 BAR 0
constant
c_IRQ_CODE_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"29"
;
-- address 0x510A4 of GN4124 BAR 0
constant
c_WR_INDEX_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"2A"
;
-- address 0x510A8 of GN4124 BAR 0
constant
c_CORE_STATUS_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"2B"
;
-- address 0x510AC of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Addresses of the White Rabbit control and status registers
constant
c_WRABBIT_STATUS_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"2C"
;
-- address 0x510B0 of GN4124 BAR 0
constant
c_WRABBIT_CTRL_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"2D"
;
-- address 0x510B4 of GN4124 BAR 0
constant
c_WRABBIT_STATUS_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"2C"
;
-- address 0x510B0 of GN4124 BAR 0
constant
c_WRABBIT_CTRL_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"2D"
;
-- address 0x510B4 of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Address of TDC core Control register
-- corresponds to:
constant
c_CTRL_REG_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"3F"
;
-- address 0x510FC of GN4124 BAR 0
-- corresponds to:
constant
c_CTRL_REG_ADR
:
std_logic_vector
(
7
downto
0
)
:
=
x"3F"
;
-- address 0x510FC of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
...
...
@@ -296,20 +297,20 @@ package tdc_core_pkg is
-- (15+1) * acam_ref_clk = (15+1) * 32 ns
-- x"00000040" * clk_i = 64 * 8 ns
-- 512 ns
constant
c_ACAM_RETRIG_PERIOD
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000040"
;
constant
c_ACAM_RETRIG_PERIOD
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000040"
;
-- Used to multiply by 64, which is the retrigger period in clk_i cycles
constant
c_ACAM_RETRIG_PERIOD_SHIFT
:
integer
:
=
6
;
constant
c_ACAM_RETRIG_PERIOD_SHIFT
:
integer
:
=
6
;
---------------------------------------------------------------------------------------------------
-- Constants regarding TDC & SPEC LEDs --
---------------------------------------------------------------------------------------------------
constant
c_SPEC_LED_PERIOD_SIM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00004E20"
;
-- 1 ms at 20 MHz
constant
c_SPEC_LED_PERIOD_SYN
:
std_logic_vector
(
31
downto
0
)
:
=
x"01312D00"
;
-- 1 s at 20 MHz
constant
c_BLINK_LGTH_SYN
:
std_logic_vector
(
31
downto
0
)
:
=
x"00BEBC20"
;
-- 100 ms at 125 MHz
constant
c_BLINK_LGTH_SIM
:
std_logic_vector
(
31
downto
0
)
:
=
x"000004E2"
;
-- 10 us at 125 MHz
constant
c_SPEC_LED_PERIOD_SIM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00004E20"
;
-- 1 ms at 20 MHz
constant
c_SPEC_LED_PERIOD_SYN
:
std_logic_vector
(
31
downto
0
)
:
=
x"01312D00"
;
-- 1 s at 20 MHz
constant
c_BLINK_LGTH_SYN
:
std_logic_vector
(
31
downto
0
)
:
=
x"00BEBC20"
;
-- 100 ms at 125 MHz
constant
c_BLINK_LGTH_SIM
:
std_logic_vector
(
31
downto
0
)
:
=
x"000004E2"
;
-- 10 us at 125 MHz
--c_RESET_WORD
...
...
@@ -322,324 +323,311 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
-- Constants regarding the One-Wire interface --
---------------------------------------------------------------------------------------------------
constant
c_FMC_ONE
_WIRE_NB
:
integer
:
=
1
;
constant
c_FMC_ONE
WIRE_NB
:
integer
:
=
1
;
---------------------------------------------------------------------------------------------------
-- Constants regarding the Carrier CSR info --
---------------------------------------------------------------------------------------------------
constant
c_CARRIER_TYPE
:
std_logic_vector
(
15
downto
0
)
:
=
X"0001"
;
constant
c_CARRIER_TYPE
:
std_logic_vector
(
15
downto
0
)
:
=
X"0001"
;
---------------------------------------------------------------------------------------------------
-- Components Declarations
:
--
-- Components Declarations
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
component
fmc_tdc_mezzanine
is
generic
(
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
false
);
port
(
clk_sys_i
:
in
std_logic
;
rst_sys_n_i
:
in
std_logic
;
-- Signals from the clks_rsts_manager unit
clk_ref_0_i
:
in
std_logic
;
rst_ref_0_i
:
in
std_logic
;
-- TDC core
acam_refclk_r_edge_p_i
:
in
std_logic
;
send_dac_word_p_o
:
out
std_logic
;
dac_word_o
:
out
std_logic_vector
(
23
downto
0
);
start_from_fpga_o
:
out
std_logic
;
err_flag_i
:
in
std_logic
;
int_flag_i
:
in
std_logic
;
start_dis_o
:
out
std_logic
;
stop_dis_o
:
out
std_logic
;
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
address_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
oe_n_o
:
out
std_logic
;
rd_n_o
:
out
std_logic
;
wr_n_o
:
out
std_logic
;
ef1_i
:
in
std_logic
;
ef2_i
:
in
std_logic
;
tdc_in_fpga_1_i
:
in
std_logic
;
tdc_in_fpga_2_i
:
in
std_logic
;
tdc_in_fpga_3_i
:
in
std_logic
;
tdc_in_fpga_4_i
:
in
std_logic
;
tdc_in_fpga_5_i
:
in
std_logic
;
enable_inputs_o
:
out
std_logic
;
term_en_1_o
:
out
std_logic
;
term_en_2_o
:
out
std_logic
;
term_en_3_o
:
out
std_logic
;
term_en_4_o
:
out
std_logic
;
term_en_5_o
:
out
std_logic
;
tdc_led_status_o
:
out
std_logic
;
tdc_led_trig1_o
:
out
std_logic
;
tdc_led_trig2_o
:
out
std_logic
;
tdc_led_trig3_o
:
out
std_logic
;
tdc_led_trig4_o
:
out
std_logic
;
tdc_led_trig5_o
:
out
std_logic
;
-- White Rabbit core
wrabbit_link_up_i
:
in
std_logic
;
wrabbit_time_valid_i
:
in
std_logic
;
wrabbit_cycles_i
:
in
std_logic_vector
(
27
downto
0
);
wrabbit_utc_i
:
in
std_logic_vector
(
31
downto
0
);
wrabbit_utc_p_o
:
out
std_logic
;
wrabbit_clk_aux_lock_en_o
:
out
std_logic
;
wrabbit_clk_aux_locked_i
:
in
std_logic
;
wrabbit_clk_dmtd_locked_i
:
in
std_logic
;
wrabbit_dac_value_i
:
in
std_logic_vector
(
23
downto
0
);
wrabbit_dac_wr_p_i
:
in
std_logic
;
-- WISHBONE interface with the GN4124/VME_core
-- for the core configuration | core interrupts | 1Wire | I2C
wb_tdc_csr_adr_i
:
in
std_logic_vector
(
31
downto
0
);
wb_tdc_csr_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_tdc_csr_cyc_i
:
in
std_logic
;
wb_tdc_csr_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_tdc_csr_stb_i
:
in
std_logic
;
wb_tdc_csr_we_i
:
in
std_logic
;
wb_tdc_csr_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_tdc_csr_ack_o
:
out
std_logic
;
wb_tdc_csr_stall_o
:
out
std_logic
;
wb_irq_o
:
out
std_logic
;
-- Interrupt pulses, for debug
irq_tstamp_p_o
:
out
std_logic
;
irq_time_p_o
:
out
std_logic
;
irq_acam_err_p_o
:
out
std_logic
;
-- I2C EEPROM interface
i2c_scl_o
:
out
std_logic
;
i2c_scl_oen_o
:
out
std_logic
;
i2c_scl_i
:
in
std_logic
;
i2c_sda_o
:
out
std_logic
;
i2c_sda_oen_o
:
out
std_logic
;
i2c_sda_i
:
in
std_logic
;
-- 1-wire UniqueID&Thermometer interface
one_wire_b
:
inout
std_logic
;
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_stb_o
:
out
std_logic
);
generic
(
g_with_wrabbit_core
:
boolean
:
=
TRUE
;
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
FALSE
);
port
-- 62.5MHz clock and synchronous reset
(
clk_sys_i
:
in
std_logic
;
rst_sys_n_i
:
in
std_logic
;
-- Signals from the clks_rsts_manager unit
clk_ref_0_i
:
in
std_logic
;
rst_ref_0_i
:
in
std_logic
;
-- TDC core
acam_refclk_r_edge_p_i
:
in
std_logic
;
send_dac_word_p_o
:
out
std_logic
;
dac_word_o
:
out
std_logic_vector
(
23
downto
0
);
start_from_fpga_o
:
out
std_logic
;
err_flag_i
:
in
std_logic
;
int_flag_i
:
in
std_logic
;
start_dis_o
:
out
std_logic
;
stop_dis_o
:
out
std_logic
;
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
address_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
oe_n_o
:
out
std_logic
;
rd_n_o
:
out
std_logic
;
wr_n_o
:
out
std_logic
;
ef1_i
:
in
std_logic
;
ef2_i
:
in
std_logic
;
tdc_in_fpga_1_i
:
in
std_logic
;
tdc_in_fpga_2_i
:
in
std_logic
;
tdc_in_fpga_3_i
:
in
std_logic
;
tdc_in_fpga_4_i
:
in
std_logic
;
tdc_in_fpga_5_i
:
in
std_logic
;
enable_inputs_o
:
out
std_logic
;
term_en_1_o
:
out
std_logic
;
term_en_2_o
:
out
std_logic
;
term_en_3_o
:
out
std_logic
;
term_en_4_o
:
out
std_logic
;
term_en_5_o
:
out
std_logic
;
tdc_led_status_o
:
out
std_logic
;
tdc_led_trig1_o
:
out
std_logic
;
tdc_led_trig2_o
:
out
std_logic
;
tdc_led_trig3_o
:
out
std_logic
;
tdc_led_trig4_o
:
out
std_logic
;
tdc_led_trig5_o
:
out
std_logic
;
-- White Rabbit core
wrabbit_link_up_i
:
in
std_logic
;
wrabbit_time_valid_i
:
in
std_logic
;
wrabbit_cycles_i
:
in
std_logic_vector
(
27
downto
0
);
wrabbit_utc_i
:
in
std_logic_vector
(
31
downto
0
);
wrabbit_clk_aux_lock_en_o
:
out
std_logic
;
wrabbit_clk_aux_locked_i
:
in
std_logic
;
wrabbit_clk_dmtd_locked_i
:
in
std_logic
;
wrabbit_dac_value_i
:
in
std_logic_vector
(
23
downto
0
);
wrabbit_dac_wr_p_i
:
in
std_logic
;
-- WISHBONE interface with the GN4124/VME_core
-- for the core configuration | timestamps retrieval | core interrupts | 1Wire | I2C
wb_tdc_csr_adr_i
:
in
std_logic_vector
(
31
downto
0
);
wb_tdc_csr_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_tdc_csr_cyc_i
:
in
std_logic
;
wb_tdc_csr_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_tdc_csr_stb_i
:
in
std_logic
;
wb_tdc_csr_we_i
:
in
std_logic
;
wb_tdc_csr_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_tdc_csr_ack_o
:
out
std_logic
;
wb_tdc_csr_stall_o
:
out
std_logic
;
wb_irq_o
:
out
std_logic
;
-- I2C EEPROM interface
i2c_scl_o
:
out
std_logic
;
i2c_scl_oen_o
:
out
std_logic
;
i2c_scl_i
:
in
std_logic
;
i2c_sda_o
:
out
std_logic
;
i2c_sda_oen_o
:
out
std_logic
;
i2c_sda_i
:
in
std_logic
;
-- 1-wire UniqueID&Thermometer interface
onewire_b
:
inout
std_logic
;
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_stb_o
:
out
std_logic
);
end
component
;
---------------------------------------------------------------------------------------------------
component
fmc_tdc_core
generic
(
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
false
);
port
(
clk_125m_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
acam_refclk_r_edge_p_i
:
in
std_logic
;
send_dac_word_p_o
:
out
std_logic
;
dac_word_o
:
out
std_logic_vector
(
23
downto
0
);
start_from_fpga_o
:
out
std_logic
;
err_flag_i
:
in
std_logic
;
int_flag_i
:
in
std_logic
;
start_dis_o
:
out
std_logic
;
stop_dis_o
:
out
std_logic
;
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
address_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
oe_n_o
:
out
std_logic
;
rd_n_o
:
out
std_logic
;
wr_n_o
:
out
std_logic
;
ef1_i
:
in
std_logic
;
ef2_i
:
in
std_logic
;
tdc_in_fpga_1_i
:
in
std_logic
;
tdc_in_fpga_2_i
:
in
std_logic
;
tdc_in_fpga_3_i
:
in
std_logic
;
tdc_in_fpga_4_i
:
in
std_logic
;
tdc_in_fpga_5_i
:
in
std_logic
;
enable_inputs_o
:
out
std_logic
;
term_en_1_o
:
out
std_logic
;
term_en_2_o
:
out
std_logic
;
term_en_3_o
:
out
std_logic
;
term_en_4_o
:
out
std_logic
;
term_en_5_o
:
out
std_logic
;
tdc_led_status_o
:
out
std_logic
;
tdc_led_trig1_o
:
out
std_logic
;
tdc_led_trig2_o
:
out
std_logic
;
tdc_led_trig3_o
:
out
std_logic
;
tdc_led_trig4_o
:
out
std_logic
;
tdc_led_trig5_o
:
out
std_logic
;
wrabbit_status_reg_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_ctrl_reg_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_synched_i
:
in
std_logic
;
wrabbit_tai_p_i
:
in
std_logic
;
wrabbit_tai_i
:
in
std_logic_vector
(
31
downto
0
);
irq_tstamp_p_o
:
out
std_logic
;
irq_time_p_o
:
out
std_logic
;
irq_acam_err_p_o
:
out
std_logic
;
tdc_config_wb_adr_i
:
in
std_logic_vector
(
g_span
-1
downto
0
);
tdc_config_wb_dat_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
tdc_config_wb_stb_i
:
in
std_logic
;
tdc_config_wb_we_i
:
in
std_logic
;
tdc_config_wb_cyc_i
:
in
std_logic
;
tdc_config_wb_dat_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
tdc_config_wb_ack_o
:
out
std_logic
;
tdc_mem_wb_adr_i
:
in
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_stb_i
:
in
std_logic
;
tdc_mem_wb_we_i
:
in
std_logic
;
tdc_mem_wb_cyc_i
:
in
std_logic
;
tdc_mem_wb_ack_o
:
out
std_logic
;
tdc_mem_wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_stall_o
:
out
std_logic
;
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_stb_o
:
out
std_logic
);
generic
(
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
FALSE
);
port
(
clk_125m_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
acam_refclk_r_edge_p_i
:
in
std_logic
;
send_dac_word_p_o
:
out
std_logic
;
dac_word_o
:
out
std_logic_vector
(
23
downto
0
);
start_from_fpga_o
:
out
std_logic
;
err_flag_i
:
in
std_logic
;
int_flag_i
:
in
std_logic
;
start_dis_o
:
out
std_logic
;
stop_dis_o
:
out
std_logic
;
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
address_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
oe_n_o
:
out
std_logic
;
rd_n_o
:
out
std_logic
;
wr_n_o
:
out
std_logic
;
ef1_i
:
in
std_logic
;
ef2_i
:
in
std_logic
;
tdc_in_fpga_1_i
:
in
std_logic
;
tdc_in_fpga_2_i
:
in
std_logic
;
tdc_in_fpga_3_i
:
in
std_logic
;
tdc_in_fpga_4_i
:
in
std_logic
;
tdc_in_fpga_5_i
:
in
std_logic
;
enable_inputs_o
:
out
std_logic
;
term_en_1_o
:
out
std_logic
;
term_en_2_o
:
out
std_logic
;
term_en_3_o
:
out
std_logic
;
term_en_4_o
:
out
std_logic
;
term_en_5_o
:
out
std_logic
;
tdc_led_status_o
:
out
std_logic
;
tdc_led_trig1_o
:
out
std_logic
;
tdc_led_trig2_o
:
out
std_logic
;
tdc_led_trig3_o
:
out
std_logic
;
tdc_led_trig4_o
:
out
std_logic
;
tdc_led_trig5_o
:
out
std_logic
;
wrabbit_status_reg_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_ctrl_reg_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_synched_i
:
in
std_logic
;
wrabbit_tai_p_i
:
in
std_logic
;
wrabbit_tai_i
:
in
std_logic_vector
(
31
downto
0
);
irq_tstamp_p_o
:
out
std_logic
;
irq_time_p_o
:
out
std_logic
;
irq_acam_err_p_o
:
out
std_logic
;
tdc_config_wb_adr_i
:
in
std_logic_vector
(
g_span
-1
downto
0
);
tdc_config_wb_dat_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
tdc_config_wb_stb_i
:
in
std_logic
;
tdc_config_wb_we_i
:
in
std_logic
;
tdc_config_wb_cyc_i
:
in
std_logic
;
tdc_config_wb_dat_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
tdc_config_wb_ack_o
:
out
std_logic
;
tdc_mem_wb_adr_i
:
in
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_stb_i
:
in
std_logic
;
tdc_mem_wb_we_i
:
in
std_logic
;
tdc_mem_wb_cyc_i
:
in
std_logic
;
tdc_mem_wb_ack_o
:
out
std_logic
;
tdc_mem_wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_stall_o
:
out
std_logic
;
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_stb_o
:
out
std_logic
);
end
component
;
---------------------------------------------------------------------------------------------------
component
wrabbit_sync
is
generic
(
g_simulation
:
boolean
;
g_with_wrabbit_core
:
boolean
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_sys_i
:
in
std_logic
;
clk_ref_i
:
in
std_logic
;
rst_n_ref_i
:
in
std_logic
;
wrabbit_dac_value_i
:
in
std_logic_vector
(
23
downto
0
);
wrabbit_dac_wr_p_i
:
in
std_logic
;
wrabbit_link_up_i
:
in
std_logic
;
wrabbit_time_valid_i
:
in
std_logic
;
-- this is i te clk_ref_0 domain, no??
wrabbit_clk_aux_lock_en_o
:
out
std_logic
;
wrabbit_clk_aux_locked_i
:
in
std_logic
;
wrabbit_clk_dmtd_locked_i
:
in
std_logic
;
wrabbit_synched_o
:
out
std_logic
;
wrabbit_reg_i
:
in
std_logic_vector
(
31
downto
0
);
wrabbit_reg_o
:
out
std_logic_vector
(
31
downto
0
));
generic
(
g_simulation
:
boolean
;
g_with_wrabbit_core
:
boolean
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_sys_i
:
in
std_logic
;
clk_ref_i
:
in
std_logic
;
rst_n_ref_i
:
in
std_logic
;
wrabbit_dac_value_i
:
in
std_logic_vector
(
23
downto
0
);
wrabbit_dac_wr_p_i
:
in
std_logic
;
wrabbit_link_up_i
:
in
std_logic
;
wrabbit_time_valid_i
:
in
std_logic
;
-- this is i te clk_ref_0 domain, no??
wrabbit_clk_aux_lock_en_o
:
out
std_logic
;
wrabbit_clk_aux_locked_i
:
in
std_logic
;
wrabbit_clk_dmtd_locked_i
:
in
std_logic
;
wrabbit_synched_o
:
out
std_logic
;
wrabbit_reg_i
:
in
std_logic_vector
(
31
downto
0
);
wrabbit_reg_o
:
out
std_logic_vector
(
31
downto
0
));
end
component
;
---------------------------------------------------------------------------------------------------
component
spec_reset_gen
is
port
(
clk_sys_i
:
in
std_logic
;
rst_pcie_n_a_i
:
in
std_logic
;
rst_button_n_a_i
:
in
std_logic
;
rst_n_o
:
out
std_logic
);
end
component
;
---------------------------------------------------------------------------------------------------
component
decr_counter
generic
(
width
:
integer
:
=
32
);
(
width
:
integer
:
=
32
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
counter_load_i
:
in
std_logic
;
counter_top_i
:
in
std_logic_vector
(
width
-1
downto
0
);
-------------------------------------------------------------
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
counter_load_i
:
in
std_logic
;
counter_top_i
:
in
std_logic_vector
(
width
-1
downto
0
);
-------------------------------------------------------------
counter_is_zero_o
:
out
std_logic
;
counter_o
:
out
std_logic_vector
(
width
-1
downto
0
));
-------------------------------------------------------------
-------------------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
free_counter
is
generic
(
width
:
integer
:
=
32
);
(
width
:
integer
:
=
32
);
port
(
clk_i
:
in
std_logic
;
counter_en_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
counter_top_i
:
in
std_logic_vector
(
width
-1
downto
0
);
-------------------------------------------------------------
(
clk_i
:
in
std_logic
;
counter_en_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
counter_top_i
:
in
std_logic_vector
(
width
-1
downto
0
);
-------------------------------------------------------------
counter_is_zero_o
:
out
std_logic
;
counter_o
:
out
std_logic_vector
(
width
-1
downto
0
));
-------------------------------------------------------------
-------------------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
incr_counter
generic
(
width
:
integer
:
=
32
);
(
width
:
integer
:
=
32
);
port
(
clk_i
:
in
std_logic
;
counter_top_i
:
in
std_logic_vector
(
width
-1
downto
0
);
counter_incr_en_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
-------------------------------------------------------------
(
clk_i
:
in
std_logic
;
counter_top_i
:
in
std_logic_vector
(
width
-1
downto
0
);
counter_incr_en_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
-------------------------------------------------------------
counter_is_full_o
:
out
std_logic
;
counter_o
:
out
std_logic_vector
(
width
-1
downto
0
));
-------------------------------------------------------------
end
component
;
-------------------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
component
start_retrig_ctrl
generic
(
g_width
:
integer
:
=
32
);
(
g_width
:
integer
:
=
32
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
acam_intflag_f_edge_p_i
:
in
std_logic
;
utc_p_i
:
in
std_logic
;
----------------------------------------------------------------------
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
acam_intflag_f_edge_p_i
:
in
std_logic
;
utc_p_i
:
in
std_logic
;
----------------------------------------------------------------------
current_retrig_nb_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
roll_over_incr_recent_o
:
out
std_logic
;
clk_i_cycles_offset_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
roll_over_nb_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
retrig_nb_offset_o
:
out
std_logic_vector
(
g_width
-1
downto
0
));
----------------------------------------------------------------------
----------------------------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
local_pps_gen
generic
(
g_width
:
integer
:
=
32
);
(
g_width
:
integer
:
=
32
);
port
(
acam_refclk_r_edge_p_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
clk_period_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
load_utc_p_i
:
in
std_logic
;
pulse_delay_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
rst_i
:
in
std_logic
;
starting_utc_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
----------------------------------------------------------------------
(
acam_refclk_r_edge_p_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
clk_period_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
load_utc_p_i
:
in
std_logic
;
pulse_delay_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
rst_i
:
in
std_logic
;
starting_utc_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
----------------------------------------------------------------------
local_utc_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
local_utc_p_o
:
out
std_logic
);
----------------------------------------------------------------------
----------------------------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
data_engine
port
(
acam_ack_i
:
in
std_logic
;
acam_dat_i
:
in
std_logic_vector
(
31
downto
0
);
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
acam_ef1_i
:
in
std_logic
;
acam_ef1_meta_i
:
in
std_logic
;
acam_ef2_i
:
in
std_logic
;
acam_ef2_meta_i
:
in
std_logic
;
activate_acq_p_i
:
in
std_logic
;
deactivate_acq_p_i
:
in
std_logic
;
acam_wr_config_p_i
:
in
std_logic
;
acam_rdbk_config_p_i
:
in
std_logic
;
acam_rdbk_status_p_i
:
in
std_logic
;
acam_rdbk_ififo1_p_i
:
in
std_logic
;
acam_rdbk_ififo2_p_i
:
in
std_logic
;
acam_rdbk_start01_p_i
:
in
std_logic
;
acam_rst_p_i
:
in
std_logic
;
acam_config_i
:
in
config_vector
;
start_from_fpga_i
:
in
std_logic
;
----------------------------------------------------------------------
(
acam_ack_i
:
in
std_logic
;
acam_dat_i
:
in
std_logic_vector
(
31
downto
0
);
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
acam_ef1_i
:
in
std_logic
;
acam_ef1_meta_i
:
in
std_logic
;
acam_ef2_i
:
in
std_logic
;
acam_ef2_meta_i
:
in
std_logic
;
activate_acq_p_i
:
in
std_logic
;
deactivate_acq_p_i
:
in
std_logic
;
acam_wr_config_p_i
:
in
std_logic
;
acam_rdbk_config_p_i
:
in
std_logic
;
acam_rdbk_status_p_i
:
in
std_logic
;
acam_rdbk_ififo1_p_i
:
in
std_logic
;
acam_rdbk_ififo2_p_i
:
in
std_logic
;
acam_rdbk_start01_p_i
:
in
std_logic
;
acam_rst_p_i
:
in
std_logic
;
acam_config_i
:
in
config_vector
;
start_from_fpga_i
:
in
std_logic
;
----------------------------------------------------------------------
state_active_p_o
:
out
std_logic
;
acam_adr_o
:
out
std_logic_vector
(
7
downto
0
);
acam_adr_o
:
out
std_logic_vector
(
7
downto
0
);
acam_cyc_o
:
out
std_logic
;
acam_dat_o
:
out
std_logic_vector
(
31
downto
0
);
acam_stb_o
:
out
std_logic
;
...
...
@@ -652,34 +640,33 @@ package tdc_core_pkg is
acam_tstamp1_ok_p_o
:
out
std_logic
;
acam_tstamp2_o
:
out
std_logic_vector
(
31
downto
0
);
acam_tstamp2_ok_p_o
:
out
std_logic
);
----------------------------------------------------------------------
----------------------------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
reg_ctrl
generic
(
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
);
(
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
tdc_config_wb_adr_i
:
in
std_logic_vector
(
g_span
-1
downto
0
);
tdc_config_wb_cyc_i
:
in
std_logic
;
tdc_config_wb_dat_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
tdc_config_wb_stb_i
:
in
std_logic
;
tdc_config_wb_we_i
:
in
std_logic
;
acam_config_rdbk_i
:
in
config_vector
;
acam_ififo1_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
acam_ififo2_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
acam_start01_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
local_utc_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
irq_code_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
wr_index_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
core_status_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_status_reg_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
----------------------------------------------------------------------
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
tdc_config_wb_adr_i
:
in
std_logic_vector
(
g_span
-1
downto
0
);
tdc_config_wb_cyc_i
:
in
std_logic
;
tdc_config_wb_dat_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
tdc_config_wb_stb_i
:
in
std_logic
;
tdc_config_wb_we_i
:
in
std_logic
;
acam_config_rdbk_i
:
in
config_vector
;
acam_ififo1_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
acam_ififo2_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
acam_start01_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
local_utc_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
irq_code_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
wr_index_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
core_status_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_status_reg_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
----------------------------------------------------------------------
tdc_config_wb_ack_o
:
out
std_logic
;
tdc_config_wb_dat_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
activate_acq_p_o
:
out
std_logic
;
...
...
@@ -695,7 +682,7 @@ package tdc_core_pkg is
load_utc_p_o
:
out
std_logic
;
irq_tstamp_threshold_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
irq_time_threshold_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
send_dac_word_p_o
:
out
std_logic
;
send_dac_word_p_o
:
out
std_logic
;
dac_word_o
:
out
std_logic_vector
(
23
downto
0
);
dacapo_c_rst_p_o
:
out
std_logic
;
acam_config_o
:
out
config_vector
;
...
...
@@ -704,53 +691,52 @@ package tdc_core_pkg is
start_phase_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
one_hz_phase_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_ctrl_reg_o
:
out
std_logic_vector
(
g_width
-1
downto
0
));
----------------------------------------------------------------------
----------------------------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
acam_timecontrol_interface
port
(
err_flag_i
:
in
std_logic
;
int_flag_i
:
in
std_logic
;
acam_refclk_r_edge_p_i
:
in
std_logic
;
utc_p_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
activate_acq_p_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
window_delay_i
:
in
std_logic_vector
(
31
downto
0
);
state_active_p_i
:
in
std_logic
;
deactivate_acq_p_i
:
in
std_logic
;
----------------------------------------------------------------------
(
err_flag_i
:
in
std_logic
;
int_flag_i
:
in
std_logic
;
acam_refclk_r_edge_p_i
:
in
std_logic
;
utc_p_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
activate_acq_p_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
state_active_p_i
:
in
std_logic
;
deactivate_acq_p_i
:
in
std_logic
;
----------------------------------------------------------------------
start_from_fpga_o
:
out
std_logic
;
stop_dis_o
:
out
std_logic
;
stop_dis_o
:
out
std_logic
;
acam_errflag_r_edge_p_o
:
out
std_logic
;
acam_errflag_f_edge_p_o
:
out
std_logic
;
acam_intflag_f_edge_p_o
:
out
std_logic
);
----------------------------------------------------------------------
----------------------------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
data_formatting
port
(
tstamp_wr_wb_ack_i
:
in
std_logic
;
tstamp_wr_dat_i
:
in
std_logic_vector
(
127
downto
0
);
acam_tstamp1_i
:
in
std_logic_vector
(
31
downto
0
);
acam_tstamp1_ok_p_i
:
in
std_logic
;
acam_tstamp2_i
:
in
std_logic_vector
(
31
downto
0
);
acam_tstamp2_ok_p_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
dacapo_c_rst_p_i
:
in
std_logic
;
deactivate_chan_i
:
in
std_logic_vector
(
4
downto
0
);
rst_i
:
in
std_logic
;
roll_over_incr_recent_i
:
in
std_logic
;
clk_i_cycles_offset_i
:
in
std_logic_vector
(
31
downto
0
);
roll_over_nb_i
:
in
std_logic_vector
(
31
downto
0
);
utc_i
:
in
std_logic_vector
(
31
downto
0
);
retrig_nb_offset_i
:
in
std_logic_vector
(
31
downto
0
);
utc_p_i
:
in
std_logic
;
----------------------------------------------------------------------
(
tstamp_wr_wb_ack_i
:
in
std_logic
;
tstamp_wr_dat_i
:
in
std_logic_vector
(
127
downto
0
);
acam_tstamp1_i
:
in
std_logic_vector
(
31
downto
0
);
acam_tstamp1_ok_p_i
:
in
std_logic
;
acam_tstamp2_i
:
in
std_logic_vector
(
31
downto
0
);
acam_tstamp2_ok_p_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
dacapo_c_rst_p_i
:
in
std_logic
;
deactivate_chan_i
:
in
std_logic_vector
(
4
downto
0
);
rst_i
:
in
std_logic
;
roll_over_incr_recent_i
:
in
std_logic
;
clk_i_cycles_offset_i
:
in
std_logic_vector
(
31
downto
0
);
roll_over_nb_i
:
in
std_logic_vector
(
31
downto
0
);
utc_i
:
in
std_logic_vector
(
31
downto
0
);
retrig_nb_offset_i
:
in
std_logic_vector
(
31
downto
0
);
utc_p_i
:
in
std_logic
;
----------------------------------------------------------------------
tstamp_wr_wb_adr_o
:
out
std_logic_vector
(
7
downto
0
);
tstamp_wr_wb_cyc_o
:
out
std_logic
;
tstamp_wr_dat_o
:
out
std_logic_vector
(
127
downto
0
);
...
...
@@ -759,28 +745,28 @@ package tdc_core_pkg is
tstamp_wr_p_o
:
out
std_logic
;
acam_channel_o
:
out
std_logic_vector
(
2
downto
0
);
wr_index_o
:
out
std_logic_vector
(
31
downto
0
));
----------------------------------------------------------------------
----------------------------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
irq_generator
is
generic
(
g_width
:
integer
:
=
32
);
(
g_width
:
integer
:
=
32
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
irq_tstamp_threshold_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
irq_time_threshold_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
activate_acq_p_i
:
in
std_logic
;
deactivate_acq_p_i
:
in
std_logic
;
tstamp_wr_p_i
:
in
std_logic
;
acam_errflag_r_edge_p_i
:
in
std_logic
;
----------------------------------------------------------------------
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
irq_tstamp_threshold_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
irq_time_threshold_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
activate_acq_p_i
:
in
std_logic
;
deactivate_acq_p_i
:
in
std_logic
;
tstamp_wr_p_i
:
in
std_logic
;
acam_errflag_r_edge_p_i
:
in
std_logic
;
----------------------------------------------------------------------
irq_tstamp_p_o
:
out
std_logic
;
irq_acam_err_p_o
:
out
std_logic
;
irq_time_p_o
:
out
std_logic
);
----------------------------------------------------------------------
----------------------------------------------------------------------
end
component
;
...
...
@@ -805,62 +791,24 @@ package tdc_core_pkg is
end
component
tdc_eic
;
---------------------------------------------------------------------------------------------------
component
dma_eic
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
irq_dma_done_i
:
in
std_logic
;
irq_dma_error_i
:
in
std_logic
);
end
component
dma_eic
;
---------------------------------------------------------------------------------------------------
component
irq_controller
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
irq_src_p_i
:
in
std_logic_vector
(
31
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
----------------------------------------------------------------------
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_ack_o
:
out
std_logic
;
irq_p_o
:
out
std_logic
);
end
component
irq_controller
;
---------------------------------------------------------------------------------------------------
component
clks_rsts_manager
generic
(
nb_of_reg
:
integer
:
=
68
);
(
nb_of_reg
:
integer
:
=
68
);
port
(
clk_sys_i
:
in
std_logic
;
acam_refclk_p_i
:
in
std_logic
;
acam_refclk_n_i
:
in
std_logic
;
tdc_125m_clk_p_i
:
in
std_logic
;
tdc_125m_clk_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
pll_status_i
:
in
std_logic
;
pll_sdo_i
:
in
std_logic
;
send_dac_word_p_i
:
in
std_logic
;
dac_word_i
:
in
std_logic_vector
(
23
downto
0
);
wrabbit_dac_wr_p_i
:
in
std_logic
;
wrabbit_dac_value_i
:
in
std_logic_vector
(
23
downto
0
);
----------------------------------------------------------------------
(
clk_sys_i
:
in
std_logic
;
acam_refclk_p_i
:
in
std_logic
;
acam_refclk_n_i
:
in
std_logic
;
tdc_125m_clk_p_i
:
in
std_logic
;
tdc_125m_clk_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
pll_status_i
:
in
std_logic
;
pll_sdo_i
:
in
std_logic
;
send_dac_word_p_i
:
in
std_logic
;
dac_word_i
:
in
std_logic_vector
(
23
downto
0
);
wrabbit_dac_wr_p_i
:
in
std_logic
;
wrabbit_dac_value_i
:
in
std_logic_vector
(
23
downto
0
);
----------------------------------------------------------------------
tdc_125m_clk_o
:
out
std_logic
;
internal_rst_o
:
out
std_logic
;
acam_refclk_r_edge_p_o
:
out
std_logic
;
...
...
@@ -869,7 +817,7 @@ package tdc_core_pkg is
pll_sdi_o
:
out
std_logic
;
pll_sclk_o
:
out
std_logic
;
pll_status_o
:
out
std_logic
);
----------------------------------------------------------------------
----------------------------------------------------------------------
end
component
;
...
...
@@ -910,189 +858,173 @@ package tdc_core_pkg is
component
leds_manager
is
generic
(
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
false
);
values_for_simul
:
boolean
:
=
FALSE
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
utc_p_i
:
in
std_logic
;
acam_inputs_en_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
acam_channel_i
:
in
std_logic_vector
(
5
downto
0
);
tstamp_wr_p_i
:
in
std_logic
;
----------------------------------------------------------------------
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
utc_p_i
:
in
std_logic
;
acam_inputs_en_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
acam_channel_i
:
in
std_logic_vector
(
5
downto
0
);
tstamp_wr_p_i
:
in
std_logic
;
----------------------------------------------------------------------
tdc_led_status_o
:
out
std_logic
;
tdc_led_trig1_o
:
out
std_logic
;
tdc_led_trig2_o
:
out
std_logic
;
tdc_led_trig3_o
:
out
std_logic
;
tdc_led_trig4_o
:
out
std_logic
;
tdc_led_trig5_o
:
out
std_logic
);
----------------------------------------------------------------------
----------------------------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
acam_databus_interface
port
(
ef1_i
:
in
std_logic
;
ef2_i
:
in
std_logic
;
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
adr_i
:
in
std_logic_vector
(
7
downto
0
);
cyc_i
:
in
std_logic
;
dat_i
:
in
std_logic_vector
(
31
downto
0
);
stb_i
:
in
std_logic
;
we_i
:
in
std_logic
;
----------------------------------------------------------------------
adr_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
oe_n_o
:
out
std_logic
;
rd_n_o
:
out
std_logic
;
wr_n_o
:
out
std_logic
;
ack_o
:
out
std_logic
;
ef1_o
:
out
std_logic
;
ef1_meta_o
:
out
std_logic
;
ef2_o
:
out
std_logic
;
ef2_meta_o
:
out
std_logic
;
dat_o
:
out
std_logic_vector
(
31
downto
0
));
----------------------------------------------------------------------
(
ef1_i
:
in
std_logic
;
ef2_i
:
in
std_logic
;
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
adr_i
:
in
std_logic_vector
(
7
downto
0
);
cyc_i
:
in
std_logic
;
dat_i
:
in
std_logic_vector
(
31
downto
0
);
stb_i
:
in
std_logic
;
we_i
:
in
std_logic
;
----------------------------------------------------------------------
adr_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
oe_n_o
:
out
std_logic
;
rd_n_o
:
out
std_logic
;
wr_n_o
:
out
std_logic
;
ack_o
:
out
std_logic
;
ef1_o
:
out
std_logic
;
ef1_meta_o
:
out
std_logic
;
ef2_o
:
out
std_logic
;
ef2_meta_o
:
out
std_logic
;
dat_o
:
out
std_logic_vector
(
31
downto
0
));
----------------------------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
circular_buffer
port
(
clk_i
:
in
std_logic
;
tstamp_wr_rst_i
:
in
std_logic
;
tstamp_wr_stb_i
:
in
std_logic
;
tstamp_wr_cyc_i
:
in
std_logic
;
tstamp_wr_we_i
:
in
std_logic
;
tstamp_wr_adr_i
:
in
std_logic_vector
(
7
downto
0
);
tstamp_wr_dat_i
:
in
std_logic_vector
(
127
downto
0
);
tdc_mem_wb_rst_i
:
in
std_logic
;
tdc_mem_wb_stb_i
:
in
std_logic
;
tdc_mem_wb_cyc_i
:
in
std_logic
;
tdc_mem_wb_we_i
:
in
std_logic
;
tdc_mem_wb_adr_i
:
in
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
--------------------------------------------------
(
clk_i
:
in
std_logic
;
tstamp_wr_rst_i
:
in
std_logic
;
tstamp_wr_stb_i
:
in
std_logic
;
tstamp_wr_cyc_i
:
in
std_logic
;
tstamp_wr_we_i
:
in
std_logic
;
tstamp_wr_adr_i
:
in
std_logic_vector
(
7
downto
0
);
tstamp_wr_dat_i
:
in
std_logic_vector
(
127
downto
0
);
tdc_mem_wb_rst_i
:
in
std_logic
;
tdc_mem_wb_stb_i
:
in
std_logic
;
tdc_mem_wb_cyc_i
:
in
std_logic
;
tdc_mem_wb_we_i
:
in
std_logic
;
tdc_mem_wb_adr_i
:
in
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
--------------------------------------------------
tstamp_wr_ack_p_o
:
out
std_logic
;
tstamp_wr_dat_o
:
out
std_logic_vector
(
127
downto
0
);
tdc_mem_wb_ack_o
:
out
std_logic
;
tdc_mem_wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_stall_o
:
out
std_logic
);
--------------------------------------------------
--------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
blk_mem_circ_buff_v6_4
port
(
clka
:
in
std_logic
;
addra
:
in
std_logic_vector
(
7
downto
0
);
dina
:
in
std_logic_vector
(
127
downto
0
);
ena
:
in
std_logic
;
wea
:
in
std_logic_vector
(
0
downto
0
);
clkb
:
in
std_logic
;
addrb
:
in
std_logic_vector
(
9
downto
0
);
dinb
:
in
std_logic_vector
(
31
downto
0
);
enb
:
in
std_logic
;
web
:
in
std_logic_vector
(
0
downto
0
);
--------------------------------------------------
douta
:
out
std_logic_vector
(
127
downto
0
);
doutb
:
out
std_logic_vector
(
31
downto
0
));
--------------------------------------------------
(
clka
:
in
std_logic
;
addra
:
in
std_logic_vector
(
7
downto
0
);
dina
:
in
std_logic_vector
(
127
downto
0
);
ena
:
in
std_logic
;
wea
:
in
std_logic_vector
(
0
downto
0
);
clkb
:
in
std_logic
;
addrb
:
in
std_logic_vector
(
9
downto
0
);
dinb
:
in
std_logic_vector
(
31
downto
0
);
enb
:
in
std_logic
;
web
:
in
std_logic_vector
(
0
downto
0
);
--------------------------------------------------
douta
:
out
std_logic_vector
(
127
downto
0
);
doutb
:
out
std_logic_vector
(
31
downto
0
));
--------------------------------------------------
end
component
;
component
fmc_tdc_wrapper
is
generic
(
g_simulation
:
boolean
);
port
(
clk_sys_i
:
in
std_logic
;
rst_sys_n_i
:
in
std_logic
;
rst_n_a_i
:
in
std_logic
;
pll_sclk_o
:
out
std_logic
;
pll_sdi_o
:
out
std_logic
;
pll_cs_o
:
out
std_logic
;
pll_dac_sync_o
:
out
std_logic
;
pll_sdo_i
:
in
std_logic
;
pll_status_i
:
in
std_logic
;
tdc_clk_125m_p_i
:
in
std_logic
;
tdc_clk_125m_n_i
:
in
std_logic
;
acam_refclk_p_i
:
in
std_logic
;
acam_refclk_n_i
:
in
std_logic
;
start_from_fpga_o
:
out
std_logic
;
err_flag_i
:
in
std_logic
;
int_flag_i
:
in
std_logic
;
start_dis_o
:
out
std_logic
;
stop_dis_o
:
out
std_logic
;
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
address_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
oe_n_o
:
out
std_logic
;
rd_n_o
:
out
std_logic
;
wr_n_o
:
out
std_logic
;
ef1_i
:
in
std_logic
;
ef2_i
:
in
std_logic
;
enable_inputs_o
:
out
std_logic
;
term_en_1_o
:
out
std_logic
;
term_en_2_o
:
out
std_logic
;
term_en_3_o
:
out
std_logic
;
term_en_4_o
:
out
std_logic
;
term_en_5_o
:
out
std_logic
;
tdc_led_status_o
:
out
std_logic
;
tdc_led_trig1_o
:
out
std_logic
;
tdc_led_trig2_o
:
out
std_logic
;
tdc_led_trig3_o
:
out
std_logic
;
tdc_led_trig4_o
:
out
std_logic
;
tdc_led_trig5_o
:
out
std_logic
;
tdc_in_fpga_1_i
:
in
std_logic
;
tdc_in_fpga_2_i
:
in
std_logic
;
tdc_in_fpga_3_i
:
in
std_logic
;
tdc_in_fpga_4_i
:
in
std_logic
;
tdc_in_fpga_5_i
:
in
std_logic
;
mezz_one_wire_b
:
inout
std_logic
;
mezz_scl_b
:
inout
std_logic
;
mezz_sda_b
:
inout
std_logic
;
tm_link_up_i
:
in
std_logic
;
tm_time_valid_i
:
in
std_logic
;
tm_cycles_i
:
in
std_logic_vector
(
27
downto
0
);
tm_tai_i
:
in
std_logic_vector
(
39
downto
0
);
tm_clk_aux_lock_en_o
:
out
std_logic
;
tm_clk_aux_locked_i
:
in
std_logic
;
tm_clk_dmtd_locked_i
:
in
std_logic
;
tm_dac_value_i
:
in
std_logic_vector
(
23
downto
0
);
tm_dac_wr_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
direct_slave_i
:
in
t_wishbone_slave_in
;
direct_slave_o
:
out
t_wishbone_slave_out
;
irq_o
:
out
std_logic
;
clk_125m_tdc_o
:
out
std_logic
);
clk_sys_i
:
in
std_logic
;
rst_sys_n_i
:
in
std_logic
;
rst_n_a_i
:
in
std_logic
;
pll_sclk_o
:
out
std_logic
;
pll_sdi_o
:
out
std_logic
;
pll_cs_o
:
out
std_logic
;
pll_dac_sync_o
:
out
std_logic
;
pll_sdo_i
:
in
std_logic
;
pll_status_i
:
in
std_logic
;
tdc_clk_125m_p_i
:
in
std_logic
;
tdc_clk_125m_n_i
:
in
std_logic
;
acam_refclk_p_i
:
in
std_logic
;
acam_refclk_n_i
:
in
std_logic
;
start_from_fpga_o
:
out
std_logic
;
err_flag_i
:
in
std_logic
;
int_flag_i
:
in
std_logic
;
start_dis_o
:
out
std_logic
;
stop_dis_o
:
out
std_logic
;
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
address_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
oe_n_o
:
out
std_logic
;
rd_n_o
:
out
std_logic
;
wr_n_o
:
out
std_logic
;
ef1_i
:
in
std_logic
;
ef2_i
:
in
std_logic
;
enable_inputs_o
:
out
std_logic
;
term_en_1_o
:
out
std_logic
;
term_en_2_o
:
out
std_logic
;
term_en_3_o
:
out
std_logic
;
term_en_4_o
:
out
std_logic
;
term_en_5_o
:
out
std_logic
;
tdc_led_status_o
:
out
std_logic
;
tdc_led_trig1_o
:
out
std_logic
;
tdc_led_trig2_o
:
out
std_logic
;
tdc_led_trig3_o
:
out
std_logic
;
tdc_led_trig4_o
:
out
std_logic
;
tdc_led_trig5_o
:
out
std_logic
;
tdc_in_fpga_1_i
:
in
std_logic
;
tdc_in_fpga_2_i
:
in
std_logic
;
tdc_in_fpga_3_i
:
in
std_logic
;
tdc_in_fpga_4_i
:
in
std_logic
;
tdc_in_fpga_5_i
:
in
std_logic
;
mezz_scl_b
:
inout
std_logic
;
mezz_sda_b
:
inout
std_logic
;
mezz_one_wire_b
:
inout
std_logic
;
tm_link_up_i
:
in
std_logic
;
tm_time_valid_i
:
in
std_logic
;
tm_cycles_i
:
in
std_logic_vector
(
27
downto
0
);
tm_tai_i
:
in
std_logic_vector
(
39
downto
0
);
tm_clk_aux_lock_en_o
:
out
std_logic
;
tm_clk_aux_locked_i
:
in
std_logic
;
tm_clk_dmtd_locked_i
:
in
std_logic
;
tm_dac_value_i
:
in
std_logic_vector
(
23
downto
0
);
tm_dac_wr_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
direct_slave_i
:
in
t_wishbone_slave_in
;
direct_slave_o
:
out
t_wishbone_slave_out
;
irq_o
:
out
std_logic
;
clk_125m_tdc_o
:
out
std_logic
);
end
component
fmc_tdc_wrapper
;
component
fmc_tdc_direct_readout
is
port
(
clk_tdc_i
:
in
std_logic
;
rst_tdc_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
rst_sys_n_i
:
in
std_logic
;
direct_timestamp_i
:
in
std_logic_vector
(
127
downto
0
);
direct_timestamp_wr_i
:
in
std_logic
;
direct_slave_i
:
in
t_wishbone_slave_in
;
direct_slave_o
:
out
t_wishbone_slave_out
);
end
component
fmc_tdc_direct_readout
;
end
tdc_core_pkg
;
--=================================================================================================
-- package body
--=================================================================================================
package
body
tdc_core_pkg
is
end
tdc_core_pkg
;
--=================================================================================================
-- package end
...
...
@@ -1100,3 +1032,4 @@ end tdc_core_pkg;
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
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