rtl: use the real (HW postprocessed) timestamp for writing the DMA buffer

8e1b578c · Tomasz Wlostowski · 4e8dfa4b · 8e1b578c
Commit 8e1b578c authored Sep 03, 2018 by Tomasz Wlostowski
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Showing with 4 additions and 4 deletions

tdc_dma_channel.vhd hdl/rtl/tdc_dma_channel.vhd +4 -4

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--- a/hdl/rtl/tdc_dma_channel.vhd
+++ b/hdl/rtl/tdc_dma_channel.vhd
@@ -249,22 +249,22 @@ begin
 --  bit  2-0 chan  (mask: 0x7)
          when SER0 =>
-            fifo_in_data    <= ts.raw.tai;
+            fifo_in_data    <= ts.tai;
            fifo_in_is_addr <= '0';
            fifo_wr         <= '1';
            state           <= SER1;
          when SER1 =>
-            fifo_in_data    <= ts.raw.coarse;
+            fifo_in_data    <= ts.coarse;
            fifo_in_is_addr <= '0';
            fifo_wr         <= '1';
            state           <= SER2;
          when SER2 =>
-            fifo_in_data    <= "000000000000000" & ts.raw.n_bins;
+            fifo_in_data    <= x"00000" & ts.frac;
            fifo_in_is_addr <= '0';
            fifo_wr         <= '1';
            state           <= SER3;
          when SER3 =>
-            fifo_in_data    <= ts.raw.seq(27 downto 0) & ts.raw.slope & ts.raw.channel(2 downto 0);
+            fifo_in_data    <= ts.seq(27 downto 0) & ts.slope & ts.channel(2 downto 0);
            fifo_in_is_addr <= '0';
            fifo_wr         <= '1';
            state           <= WAIT_NEXT_TS;