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FMC TDC 1ns 5cha - Gateware
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FMC TDC 1ns 5cha - Gateware
Commits
8e1b578c
Commit
8e1b578c
authored
Sep 03, 2018
by
Tomasz Wlostowski
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rtl: use the real (HW postprocessed) timestamp for writing the DMA buffer
parent
4e8dfa4b
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tdc_dma_channel.vhd
hdl/rtl/tdc_dma_channel.vhd
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hdl/rtl/tdc_dma_channel.vhd
View file @
8e1b578c
...
@@ -249,22 +249,22 @@ begin
...
@@ -249,22 +249,22 @@ begin
-- bit 2-0 chan (mask: 0x7)
-- bit 2-0 chan (mask: 0x7)
when
SER0
=>
when
SER0
=>
fifo_in_data
<=
ts
.
raw
.
tai
;
fifo_in_data
<=
ts
.
tai
;
fifo_in_is_addr
<=
'0'
;
fifo_in_is_addr
<=
'0'
;
fifo_wr
<=
'1'
;
fifo_wr
<=
'1'
;
state
<=
SER1
;
state
<=
SER1
;
when
SER1
=>
when
SER1
=>
fifo_in_data
<=
ts
.
raw
.
coarse
;
fifo_in_data
<=
ts
.
coarse
;
fifo_in_is_addr
<=
'0'
;
fifo_in_is_addr
<=
'0'
;
fifo_wr
<=
'1'
;
fifo_wr
<=
'1'
;
state
<=
SER2
;
state
<=
SER2
;
when
SER2
=>
when
SER2
=>
fifo_in_data
<=
"000000000000000"
&
ts
.
raw
.
n_bins
;
fifo_in_data
<=
x"00000"
&
ts
.
frac
;
fifo_in_is_addr
<=
'0'
;
fifo_in_is_addr
<=
'0'
;
fifo_wr
<=
'1'
;
fifo_wr
<=
'1'
;
state
<=
SER3
;
state
<=
SER3
;
when
SER3
=>
when
SER3
=>
fifo_in_data
<=
ts
.
raw
.
seq
(
27
downto
0
)
&
ts
.
raw
.
slope
&
ts
.
raw
.
channel
(
2
downto
0
);
fifo_in_data
<=
ts
.
seq
(
27
downto
0
)
&
ts
.
slope
&
ts
.
channel
(
2
downto
0
);
fifo_in_is_addr
<=
'0'
;
fifo_in_is_addr
<=
'0'
;
fifo_wr
<=
'1'
;
fifo_wr
<=
'1'
;
state
<=
WAIT_NEXT_TS
;
state
<=
WAIT_NEXT_TS
;
...
...
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