Skip to content

F
FMC TDC 1ns 5cha - Gateware
Commit 9a23aeb5 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

rtl: added raw timestamp readout mode

parent 8e1b578c
Hide whitespace changes
Inline Side-by-side
Showing with 58 additions and 19 deletions
hdl/rtl/fmc_tdc_core.vhd
View file @ 9a23aeb5
......@@ -213,6 +213,7 @@ entity fmc_tdc_core is
ts_offset_i : in t_tdc_timestamp_array(4 downto 0);
reset_seq_i : in std_logic_vector(4 downto 0);
raw_enable_i : in std_logic_vector(4 downto 0);
timestamp_o : out t_tdc_timestamp_array(4 downto 0);
timestamp_valid_o : out std_logic_vector(4 downto 0);
timestamp_ready_i : in std_logic_vector(4 downto 0);
......@@ -551,7 +552,8 @@ begin
ts_valid_o => final_timestamp_valid,
ts_ready_i => final_timestamp_ready,
ts_offset_i => ts_offset_i,
reset_seq_i => reset_seq_i
reset_seq_i => reset_seq_i,
raw_enable_i => raw_enable_i
);
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 9a23aeb5
......@@ -278,6 +278,7 @@ architecture rtl of fmc_tdc_mezzanine is
signal ts_offset : t_tdc_timestamp_array(4 downto 0);
signal reset_seq : std_logic_vector(4 downto 0);
signal raw_enable : std_logic_vector(4 downto 0);
function f_wb_shift_address_word (w : t_wishbone_master_out) return t_wishbone_master_out is
variable r : t_wishbone_master_out;
......@@ -378,6 +379,7 @@ begin
timestamp_valid_o => tdc_timestamp_valid,
timestamp_ready_i => tdc_timestamp_ready,
raw_enable_i => raw_enable,
ts_offset_i => ts_offset,
reset_seq_i => reset_seq,
......@@ -435,13 +437,12 @@ begin
timestamp_i => timestamp,
timestamp_valid_i => timestamp_stb,
ts_offset_o => ts_offset(i),
reset_seq_o => reset_seq(i));
reset_seq_o => reset_seq(i),
raw_enable_o => raw_enable(i));
timestamp_stb(i) <= timestamp_valid(i) and timestamp_ready(i);
end generate gen_fifos;
timestamp_ready <= (others => '1');
gen_with_dma_readout : if g_use_dma_readout generate
U_DMA_Engine : entity work.tdc_dma_engine
generic map (
......@@ -452,7 +453,7 @@ begin
enable_i => channel_enable,
ts_i => timestamp,
ts_valid_i => timestamp_valid,
-- ts_ready_o => timestamp_ready,
ts_ready_o => timestamp_ready,
slave_i => cnx_master_out(c_WB_SLAVE_TDC_DMA),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_DMA),
irq_o => irq_dma,
......
hdl/rtl/timestamp_convert_filter.vhd
View file @ 9a23aeb5
......@@ -13,18 +13,19 @@ entity timestamp_convert_filter is
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
enable_i : in std_logic_vector(4 downto 0);
reset_seq_i : in std_logic_vector(4 downto 0);
enable_i : in std_logic_vector(4 downto 0);
reset_seq_i : in std_logic_vector(4 downto 0);
raw_enable_i : in std_logic_vector(4 downto 0);
-- raw timestamp input, clk_tdc_i domain
ts_i : in t_raw_acam_timestamp;
ts_valid_i : in std_logic;
-- converted and filtered timestamp output, clk_sys_i domain
ts_offset_i : in t_tdc_timestamp_array(4 downto 0);
ts_o : out t_tdc_timestamp_array(4 downto 0);
ts_offset_i : in t_tdc_timestamp_array(4 downto 0);
ts_o : out t_tdc_timestamp_array(4 downto 0);
ts_valid_o : buffer std_logic_vector(4 downto 0);
ts_ready_i : in std_logic_vector(4 downto 0)
ts_ready_i : in std_logic_vector(4 downto 0)
);
......@@ -243,15 +244,31 @@ begin
if rst_sys_n_i = '0' or enable_i(i) = '0' then
ts_valid_o(i) <= '0';
else
if ts_ready_i(i) = '1' then
ts_valid_o(i) <= '0';
end if;
if ts_valid_postoffset(i) = '1' then
ts_valid_o(i) <= '1';
ts_o(i) <= ts_postoffset(i);
if raw_enable_i(i) = '1' then
if ts_valid_sys = '1' and unsigned(ts_latched.channel) = i then
ts_valid_o(i) <= '1';
ts_o(i).tai <= ts_latched.tai;
ts_o(i).coarse <= ts_latched.coarse;
-- ts_o(i).frac <= ts_latched.n_bins;
ts_o(i).seq <= "000000000000000" & ts_latched.n_bins;
end if;
else
if ts_valid_postoffset(i) = '1' then
ts_valid_o(i) <= '1';
ts_o(i) <= ts_postoffset(i);
end if;
end if;
end if;
end if;
end process;
......
hdl/rtl/timestamp_fifo.vhd
View file @ 9a23aeb5
......@@ -51,7 +51,8 @@ entity timestamp_fifo is
timestamp_valid_i : in std_logic_vector(4 downto 0);
ts_offset_o : out t_tdc_timestamp;
reset_seq_o : out std_logic
reset_seq_o : out std_logic;
raw_enable_o : out std_logic
);
end entity;
......@@ -88,7 +89,7 @@ begin
ts_offset_o.coarse <= regs_out.offset2_o;
ts_offset_o.frac <= regs_out.offset3_o(11 downto 0);
reset_seq_o <= regs_out.csr_rst_seq_o;
raw_enable_o <= regs_out.csr_raw_mode_o;
timestamp_with_seq(31 downto 0) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).tai), 32));
timestamp_with_seq(63 downto 32) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).coarse), 32));
......
hdl/rtl/timestamp_fifo_wb.vhd
View file @ 9a23aeb5
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wb.vhd
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created : Thu Aug 30 21:26:01 2018
-- Created : Sun Sep 2 15:37:55 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
......@@ -46,6 +46,7 @@ signal tsf_csr_delta_read_int : std_logic ;
signal tsf_csr_rst_seq_dly0 : std_logic ;
signal tsf_csr_rst_seq_int : std_logic ;
signal tsf_csr_delta_ref_int : std_logic_vector(2 downto 0);
signal tsf_csr_raw_mode_int : std_logic ;
signal tsf_fifo_full_int : std_logic ;
signal tsf_fifo_empty_int : std_logic ;
signal tsf_fifo_clear_bus_int : std_logic ;
......@@ -78,6 +79,7 @@ begin
tsf_csr_delta_read_int <= '0';
tsf_csr_rst_seq_int <= '0';
tsf_csr_delta_ref_int <= "000";
tsf_csr_raw_mode_int <= '0';
tsf_fifo_clear_bus_int <= '0';
tsf_fifo_rdreq_int <= '0';
elsif rising_edge(clk_sys_i) then
......@@ -139,12 +141,13 @@ begin
tsf_csr_delta_read_int <= wrdata_reg(1);
tsf_csr_rst_seq_int <= wrdata_reg(2);
tsf_csr_delta_ref_int <= wrdata_reg(5 downto 3);
tsf_csr_raw_mode_int <= wrdata_reg(6);
end if;
rddata_reg(0) <= regs_i.csr_delta_ready_i;
rddata_reg(1) <= '0';
rddata_reg(2) <= '0';
rddata_reg(5 downto 3) <= tsf_csr_delta_ref_int;
rddata_reg(6) <= 'X';
rddata_reg(6) <= tsf_csr_raw_mode_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
......@@ -313,6 +316,8 @@ end process;
-- Delta Timestamp Reference Channel
regs_o.csr_delta_ref_o <= tsf_csr_delta_ref_int;
-- Raw readout mode
regs_o.csr_raw_mode_o <= tsf_csr_raw_mode_int;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 0
process (clk_sys_i, rst_n_i)
begin
......
hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
View file @ 9a23aeb5
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created : Thu Aug 30 21:26:01 2018
-- Created : Sun Sep 2 15:37:55 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
......@@ -57,6 +57,7 @@ package tsf_wbgen2_pkg is
csr_delta_read_o : std_logic;
csr_rst_seq_o : std_logic;
csr_delta_ref_o : std_logic_vector(2 downto 0);
csr_raw_mode_o : std_logic;
end record;
constant c_tsf_out_registers_init_value: t_tsf_out_registers := (
......@@ -68,7 +69,8 @@ package tsf_wbgen2_pkg is
offset3_o => (others => '0'),
csr_delta_read_o => '0',
csr_rst_seq_o => '0',
csr_delta_ref_o => (others => '0')
csr_delta_ref_o => (others => '0'),
csr_raw_mode_o => '0'
);
function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers;
......
hdl/rtl/wbgen/timestamp_fifo_wb.wb
View file @ 9a23aeb5
......@@ -161,6 +161,17 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "Raw readout mode";
description = "1: enables readout of raw timestamps";
prefix = "RAW_MODE";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment