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9fb0d486 · Tomasz Wlostowski · 92b7f5e7 · 9fb0d486 · 9fb0d486 · 9fb0d486
Commit 9fb0d486 authored Apr 04, 2015 by Tomasz Wlostowski
11 changed files
--- a/hdl/rtl/circular_buffer.vhd
+++ b/hdl/rtl/circular_buffer.vhd
@@ -281,7 +281,7 @@ begin
        g_data_width               => 32,
        g_size                     => 256,
        g_with_byte_enable         => false,
-        g_addr_conflict_resolution => "dont_care",
+        g_addr_conflict_resolution => "write_first",
        g_dual_clock               => true)
      port map (
        rst_n_i => rst_n_sys_i,
@@ -290,12 +290,12 @@ begin
        aa_i    => tstamp_wr_adr_i(7 downto 0),
        da_i    => tstamp_wr_dat_i(32*i + 31 downto 32*i),
        clkb_i  => clk_sys_i,
-        web_i   => tstamp_rd_we(i),
+        web_i   => '0',
        ab_i    => tdc_mem_wb_adr_i(9 downto 2),
        db_i    => tdc_mem_wb_dat_i,
        qb_o    => mb_data(i));

-    tstamp_rd_we(i) <= '1' when unsigned(tdc_mem_wb_adr_i(1 downto 0)) = i else '0';
+--    tstamp_rd_we(i) <= '1' when unsigned(tdc_mem_wb_adr_i(1 downto 0)) = i else '0';

    process(clk_sys_i)
    begin

--- a/hdl/rtl/clks_rsts_manager.vhd
+++ b/hdl/rtl/clks_rsts_manager.vhd
--- a/hdl/rtl/data_formatting.vhd
+++ b/hdl/rtl/data_formatting.vhd
--- a/hdl/rtl/fmc_tdc_core.vhd
+++ b/hdl/rtl/fmc_tdc_core.vhd
@@ -281,26 +281,6 @@ architecture rtl of fmc_tdc_core is

  signal rst_sys: std_logic;
  
-- Chipscope
-  component chipscope_ila
-    port (
-      CONTROL : inout std_logic_vector(35 downto 0);
-      CLK     : in    std_logic;
-      TRIG0   : in    std_logic_vector(31 downto 0);
-      TRIG1   : in    std_logic_vector(31 downto 0);
-      TRIG2   : in    std_logic_vector(31 downto 0);
-      TRIG3   : in    std_logic_vector(31 downto 0));
-  end component;
-  component chipscope_icon
-    port (
-      CONTROL0 : inout std_logic_vector (35 downto 0));
-  end component;
-  signal CONTROL : std_logic_vector(35 downto 0);
-  signal CLK     : std_logic;
-  signal TRIG0   : std_logic_vector(31 downto 0);
-  signal TRIG1   : std_logic_vector(31 downto 0);
-  signal TRIG2   : std_logic_vector(31 downto 0);
-  signal TRIG3   : std_logic_vector(31 downto 0);

  
 --=================================================================================================
@@ -629,41 +609,6 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
 --------------------------------------------------------------------------------------------------- 
  start_dis_o <= '0';

---------------------------------------------------------------------------------------------------
--                                           CHIPSCOPE                                           --
---------------------------------------------------------------------------------------------------   
-  
--   chipscope_ila_1 : chipscope_ila
--   port map (
--     CONTROL => CONTROL,
--     CLK     => clk_tdc_i,
--     TRIG0   => TRIG0,
--     TRIG1   => TRIG1,
--     TRIG2   => TRIG2,
--     TRIG3   => TRIG3);
--
--  chipscope_icon_1 : chipscope_icon
--   port map (
--     CONTROL0 => CONTROL);
-- 
--  TRIG0(0)            <= utc_p;
--  TRIG0(1)            <= ef1_i;
--  TRIG0(2)            <= acam_intflag_f_edge_p;
--  TRIG0(15 downto 3)  <= roll_over_nb(12 downto 0);
--  TRIG0(16)           <= start_from_fpga;  
--  TRIG0(24 downto 17) <= retrig_nb_offset(7 downto 0);
--  TRIG0(31 downto 25) <= clk_i_cycles_offset(6 downto 0);  
--
--  TRIG1(30 downto 0)  <= acam_tstamp1(30 downto 0);
--  TRIG1(31)           <= acam_tstamp1_ok_p;
--
--  TRIG2(31 downto 0)  <= utc(31 downto 0); 
--  
--  TRIG3(0)            <= tdc_in_fpga_1_i;
--  TRIG3(1)            <= roll_over_incr_recent;
--  TRIG3(2)            <= wrabbit_tai_p_i;
--  TRIG3(31 downto 3)  <= current_retrig_nb(28 downto 0);
-  
 end rtl;
 ----------------------------------------------------------------------------------------------------
 --  architecture ends

--- a/hdl/rtl/fmc_tdc_mezzanine.vhd
+++ b/hdl/rtl/fmc_tdc_mezzanine.vhd
--- a/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/rtl/reg_ctrl.vhd
@@ -72,6 +72,7 @@ use IEEE.NUMERIC_STD.all;    -- conversion functions
 -- Specific library
 library work;
 use work.tdc_core_pkg.all;   -- definitions of types, constants, entities
+use work.gencores_pkg.all;
 use work.wishbone_pkg.all;

 --=================================================================================================
@@ -186,28 +187,109 @@ architecture rtl of reg_ctrl is
  signal wb_out : t_wishbone_slave_out;
  signal rst_n_tdc         : std_logic;

+
+  
 --=================================================================================================
 --                                       architecture begin
 --=================================================================================================
+
+  signal cc_rst_n : std_logic;
+  signal cc_rst_n_or_sys : std_logic;
+
+    component chipscope_ila
+    port (
+      CONTROL : inout std_logic_vector(35 downto 0);
+      CLK     : in    std_logic;
+      TRIG0   : in    std_logic_vector(31 downto 0);
+      TRIG1   : in    std_logic_vector(31 downto 0);
+      TRIG2   : in    std_logic_vector(31 downto 0);
+      TRIG3   : in    std_logic_vector(31 downto 0));
+  end component;
+
+  component chipscope_icon
+    port (
+      CONTROL0 : inout std_logic_vector (35 downto 0));
+  end component;
+
+  signal CONTROL : std_logic_vector(35 downto 0);
+  signal CLK     : std_logic;
+  signal TRIG0   : std_logic_vector(31 downto 0);
+  signal TRIG1   : std_logic_vector(31 downto 0);
+  signal TRIG2   : std_logic_vector(31 downto 0);
+  signal TRIG3   : std_logic_vector(31 downto 0);
+
+  signal slave_in : t_wishbone_slave_in;
+  signal slave_out: t_wishbone_slave_out;
+  
 begin

+  chipscope_ila_1 : chipscope_ila
+    port map (
+      CONTROL => CONTROL,
+      CLK     => clk_tdc_i,
+      TRIG0   => TRIG0,
+      TRIG1   => TRIG1,
+      TRIG2   => TRIG2,
+      TRIG3   => TRIG3);
+
+  chipscope_icon_1 : chipscope_icon
+    port map (
+      CONTROL0 => CONTROL);
+
+  
  rst_n_tdc <= not rst_tdc_i;

+ 
  wb_out.stall <= '0';
  wb_out.err   <= '0';
  wb_out.rty   <= '0';

+  TRIG0 <= wb_out.dat;
+  trig1(15 downto 0) <= wb_in.adr(15 downto 0);
+  trig1(16) <= wb_in.cyc;
+  trig1(17) <= wb_in.stb;
+  trig1(18) <= wb_in.we;
+  trig1(19) <= wb_out.ack;
+
+  TRIG2 <= slave_out.dat;
+  trig3(15 downto 0) <= slave_in.adr(15 downto 0);
+  trig3(16) <= slave_in.cyc;
+  trig3(17) <= slave_in.stb;
+  trig3(18) <= slave_in.we;
+  trig3(19) <= slave_out.ack;
+  trig3(20) <= slave_out.stall;
+  trig3(21) <= slave_out.err;
+  trig3(22) <= slave_out.rty;
+
+  
+  
+ u_sync_tdc_reset : gc_sync_ffs
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_sys_i,
+      data_i   => rst_n_tdc, 
+      synced_o => cc_rst_n);
+
+  cc_rst_n_or_sys <= cc_rst_n and rst_n_sys_i;
+
+
+
+  
+  
  cmp_clks_crossing : xwb_clock_crossing
    port map
    (slave_clk_i    => clk_sys_i,  -- Slave control port: VME interface at 62.5 MHz 
-     slave_rst_n_i  => rst_n_sys_i,
-     slave_i        => slave_i,
-     slave_o        => slave_o,
+     slave_rst_n_i  => cc_rst_n_or_sys, -- reset the slave port also when resetting the TDC
+     slave_i        => slave_in,
+     slave_o        => slave_out,
     master_clk_i   => clk_tdc_i,
     master_rst_n_i => rst_n_tdc,
     master_i       => wb_out,
     master_o       => wb_in);

+  slave_in <= slave_i;
+  slave_o <= slave_out;
+  
  reg_adr <= wb_in.adr(7 downto 0);  -- we are interested in addresses 0:5000 to 0:50FC

 ---------------------------------------------------------------------------------------------------
@@ -225,7 +307,7 @@ begin
        ack_out_pipe1       <= '0';
        ack_out_pipe0       <= '0';
        cyc_in_progress     <= '0';
-      elsif(wb_in.cyc /= '1') then
+      elsif(wb_in.cyc = '0') then
        ack_out_pipe1   <= '0';
        ack_out_pipe0   <= '0';
        cyc_in_progress <= '0';
@@ -347,7 +429,7 @@ begin

      elsif wb_in.cyc = '1' and wb_in.stb = '1' and wb_in.we = '1' then

-		if reg_adr = c_STARTING_UTC_ADR then
+        if reg_adr = c_STARTING_UTC_ADR then
          starting_utc <= wb_in.dat;
        end if;


--- a/hdl/rtl/tdc_core_pkg.vhd
+++ b/hdl/rtl/tdc_core_pkg.vhd
@@ -1018,13 +1018,13 @@ end tdc_core_pkg;
 package body tdc_core_pkg is

  function f_pick(cond:boolean; if_true: std_logic_vector; if_false: std_logic_vector) return std_logic_vector is
-    begin
-      if(cond) then
-        return if_true;
-        else
-          return if_false;
-          end if;
-      end f_pick;
+  begin
+    if(cond) then
+      return if_true;
+    else
+      return if_false;
+    end if;
+  end f_pick;
  
 end tdc_core_pkg;
 --=================================================================================================

--- a/hdl/syn/svec/wr_svec_tdc.xise
+++ b/hdl/syn/svec/wr_svec_tdc.xise
--- a/hdl/testbench/svec/Manifest.py
+++ b/hdl/testbench/svec/Manifest.py
@@ -5,5 +5,5 @@ vlog_opt="+incdir+../../sim +incdir+../include/vme64x_bfm +incdir+../include "

 files = [ "main.sv" ]

-modules = { "local" :  [ "../../top/svec/with_wrabbit" ] }
+modules = { "local" :  [ "../../top/svec" ] }

--- a/hdl/testbench/svec/main.sv
+++ b/hdl/testbench/svec/main.sv
@@ -42,6 +42,9 @@ module main;

   always@(posedge clk_62m5)
     clk_acam <= ~clk_acam;
+
+   wire [27:0] fake_data= 'hcafebab;
+   
   
   
   wr_svec_tdc #(
@@ -74,7 +77,7 @@ module main;
 		     .tdc1_in_fpga_3_i(1'b0),
 		     .tdc1_in_fpga_4_i(1'b0),
 		     .tdc1_in_fpga_5_i(1'b0),
-		     .tdc1_data_bus_io(28'hcafebab),
+		     .tdc1_data_bus_io(fake_data),
 		     

 		     `WIRE_VME_PINS(8)
@@ -127,7 +130,15 @@ module main;
      CBusAccessor acc_casted = CBusAccessor'(acc);

      uint64_t d;
-      const uint64_t tdc1_base = 'h30000;
+      const uint64_t base_tdc1 = 'hc10000;
+      const uint64_t base_tdc2 = 'hc20000;
+      const uint64_t base_vic = 'hc02000;
+      const uint64_t base_carrier = 'hc01000;
+
+      const uint64_t base_tdc_eic = 'h3000;
+      const uint64_t base_tdc_buffer = 'h5000;
+      const uint64_t base_tdc_regs = 'h2000;
+      
      
      #100us;

@@ -137,31 +148,59 @@ module main;
      #15us;


-      $display("Un-reset FMCs...");
+      $display("Reset FMCs...");
+      
+      acc.write(base_carrier + 'hc, 'h3); 
+      #100us;
      
-      acc.write('hc2000c, 'h3); 
+      $display("Un-reset FMCs...");
+      acc.write(base_carrier + 'hc, 'h3); 

      #500us;
      
-      acc.read('hc40000, d); 
-      $display("TDC SDB ID : %x", d);
+      acc.read(base_tdc1 + 'h0, d); 
+      $display("TDC1 SDB ID : %x", d);
+      acc.read(base_tdc2 + 'h0, d); 
+      $display("TDC2 SDB ID : %x", d);
+

+      acc.write(base_tdc1 + base_tdc_regs + 'ha0, 1234);  // set UTC
+      acc.write(base_tdc1 + base_tdc_regs + 'hfc, 1<<9); // load UTC

-      acc.write('hc510a0, 1234);  // set UTC
-      acc.write('hc510fc, 1<<9); // load UTC
+      acc.write(base_tdc1 + base_tdc_eic + 'h04, 'hf); // enable EIC irq

-      acc.write('hc52004, 'hf); // enable EIC irq
+      acc.write(base_tdc1 + base_tdc_regs + 'h84, 'h1f); // enable all ACAM inputs
+      acc.write(base_tdc1 + base_tdc_regs + 'hfc, (1<<0)); // start acquisition

-      acc.write('hc51084, 'h1f); // enable all ACAM inputs
-      acc.write('hc510fc, (1<<0)); // start acquisition
+      
      
         
      #300us;
      forever begin
+	 uint64_t index;
+	 
 	 tdc_pulse <= 1;
 	 #1000ns;
 	 tdc_pulse <= 0;
 	 #10ns;
+
+	 acc.read(base_tdc1 + base_tdc_regs + 'ha8, index);
+	 $display("wr_index %x", index);
+
+	 index -= 16;
+	 
+
+	 acc.read(base_tdc1 + base_tdc_buffer  +index , d);
+	 $display("B0: %x", d);
+	 acc.read(base_tdc1 + base_tdc_buffer  +index+4 , d);
+	 $display("B1: %x", d);
+	 acc.read(base_tdc1 + base_tdc_buffer  +index+8 , d);
+	 $display("B2: %x", d);
+	 acc.read(base_tdc1 + base_tdc_buffer  +index+12 , d);
+	 $display("B3: %x", d);
+	 
+	 
+	 
      end
      
     

--- a/hdl/testbench/svec/wave.do
+++ b/hdl/testbench/svec/wave.do