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FMC TDC 1ns 5cha - Gateware
Commits
bb0af513
Commit
bb0af513
authored
Sep 11, 2018
by
Tomasz Wlostowski
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rtl: clean up debug metadata and pass it to the DMA engine
parent
6e2113b9
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Showing
2 changed files
with
77 additions
and
40 deletions
+77
-40
tdc_ts_addsub.vhd
hdl/rtl/tdc_ts_addsub.vhd
+6
-2
timestamp_convert_filter.vhd
hdl/rtl/timestamp_convert_filter.vhd
+71
-38
No files found.
hdl/rtl/tdc_ts_addsub.vhd
View file @
bb0af513
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Company : CERN
-- Created : 2011-08-29
-- Created : 2011-08-29
-- Last update: 2018-09-
03
-- Last update: 2018-09-
10
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -74,6 +74,7 @@ architecture rtl of tdc_ts_addsub is
...
@@ -74,6 +74,7 @@ architecture rtl of tdc_ts_addsub is
coarse
:
signed
(
31
downto
0
);
coarse
:
signed
(
31
downto
0
);
frac
:
signed
(
15
downto
0
);
frac
:
signed
(
15
downto
0
);
seq
:
std_logic_vector
(
31
downto
0
);
seq
:
std_logic_vector
(
31
downto
0
);
meta
:
std_logic_vector
(
31
downto
0
);
slope
:
std_logic
;
slope
:
std_logic
;
end
record
;
end
record
;
...
@@ -101,6 +102,7 @@ begin -- rtl
...
@@ -101,6 +102,7 @@ begin -- rtl
sums
(
0
)
.
tai
<=
signed
(
resize
(
unsigned
(
a_i
.
tai
)
+
unsigned
(
b_i
.
tai
),
33
)
);
sums
(
0
)
.
tai
<=
signed
(
resize
(
unsigned
(
a_i
.
tai
)
+
unsigned
(
b_i
.
tai
),
33
)
);
sums
(
0
)
.
seq
<=
a_i
.
seq
;
sums
(
0
)
.
seq
<=
a_i
.
seq
;
sums
(
0
)
.
slope
<=
a_i
.
slope
;
sums
(
0
)
.
slope
<=
a_i
.
slope
;
sums
(
0
)
.
meta
<=
a_i
.
meta
;
sums
(
0
)
.
frac
<=
signed
(
resize
(
unsigned
(
a_i
.
frac
),
16
)
+
resize
(
unsigned
(
b_i
.
frac
),
16
)
);
sums
(
0
)
.
frac
<=
signed
(
resize
(
unsigned
(
a_i
.
frac
),
16
)
+
resize
(
unsigned
(
b_i
.
frac
),
16
)
);
sums
(
0
)
.
coarse
<=
signed
(
resize
(
unsigned
(
a_i
.
coarse
),
sums
(
0
)
.
coarse
'length
)
+
sums
(
0
)
.
coarse
<=
signed
(
resize
(
unsigned
(
a_i
.
coarse
),
sums
(
0
)
.
coarse
'length
)
+
...
@@ -127,6 +129,7 @@ begin -- rtl
...
@@ -127,6 +129,7 @@ begin -- rtl
pipe
(
1
)
<=
pipe
(
0
);
pipe
(
1
)
<=
pipe
(
0
);
sums
(
1
)
.
seq
<=
sums
(
0
)
.
seq
;
sums
(
1
)
.
seq
<=
sums
(
0
)
.
seq
;
sums
(
1
)
.
meta
<=
sums
(
0
)
.
meta
;
sums
(
1
)
.
slope
<=
sums
(
0
)
.
slope
;
sums
(
1
)
.
slope
<=
sums
(
0
)
.
slope
;
...
@@ -190,6 +193,7 @@ begin -- rtl
...
@@ -190,6 +193,7 @@ begin -- rtl
pipe
(
3
)
<=
pipe
(
2
);
pipe
(
3
)
<=
pipe
(
2
);
sums
(
3
)
.
seq
<=
sums
(
2
)
.
seq
;
sums
(
3
)
.
seq
<=
sums
(
2
)
.
seq
;
sums
(
3
)
.
slope
<=
sums
(
2
)
.
slope
;
sums
(
3
)
.
slope
<=
sums
(
2
)
.
slope
;
sums
(
3
)
.
meta
<=
sums
(
2
)
.
meta
;
if
(
unf_coarse
=
"10"
)
then
if
(
unf_coarse
=
"10"
)
then
sums
(
3
)
.
coarse
<=
sums
(
2
)
.
coarse
+
g_coarse_range
;
sums
(
3
)
.
coarse
<=
sums
(
2
)
.
coarse
+
g_coarse_range
;
...
@@ -221,5 +225,5 @@ begin -- rtl
...
@@ -221,5 +225,5 @@ begin -- rtl
q_o
.
frac
<=
std_logic_vector
(
sums
(
c_NUM_PIPELINE_STAGES
-1
)
.
frac
(
11
downto
0
));
q_o
.
frac
<=
std_logic_vector
(
sums
(
c_NUM_PIPELINE_STAGES
-1
)
.
frac
(
11
downto
0
));
q_o
.
seq
<=
sums
(
c_NUM_PIPELINE_STAGES
-1
)
.
seq
;
q_o
.
seq
<=
sums
(
c_NUM_PIPELINE_STAGES
-1
)
.
seq
;
q_o
.
slope
<=
sums
(
c_NUM_PIPELINE_STAGES
-1
)
.
slope
;
q_o
.
slope
<=
sums
(
c_NUM_PIPELINE_STAGES
-1
)
.
slope
;
q_o
.
meta
<=
sums
(
c_NUM_PIPELINE_STAGES
-1
)
.
meta
;
end
rtl
;
end
rtl
;
hdl/rtl/timestamp_convert_filter.vhd
View file @
bb0af513
...
@@ -5,6 +5,7 @@ use ieee.NUMERIC_STD.all;
...
@@ -5,6 +5,7 @@ use ieee.NUMERIC_STD.all;
use
work
.
tdc_core_pkg
.
all
;
use
work
.
tdc_core_pkg
.
all
;
use
work
.
gencores_pkg
.
all
;
use
work
.
gencores_pkg
.
all
;
use
work
.
genram_pkg
.
all
;
entity
timestamp_convert_filter
is
entity
timestamp_convert_filter
is
port
(
port
(
...
@@ -18,7 +19,7 @@ entity timestamp_convert_filter is
...
@@ -18,7 +19,7 @@ entity timestamp_convert_filter is
raw_enable_i
:
in
std_logic_vector
(
4
downto
0
);
raw_enable_i
:
in
std_logic_vector
(
4
downto
0
);
-- raw timestamp input, clk_tdc_i domain
-- raw timestamp input, clk_tdc_i domain
ts_i
:
in
t_
raw_
acam_timestamp
;
ts_i
:
in
t_acam_timestamp
;
ts_valid_i
:
in
std_logic
;
ts_valid_i
:
in
std_logic
;
-- converted and filtered timestamp output, clk_sys_i domain
-- converted and filtered timestamp output, clk_sys_i domain
...
@@ -68,35 +69,62 @@ architecture rtl of timestamp_convert_filter is
...
@@ -68,35 +69,62 @@ architecture rtl of timestamp_convert_filter is
signal
ts_valid_sys
:
std_logic
;
signal
ts_valid_sys
:
std_logic
;
signal
ts_latched
:
t_raw_acam_timestamp
;
signal
fifo_we
,
fifo_rd
,
fifo_empty
,
fifo_full
,
fifo_rd_d
:
std_logic
;
signal
fifo_d
,
fifo_q
:
std_logic_vector
(
127
downto
0
);
signal
ts_fifo_out
:
t_acam_timestamp
;
signal
ts_valid_preoffset
,
ts_ready_preoffset
,
ts_valid_postoffset
:
std_logic_vector
(
4
downto
0
);
signal
ts_valid_preoffset
,
ts_ready_preoffset
,
ts_valid_postoffset
:
std_logic_vector
(
4
downto
0
);
signal
ts_preoffset
,
ts_postoffset
:
t_tdc_timestamp_array
(
4
downto
0
);
signal
ts_preoffset
,
ts_postoffset
:
t_tdc_timestamp_array
(
4
downto
0
);
signal
s1_meta
,
s2_meta
,
s3_meta
:
std_logic_vector
(
31
downto
0
);
begin
function
f_pack_acam_timestamp
(
ts
:
t_acam_timestamp
)
return
std_logic_vector
is
variable
rv
:
std_logic_vector
(
127
downto
0
);
begin
rv
(
31
downto
0
)
:
=
ts
.
tai
;
rv
(
63
downto
32
)
:
=
ts
.
coarse
;
rv
(
80
downto
64
)
:
=
ts
.
n_bins
;
rv
(
83
downto
81
)
:
=
ts
.
channel
;
rv
(
84
)
:
=
ts
.
slope
;
rv
(
116
downto
85
)
:
=
ts
.
meta
;
return
rv
;
end
f_pack_acam_timestamp
;
function
f_unpack_acam_timestamp
(
p
:
std_logic_vector
)
return
t_acam_timestamp
is
variable
ts
:
t_acam_timestamp
;
begin
ts
.
tai
:
=
p
(
31
downto
0
);
ts
.
coarse
:
=
p
(
63
downto
32
);
ts
.
n_bins
:
=
p
(
80
downto
64
);
ts
.
channel
:
=
p
(
83
downto
81
);
ts
.
slope
:
=
p
(
84
);
ts
.
meta
:
=
p
(
116
downto
85
);
return
ts
;
end
f_unpack_acam_timestamp
;
begin
fifo_d
<=
f_pack_acam_timestamp
(
ts_i
);
fifo_we
<=
ts_valid_i
;
U_Sync_TS_Valid
:
gc_pulse_synchronizer2
U_Sync_FIFO
:
generic_async_fifo
generic
map
(
g_data_width
=>
128
,
g_size
=>
16
,
g_show_ahead
=>
false
)
port
map
(
port
map
(
clk_in_i
=>
clk_tdc_i
,
rst_n_i
=>
rst_sys_n_i
,
rst_in_n_i
=>
rst_tdc_n_i
,
clk_wr_i
=>
clk_tdc_i
,
clk_out_i
=>
clk_sys_i
,
d_i
=>
fifo_d
,
rst_out_n_i
=>
rst_sys_n_i
,
we_i
=>
fifo_we
,
d_ready_o
=>
open
,
clk_rd_i
=>
clk_sys_i
,
d_p_i
=>
ts_valid_i
,
q_o
=>
fifo_q
,
q_p_o
=>
ts_valid_sys
);
rd_i
=>
fifo_rd
,
rd_empty_o
=>
fifo_empty
);
process
(
clk_tdc_i
)
ts_fifo_out
<=
f_unpack_acam_timestamp
(
fifo_q
);
begin
fifo_rd
<=
not
fifo_empty
;
if
rising_edge
(
clk_tdc_i
)
then
if
ts_valid_i
=
'1'
then
ts_latched
<=
ts_i
;
end
if
;
end
if
;
end
process
;
process
(
clk_sys_i
)
process
(
clk_sys_i
)
begin
begin
...
@@ -105,18 +133,22 @@ begin
...
@@ -105,18 +133,22 @@ begin
s1_valid
<=
'0'
;
s1_valid
<=
'0'
;
s2_valid
<=
'0'
;
s2_valid
<=
'0'
;
s3_valid
<=
'0'
;
s3_valid
<=
'0'
;
fifo_rd_d
<=
'0'
;
else
else
fifo_rd_d
<=
fifo_rd
;
-- 64/125 = 4096/8000: reduce fraction to avoid 64-bit division
-- 64/125 = 4096/8000: reduce fraction to avoid 64-bit division
-- frac = hwts->bins * 81 * 64 / 125;
-- frac = hwts->bins * 81 * 64 / 125;
-- stage 1: scale frac
-- stage 1: scale frac
s1_frac_scaled
<=
resize
((
unsigned
(
ts_i
.
n_bins
)
*
c_FINE_SF
)
srl
c_FINE_SHIFT
,
32
);
s1_frac_scaled
<=
resize
((
unsigned
(
ts_fifo_out
.
n_bins
)
*
c_FINE_SF
)
srl
c_FINE_SHIFT
,
32
);
s1_coarse
<=
unsigned
(
ts_i
.
coarse
);
s1_coarse
<=
unsigned
(
ts_fifo_out
.
coarse
);
s1_tai
<=
unsigned
(
ts_i
.
tai
);
s1_tai
<=
unsigned
(
ts_fifo_out
.
tai
);
s1_edge
<=
ts_i
.
slope
;
s1_edge
<=
ts_fifo_out
.
slope
;
s1_channel
<=
ts_i
.
channel
;
s1_channel
<=
ts_fifo_out
.
channel
;
s1_valid
<=
ts_valid_sys
;
s1_meta
<=
x"0000"
&
"000"
&
ts_fifo_out
.
n_bins
(
12
downto
0
);
s1_valid
<=
fifo_rd_d
;
-- stage 2: adjust coarse
-- stage 2: adjust coarse
s2_frac
<=
s1_frac_scaled
(
11
downto
0
);
s2_frac
<=
s1_frac_scaled
(
11
downto
0
);
...
@@ -124,6 +156,7 @@ begin
...
@@ -124,6 +156,7 @@ begin
s2_tai
<=
s1_tai
;
s2_tai
<=
s1_tai
;
s2_edge
<=
s1_edge
;
s2_edge
<=
s1_edge
;
s2_channel
<=
s1_channel
;
s2_channel
<=
s1_channel
;
s2_meta
<=
s1_meta
;
s2_valid
<=
s1_valid
;
s2_valid
<=
s1_valid
;
-- stage 3: roll-over coarse
-- stage 3: roll-over coarse
...
@@ -138,6 +171,7 @@ begin
...
@@ -138,6 +171,7 @@ begin
s3_tai
<=
s2_tai
;
s3_tai
<=
s2_tai
;
end
if
;
end
if
;
s3_meta
<=
s2_meta
;
s3_frac
<=
s2_frac
;
s3_frac
<=
s2_frac
;
s3_edge
<=
s2_edge
;
s3_edge
<=
s2_edge
;
s3_channel
<=
s2_channel
;
s3_channel
<=
s2_channel
;
...
@@ -151,7 +185,7 @@ begin
...
@@ -151,7 +185,7 @@ begin
s3_ts
.
tai
<=
std_logic_vector
(
s3_tai
);
s3_ts
.
tai
<=
std_logic_vector
(
s3_tai
);
s3_ts
.
slope
<=
s3_edge
;
s3_ts
.
slope
<=
s3_edge
;
s3_ts
.
channel
<=
s3_channel
;
s3_ts
.
channel
<=
s3_channel
;
s3_ts
.
meta
<=
s3_meta
;
gen_channels
:
for
i
in
0
to
4
generate
gen_channels
:
for
i
in
0
to
4
generate
...
@@ -207,6 +241,7 @@ begin
...
@@ -207,6 +241,7 @@ begin
ts_preoffset
(
i
)
.
frac
<=
channels
(
i
)
.
last_ts
.
frac
;
ts_preoffset
(
i
)
.
frac
<=
channels
(
i
)
.
last_ts
.
frac
;
ts_preoffset
(
i
)
.
channel
<=
channels
(
i
)
.
last_ts
.
channel
;
ts_preoffset
(
i
)
.
channel
<=
channels
(
i
)
.
last_ts
.
channel
;
ts_preoffset
(
i
)
.
slope
<=
channels
(
i
)
.
last_ts
.
slope
;
ts_preoffset
(
i
)
.
slope
<=
channels
(
i
)
.
last_ts
.
slope
;
ts_preoffset
(
i
)
.
meta
<=
channels
(
i
)
.
last_ts
.
meta
;
ts_valid_preoffset
(
i
)
<=
'1'
;
ts_valid_preoffset
(
i
)
<=
'1'
;
...
@@ -217,7 +252,8 @@ begin
...
@@ -217,7 +252,8 @@ begin
channels
(
i
)
.
seq
<=
channels
(
i
)
.
seq
+
1
;
channels
(
i
)
.
seq
<=
channels
(
i
)
.
seq
+
1
;
ts_preoffset
(
i
)
.
seq
<=
std_logic_vector
(
channels
(
i
)
.
seq
);
ts_preoffset
(
i
)
.
seq
<=
std_logic_vector
(
channels
(
i
)
.
seq
);
end
if
;
end
if
;
else
ts_valid_preoffset
(
i
)
<=
'0'
;
end
if
;
end
if
;
else
else
ts_valid_preoffset
(
i
)
<=
'0'
;
ts_valid_preoffset
(
i
)
<=
'0'
;
...
@@ -251,13 +287,10 @@ begin
...
@@ -251,13 +287,10 @@ begin
if
raw_enable_i
(
i
)
=
'1'
then
if
raw_enable_i
(
i
)
=
'1'
then
if
ts_valid_sys
=
'1'
and
unsigned
(
ts_latched
.
channel
)
=
i
then
--if ts_valid_sys = '1' and unsigned(ts_latched.channel) = i then
ts_valid_o
(
i
)
<=
'1'
;
-- ts_valid_o(i) <= '1';
ts_o
(
i
)
.
tai
<=
ts_latched
.
tai
;
-- ts_o(i).raw <= ts_latched.raw;
ts_o
(
i
)
.
coarse
<=
ts_latched
.
coarse
;
--end if;
-- ts_o(i).frac <= ts_latched.n_bins;
ts_o
(
i
)
.
seq
<=
"000000000000000"
&
ts_latched
.
n_bins
;
end
if
;
else
else
...
...
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