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FMC TDC 1ns 5cha - Gateware
Commit c098769a authored by egousiou's avatar egousiou
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corrections on VME interrupts controller (was not working with multiple boards) 

git-svn-id: http://svn.ohwr.org/fmc-tdc@141 85dfdc96-de2c-444c-878d-45b388be74a9
parent 6103f3f1
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hdl/ip_cores/VMEcore/VME64xCore_Top.vhd
View file @ c098769a
......@@ -430,14 +430,15 @@ begin
--------------------------------------------------------------------------------
-- Interrupter
Inst_VME_IRQ_Controller : VME_IRQ_Controller
generic map (
g_retry_timeout => 62500 -- 1ms timeout
)
port map(
clk_i => clk_i,
reset_n_i => s_reset_IRQ, -- asserted when low
VME_IACKIN_n_i => VME_IACKIN_n_oversampled,
VME_AS_n_i => VME_AS_n_oversampled,
VME_AS1_n_i => VME_AS_n_i,
VME_DS_n_i => VME_DS_n_oversampled,
VME_LWORD_n_i => VME_LWORD_n_i,
VME_ADDR_123_i => VME_ADDR_i(3 downto 1),
INT_Level_i => s_INT_Level,
INT_Vector_i => s_INT_Vector ,
......
hdl/ip_cores/VMEcore/VME_IRQ_Controller.vhd
View file @ c098769a
......@@ -123,9 +123,9 @@ entity VME_IRQ_Controller is
reset_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_AS1_n_i : in std_logic; -- this is the AS* not triple sampled
--VME_AS1_n_i : in std_logic; -- this is the AS* not triple sampled
VME_DS_n_i : in std_logic_vector (1 downto 0);
VME_LWORD_n_i : in std_logic;
--VME_LWORD_n_i : in std_logic;
VME_ADDR_123_i : in std_logic_vector (2 downto 0);
INT_Level_i : in std_logic_vector (7 downto 0);
INT_Vector_i : in std_logic_vector (7 downto 0);
......@@ -141,372 +141,188 @@ end VME_IRQ_Controller;
-- Architecture declaration
--===========================================================================
architecture Behavioral of VME_IRQ_Controller is
function f_select_irq_line (level : std_logic_vector) return std_logic_vector is
begin
case level(7 downto 0) is
when x"01" => return "1111110";
when x"02" => return "1111101";
when x"03" => return "1111011";
when x"04" => return "1110111";
when x"05" => return "1101111";
when x"06" => return "1011111";
when x"07" => return "0111111";
when others => return "1111111";
end case;
end f_select_irq_Line;
--input signals
-- signal s_INT_Req_sample : std_logic;
signal int_trigger_p : std_logic;
signal retry_count : unsigned(23 downto 0);
type t_retry_state is (R_IDLE, R_IRQ, R_WAIT_RETRY);
signal retry_state : t_retry_state;
--output signals
signal s_DTACK_OE_o : std_logic;
signal s_enable : std_logic;
signal s_IRQ : std_logic_vector(6 downto 0);
signal s_Data : std_logic_vector(31 downto 0);
--
signal s_AS_FallingEdge : std_logic;
signal s_AS_RisingEdge : std_logic;
type t_MainFSM is (IDLE, IRQ, WAIT_AS, WAIT_DS, CHECK, DATA_OUT, DTACK, IACKOUT1, IACKOUT2);
signal s_currs, s_nexts : t_MainFSM;
signal s_ack_int : std_logic;
signal s_VME_ADDR_123_latched : std_logic_vector(2 downto 0);
signal s_VME_DS_latched : std_logic_vector(1 downto 0);
signal s_ADDRmatch : std_logic;
signal s_FSM_IRQ : t_FSM_IRQ;
-- signal int_trigger_p : std_logic;
-- signal retry_count : unsigned(23 downto 0);
-- type t_retry_state is (R_IDLE, R_IRQ, R_WAIT_RETRY);
type t_retry_state is (WAIT_IRQ, WAIT_RETRY);
type t_main_state is (IDLE, IRQ, WAIT_AS, WAIT_DS, CHECK, DATA_OUT, DTACK, IACKOUT1, IACKOUT2, SCHEDULE_IRQ);
signal as_n_d0 : std_logic;
signal as_rising_p, as_falling_p : std_logic;
signal vme_addr_latched : std_logic_vector(2 downto 0);
signal state : t_main_state;
signal retry_state : t_retry_state;
signal retry_count : unsigned(23 downto 0);
signal retry_mask : std_logic;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
-- Input sampling and edge detection
ASrisingEdge : RisEdgeDetection
port map (
sig_i => VME_AS_n_i,
clk_i => clk_i,
RisEdge_o => s_AS_RisingEdge
);
ASfallingEdge : FallingEdgeDetection
port map (
sig_i => VME_AS_n_i,
clk_i => clk_i,
FallEdge_o => s_AS_FallingEdge
);
-- INT_ReqinputSample : process(clk_i)
p_int_retry : process(clk_i)
p_detect_as_edges : process(clk_i)
begin
if rising_edge(clk_i) then
if reset_n_i = '0' then
int_trigger_p <= '0';
retry_count <= (others => '0');
retry_state <= R_IDLE;
else
case retry_state is
when R_IDLE =>
if(INT_Req_i = '1') then
retry_state <= R_IRQ;
end if;
when R_IRQ =>
retry_count <= (others => '0');
int_trigger_p <= '1';
retry_state <= R_WAIT_RETRY;
when R_WAIT_RETRY =>
int_trigger_p <= '0';
if(INT_Req_i = '1') then
retry_count <= retry_count + 1;
if(retry_count = g_retry_timeout) then
retry_state <= R_IRQ;
end if;
else
retry_state <= R_IDLE;
end if;
end case;
end if;
--s_INT_Req_sample <= INT_Req_i;
as_n_d0 <= VME_AS_n_i;
as_rising_p <= not as_n_d0 and VME_AS_n_i;
as_falling_p <= as_n_d0 and not VME_AS_n_i;
end if;
end process;
--Output registers:
DTACKOutputSample : process(clk_i)
begin
if rising_edge(clk_i) then
VME_DTACK_n_o <= s_FSM_IRQ.s_DTACK;
end if;
end process;
DataDirOutputSample : process(clk_i)
begin
if rising_edge(clk_i) then
VME_DATA_DIR_o <= s_FSM_IRQ.s_DataDir;
end if;
end process;
DTACKOEOutputSample : process(clk_i)
begin
if rising_edge(clk_i) then
s_DTACK_OE_o <= s_FSM_IRQ.s_DTACK_OE;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if s_FSM_IRQ.s_resetIRQ = '1' then
VME_IRQ_n_o <= (others => '1');
elsif s_FSM_IRQ.s_enableIRQ = '1' then
VME_IRQ_n_o <= s_IRQ;
if as_falling_p = '1' then
vme_addr_latched <= VME_ADDR_123_i;
end if;
end if;
end process;
process(clk_i)
-- DataDirOutputSample : process(clk_i)
p_retry_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
VME_DATA_o <= s_Data;
end if;
end process;
if reset_n_i = '0' then
retry_mask <= '1';
retry_state <= WAIT_IRQ;
else
case retry_state is
when WAIT_IRQ =>
if(state = IRQ and INT_Req_i = '1') then
retry_state <= WAIT_RETRY;
retry_count <= (others => '0');
retry_mask <= '0';
else
retry_mask <= '1';
end if;
when WAIT_RETRY =>
if(INT_Req_i = '0') then
retry_state <= WAIT_IRQ;
else
retry_count <= retry_count + 1;
if(retry_count = g_retry_timeout) then
retry_state <= WAIT_IRQ;
end if;
end if;
end case;
end if;
end if;
end process;
-- Update current state
process(clk_i)
p_main_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
if reset_n_i = '0' then
s_currs <= IDLE;
state <= IDLE;
VME_IACKOUT_n_o <= '1';
VME_DATA_DIR_o <= '0';
VME_DTACK_n_o <= '1';
VME_DTACK_OE_o <= '0';
else
s_currs <= s_nexts;
end if;
end if;
end process;
-- Update next state
process(s_currs, int_trigger_p, VME_AS_n_i, VME_DS_n_i, s_ack_int, VME_IACKIN_n_i, s_AS_RisingEdge)
begin
case s_currs is
when IDLE =>
--if s_INT_Req_sample = '1' and VME_IACKIN_n_i = '1' then
if int_trigger_p = '1' and VME_IACKIN_n_i = '1' then
s_nexts <= IRQ;
elsif VME_IACKIN_n_i = '0' then
s_nexts <= IACKOUT2;
else
s_nexts <= IDLE;
end if;
case state is
when IDLE =>
when IRQ =>
if VME_IACKIN_n_i = '0' then -- Each Interrupter who is driving an interrupt request line
-- low waits for a falling edge on IACKIN input -->
-- the IRQ_Controller have to detect a falling edge on the IACKIN.
s_nexts <= WAIT_AS;
else
s_nexts <= IRQ;
end if;
VME_IACKOUT_n_o <= '1';
VME_DATA_DIR_o <= '0';
VME_DTACK_n_o <= '1';
VME_DTACK_OE_o <= '0';
VME_IRQ_n_o <= (others => '1');
when WAIT_AS =>
if VME_AS_n_i = '0' then -- NOT USE FALLING EDGE HERE!
s_nexts <= WAIT_DS;
else
s_nexts <= WAIT_AS;
end if;
when WAIT_DS =>
if VME_DS_n_i /= "11" then
s_nexts <= CHECK;
else
s_nexts <= WAIT_DS;
end if;
-- when LATCH_DS => -- this state is necessary only for D16 ans D32 Interrupters
-- s_nexts <= CHECK;
-- If the interrupter is D16 or D32 add a generic number of LATCH_DS state like in the VME_bus component.
when CHECK =>
if s_ack_int = '1' then
s_nexts <= DATA_OUT; -- The Interrupter send the INT_Vector
else
s_nexts <= IACKOUT1; -- the Interrupter must pass a falling edge on the IACKOUT output
end if;
when IACKOUT1 =>
if s_AS_RisingEdge = '1' then
s_nexts <= IRQ;
else
s_nexts <= IACKOUT1;
end if;
when DATA_OUT =>
s_nexts <= DTACK;
when IACKOUT2 =>
if s_AS_RisingEdge = '1' then
s_nexts <= IDLE;
else
s_nexts <= IACKOUT2;
end if;
when DTACK =>
if s_AS_RisingEdge = '1' then
s_nexts <= IDLE;
else
s_nexts <= DTACK;
end if;
when others => null;
end case;
end process;
-- Update Outputs
-- Mealy FSM
process(s_currs, VME_AS1_n_i)
begin
case s_currs is
when IDLE =>
s_FSM_IRQ.s_IACKOUT <= '1';
s_FSM_IRQ.s_DataDir <= '0';
s_FSM_IRQ.s_DTACK <= '1';
s_FSM_IRQ.s_enableIRQ <= '0';
s_FSM_IRQ.s_resetIRQ <= '1';
s_FSM_IRQ.s_DSlatch <= '0';
s_FSM_IRQ.s_DTACK_OE <= '0';
when IRQ =>
s_FSM_IRQ.s_IACKOUT <= '1';
s_FSM_IRQ.s_DataDir <= '0';
s_FSM_IRQ.s_DTACK <= '1';
s_FSM_IRQ.s_DSlatch <= '0';
s_FSM_IRQ.s_DTACK_OE <= '0';
s_FSM_IRQ.s_enableIRQ <= '1';
s_FSM_IRQ.s_resetIRQ <= '0';
when WAIT_AS =>
s_FSM_IRQ.s_IACKOUT <= '1';
s_FSM_IRQ.s_DataDir <= '0';
s_FSM_IRQ.s_DTACK <= '1';
s_FSM_IRQ.s_enableIRQ <= '0';
s_FSM_IRQ.s_DSlatch <= '0';
s_FSM_IRQ.s_DTACK_OE <= '0';
s_FSM_IRQ.s_resetIRQ <= '0';
when WAIT_DS =>
s_FSM_IRQ.s_IACKOUT <= '1';
s_FSM_IRQ.s_DataDir <= '0';
s_FSM_IRQ.s_DTACK <= '1';
s_FSM_IRQ.s_enableIRQ <= '0';
s_FSM_IRQ.s_DSlatch <= '0';
s_FSM_IRQ.s_DTACK_OE <= '0';
s_FSM_IRQ.s_resetIRQ <= '0';
-- when LATCH_DS =>
-- s_IACKOUT <= '1';
-- s_DataDir <= '0';
-- s_DTACK <= '1';
-- s_enableIRQ <= '0';
-- s_resetIRQ <= '0';
-- s_DSlatch <= '1';
-- s_DTACK_OE <= '0';
when CHECK =>
s_FSM_IRQ.s_IACKOUT <= '1';
s_FSM_IRQ.s_DataDir <= '0';
s_FSM_IRQ.s_DTACK <= '1';
s_FSM_IRQ.s_enableIRQ <= '0';
s_FSM_IRQ.s_DSlatch <= '0';
s_FSM_IRQ.s_DTACK_OE <= '0';
s_FSM_IRQ.s_resetIRQ <= '0';
when IACKOUT1 =>
s_FSM_IRQ. s_DataDir <= '0';
s_FSM_IRQ. s_DTACK <= '1';
s_FSM_IRQ. s_enableIRQ <= '0';
s_FSM_IRQ. s_DSlatch <= '0';
s_FSM_IRQ. s_DTACK_OE <= '0';
s_FSM_IRQ.s_resetIRQ <= '0';
s_FSM_IRQ.s_IACKOUT <= '0';
when IACKOUT2 =>
s_FSM_IRQ. s_DataDir <= '0';
s_FSM_IRQ. s_DTACK <= '1';
s_FSM_IRQ. s_enableIRQ <= '0';
s_FSM_IRQ. s_DSlatch <= '0';
s_FSM_IRQ. s_DTACK_OE <= '0';
s_FSM_IRQ.s_resetIRQ <= '0';
s_FSM_IRQ.s_IACKOUT <= '0';
when DATA_OUT =>
s_FSM_IRQ.s_IACKOUT <= '1';
s_FSM_IRQ. s_DTACK <= '1';
s_FSM_IRQ. s_enableIRQ <= '0';
s_FSM_IRQ. s_DSlatch <= '0';
s_FSM_IRQ.s_DataDir <= '1';
s_FSM_IRQ.s_resetIRQ <= '0';
s_FSM_IRQ.s_DTACK_OE <= '1';
if INT_Req_i = '1' and retry_mask = '1' then
if VME_IACKIN_n_i /= '0' then
state <= IRQ;
VME_IRQ_n_o <= f_select_irq_line(INT_Level_i);
else
-- IACK in progress, wait until idle
state <= SCHEDULE_IRQ;
end if;
-- just forward IACK to the next card in the daisy chain.
elsif VME_IACKIN_n_i = '0' and VME_DS_n_i /= "11" then
VME_IACKOUT_n_o <= '0';
state <= IACKOUT2;
end if;
when SCHEDULE_IRQ =>
if(VME_IACKIN_n_i /= '0') then
VME_IRQ_n_o <= f_select_irq_line(INT_Level_i);
state <= IRQ;
end if;
when IRQ =>
if VME_IACKIN_n_i = '0' then
-- Each Interrupter who is driving an interrupt request line
-- low waits for a falling edge on IACKIN input -->
-- the IRQ_Controller have to detect a falling edge on the IACKIN.
state <= WAIT_AS;
end if;
when DTACK =>
s_FSM_IRQ.s_IACKOUT <= '1';
s_FSM_IRQ. s_enableIRQ <= '0';
s_FSM_IRQ. s_resetIRQ <= '1';
s_FSM_IRQ. s_DSlatch <= '0';
s_FSM_IRQ.s_DataDir <= '1';
s_FSM_IRQ.s_DTACK <= '0';
s_FSM_IRQ.s_DTACK_OE <= '1';
when WAIT_AS =>
if VME_AS_n_i = '0' then
state <= WAIT_DS;
end if;
-- when others => null;
end case;
end process;
when WAIT_DS =>
if VME_DS_n_i /= "11" then
state <= CHECK;
end if;
-- This process provides the IRQ vector
process(INT_Level_i)
begin
case (INT_Level_i) is
when "00000001" => s_IRQ <= "1111110";
when "00000010" => s_IRQ <= "1111101";
when "00000011" => s_IRQ <= "1111011";
when "00000100" => s_IRQ <= "1110111";
when "00000101" => s_IRQ <= "1101111";
when "00000110" => s_IRQ <= "1011111";
when "00000111" => s_IRQ <= "0111111";
when others => s_IRQ <= "1111111";
end case;
end process;
when CHECK =>
if vme_addr_latched = INT_Level_i(2 downto 0) then
state <= DATA_OUT; -- The Interrupter send the INT_Vector
VME_DATA_DIR_o <= '1';
VME_DTACK_OE_o <= '1';
VME_DTACK_n_o <= '1';
else
state <= IACKOUT1; -- the Interrupter must pass a falling edge on the IACKOUT output
VME_IACKOUT_n_o <= '0';
end if;
-- This process sampling the address lines on AS falling edge
process(clk_i)
begin
if rising_edge(clk_i) then
if reset_n_i = '0' then
s_VME_ADDR_123_latched <= (others => '0');
elsif s_AS_FallingEdge = '1' then
s_VME_ADDR_123_latched <= VME_ADDR_123_i;
end if;
end if;
end process;
when IACKOUT1 =>
if as_rising_p = '1' then
VME_IACKOUT_n_o <= '1';
state <= IRQ;
end if;
-- Data strobo latch
process(clk_i)
begin
if rising_edge(clk_i) then
if reset_n_i = '0' then
s_VME_DS_latched <= (others => '0');
elsif s_FSM_IRQ.s_DSlatch = '1' then
s_VME_DS_latched <= VME_DS_n_i;
end if;
end if;
end process;
when IACKOUT2 =>
if VME_AS_n_i = '1' then
VME_IACKOUT_n_o <= '1';
state <= IDLE;
end if;
when DATA_OUT =>
VME_DTACK_n_o <= '0';
VME_IRQ_n_o <= (others => '1');
state <= DTACK;
when DTACK =>
if as_rising_p = '1' then
VME_DTACK_OE_o <= '0';
VME_DATA_DIR_o <= '0';
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
--This process check the A01 A02 A03:
process(clk_i)
begin
if rising_edge(clk_i) then
if reset_n_i = '0' then
s_ADDRmatch <= '0';
elsif unsigned(INT_Level_i) = unsigned(s_VME_ADDR_123_latched) then
s_ADDRmatch <= '1';
else
s_ADDRmatch <= '0';
end if;
end if;
end process;
s_ack_int <= s_ADDRmatch; --D08 Interrupter
-- s_ack_int <= (not(s_VME_DS_latched(1))) and s_ADDRmatch and (not(VME_LWORD_n_i))
-- for a D32 Interrupter
VME_DATA_o <= x"000000" & INT_Vector_i;
s_Data <= x"000000" & INT_Vector_i;
s_enable <= ((not s_FSM_IRQ.s_DTACK) and (s_AS_RisingEdge));
-- the INT_Vector is in the D0:D7 lines (byte3 in big endian order)
VME_DTACK_OE_o <= s_DTACK_OE_o;
VME_IACKOUT_n_o <= s_FSM_IRQ.s_IACKOUT;
end Behavioral;
--===========================================================================
-- Architecture end
......
hdl/ip_cores/VMEcore/vme64x_pack.vhd
View file @ c098769a
......@@ -361,6 +361,7 @@ constant c_STOP : integer := (to_integer("00" & c_FUNC7_ADER_0_addr(18 downto 2)
DECIDE_NEXT_CYCLE,
INCREMENT_ADDR,
SET_DATA_PHASE
-- UGLY_WAIT_TO_MAKE_DECODING_WORK
-- uncomment for using 2e modes:
-- WAIT_FOR_DS_2e,
-- ADDR_PHASE_1,
......@@ -812,26 +813,25 @@ constant c_STOP : integer := (to_integer("00" & c_FUNC7_ADER_0_addr(18 downto 2)
component VME_IRQ_Controller is
generic(
g_retry_timeout : integer range 1024 to 16777215);
port(
clk_i : in std_logic;
reset_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_AS1_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_LWORD_n_i : in std_logic;
VME_ADDR_123_i : in std_logic_vector(2 downto 0);
INT_Level_i : in std_logic_vector(7 downto 0);
INT_Vector_i : in std_logic_vector(7 downto 0);
VME_DS_n_i : in std_logic_vector (1 downto 0);
VME_ADDR_123_i : in std_logic_vector (2 downto 0);
INT_Level_i : in std_logic_vector (7 downto 0);
INT_Vector_i : in std_logic_vector (7 downto 0);
INT_Req_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic
);
end component VME_IRQ_Controller;
VME_DATA_o : out std_logic_vector (31 downto 0);
VME_DATA_DIR_o : out std_logic);
end component;
component VME_CRAM is
generic (dl : integer := 8;
......
hdl/syn/svec/svec-tdc-fmc.gise
View file @ c098769a
......@@ -103,7 +103,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1385128254" xil_pn:in_ck="5268971704634117961" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7543648610729664005" xil_pn:start_ts="1385128088">
<transform xil_pn:end_ts="1385649337" xil_pn:in_ck="5268971704634117961" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7543648610729664005" xil_pn:start_ts="1385649161">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -125,7 +125,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1385128269" xil_pn:in_ck="-3760130385703199631" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8504525175841796663" xil_pn:start_ts="1385128254">
<transform xil_pn:end_ts="1385649353" xil_pn:in_ck="-3760130385703199631" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8504525175841796663" xil_pn:start_ts="1385649337">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -135,7 +135,7 @@
<outfile xil_pn:name="top_tdc.ngd"/>
<outfile xil_pn:name="top_tdc_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1385128482" xil_pn:in_ck="-7440346353620165565" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7568465460566446564" xil_pn:start_ts="1385128269">
<transform xil_pn:end_ts="1385649562" xil_pn:in_ck="-7440346353620165565" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7568465460566446564" xil_pn:start_ts="1385649353">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -148,7 +148,7 @@
<outfile xil_pn:name="top_tdc_summary.xml"/>
<outfile xil_pn:name="top_tdc_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1385128706" xil_pn:in_ck="4998236143670007004" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-7978487711023391987" xil_pn:start_ts="1385128482">
<transform xil_pn:end_ts="1385649703" xil_pn:in_ck="4998236143670007004" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-7978487711023391987" xil_pn:start_ts="1385649562">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -163,7 +163,7 @@
<outfile xil_pn:name="top_tdc_pad.txt"/>
<outfile xil_pn:name="top_tdc_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1385128766" xil_pn:in_ck="182976557419624816" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5293564962942599218" xil_pn:start_ts="1385128706">
<transform xil_pn:end_ts="1385649768" xil_pn:in_ck="182976557419624816" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5293564962942599218" xil_pn:start_ts="1385649703">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -175,7 +175,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1385128706" xil_pn:in_ck="-7440346353620165697" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1385128683">
<transform xil_pn:end_ts="1385649703" xil_pn:in_ck="-7440346353620165697" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1385649681">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/syn/svec/top_tdc.bin
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hdl/syn/svec/top_tdc.twr
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hdl/syn/svec/top_tdc_summary.html
View file @ c098769a
......@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>top_tdc Project Status (11/22/2013 - 14:59:27)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>top_tdc Project Status (11/28/2013 - 15:42:49)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>svec-tdc-fmc.xise</TD>
......@@ -25,7 +25,7 @@ No Errors</TD>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/*.xmsgs?&DataKey=Warning'>3330 Warnings (3317 new)</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/*.xmsgs?&DataKey=Warning'>3325 Warnings (3303 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
......@@ -39,8 +39,7 @@ No Errors</TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>
<font color="red"; face="Arial"><b>X </b></font>
<A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.ptwx?&DataKey=ConstraintsData'>1 Failing Constraint</A></TD>
<A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
......@@ -49,7 +48,7 @@ No Errors</TD>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>7 &nbsp;<A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
<TD>0 &nbsp;<A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
</TR>
</TABLE>
......@@ -61,13 +60,13 @@ System Settings</A>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>6,532</TD>
<TD ALIGN=RIGHT>6,526</TD>
<TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>6,486</TD>
<TD ALIGN=RIGHT>6,480</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -91,31 +90,31 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>9,239</TD>
<TD ALIGN=RIGHT>9,248</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>10%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>8,951</TD>
<TD ALIGN=RIGHT>8,960</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>9%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>5,945</TD>
<TD ALIGN=RIGHT>5,957</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>387</TD>
<TD ALIGN=RIGHT>409</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>2,619</TD>
<TD ALIGN=RIGHT>2,594</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -175,13 +174,13 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
<TD ALIGN=RIGHT>177</TD>
<TD ALIGN=RIGHT>176</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD>
<TD ALIGN=RIGHT>74</TD>
<TD ALIGN=RIGHT>75</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -193,7 +192,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>3,678</TD>
<TD ALIGN=RIGHT>3,647</TD>
<TD ALIGN=RIGHT>23,038</TD>
<TD ALIGN=RIGHT>15%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -205,37 +204,37 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>10,525</TD>
<TD ALIGN=RIGHT>10,494</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>4,788</TD>
<TD ALIGN=RIGHT>10,525</TD>
<TD ALIGN=RIGHT>4,755</TD>
<TD ALIGN=RIGHT>10,494</TD>
<TD ALIGN=RIGHT>45%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>1,286</TD>
<TD ALIGN=RIGHT>10,525</TD>
<TD ALIGN=RIGHT>12%</TD>
<TD ALIGN=RIGHT>1,246</TD>
<TD ALIGN=RIGHT>10,494</TD>
<TD ALIGN=RIGHT>11%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>4,451</TD>
<TD ALIGN=RIGHT>10,525</TD>
<TD ALIGN=RIGHT>4,493</TD>
<TD ALIGN=RIGHT>10,494</TD>
<TD ALIGN=RIGHT>42%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
<TD ALIGN=RIGHT>207</TD>
<TD ALIGN=RIGHT>208</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>363</TD>
<TD ALIGN=RIGHT>369</TD>
<TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -446,7 +445,7 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>7 (Setup: 7, Hold: 0, Component Switching Limit: 0)</TD>
<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
......@@ -459,8 +458,7 @@ System Settings</A>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>
<font color="red"; face="Arial"><b>X </b></font>
<A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.ptwx?&DataKey=ConstraintsData'>1 Failing Constraint</A></TD>
<A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TABLE>
......@@ -471,21 +469,21 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Nov 22 14:50:53 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Warning'>3318 Warnings (3317 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Info'>135 Infos (135 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Nov 22 14:51:09 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Nov 22 14:54:42 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Info'>279 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Nov 22 14:58:03 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Warning'>7 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:35:36 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Warning'>3314 Warnings (3303 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Info'>131 Infos (131 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:35:53 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:39:22 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Info'>279 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:41:21 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Warning'>6 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri Nov 22 14:58:25 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Fri Nov 22 14:59:18 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/bitgen.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:41:43 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:42:40 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/bitgen.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri Nov 22 14:59:19 2013</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri Nov 22 14:59:26 2013</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Nov 28 15:42:40 2013</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Nov 28 15:42:48 2013</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 11/22/2013 - 14:59:27</center>
<br><center><b>Date Generated:</b> 11/28/2013 - 15:42:49</center>
</BODY></HTML>
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