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FMC TDC 1ns 5cha - Gateware
Commit c098769a authored by egousiou's avatar egousiou
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corrections on VME interrupts controller (was not working with multiple boards) 

git-svn-id: http://svn.ohwr.org/fmc-tdc@141 85dfdc96-de2c-444c-878d-45b388be74a9
parent 6103f3f1
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hdl/ip_cores/VMEcore/VME64xCore_Top.vhd
View file @ c098769a
......@@ -430,14 +430,15 @@ begin
--------------------------------------------------------------------------------
-- Interrupter
Inst_VME_IRQ_Controller : VME_IRQ_Controller
generic map (
g_retry_timeout => 62500 -- 1ms timeout
)
port map(
clk_i => clk_i,
reset_n_i => s_reset_IRQ, -- asserted when low
VME_IACKIN_n_i => VME_IACKIN_n_oversampled,
VME_AS_n_i => VME_AS_n_oversampled,
VME_AS1_n_i => VME_AS_n_i,
VME_DS_n_i => VME_DS_n_oversampled,
VME_LWORD_n_i => VME_LWORD_n_i,
VME_ADDR_123_i => VME_ADDR_i(3 downto 1),
INT_Level_i => s_INT_Level,
INT_Vector_i => s_INT_Vector ,
......
hdl/ip_cores/VMEcore/VME_IRQ_Controller.vhd
View file @ c098769a
This diff is collapsed.
hdl/ip_cores/VMEcore/vme64x_pack.vhd
View file @ c098769a
......@@ -361,6 +361,7 @@ constant c_STOP : integer := (to_integer("00" & c_FUNC7_ADER_0_addr(18 downto 2)
DECIDE_NEXT_CYCLE,
INCREMENT_ADDR,
SET_DATA_PHASE
-- UGLY_WAIT_TO_MAKE_DECODING_WORK
-- uncomment for using 2e modes:
-- WAIT_FOR_DS_2e,
-- ADDR_PHASE_1,
......@@ -812,26 +813,25 @@ constant c_STOP : integer := (to_integer("00" & c_FUNC7_ADER_0_addr(18 downto 2)
component VME_IRQ_Controller is
generic(
g_retry_timeout : integer range 1024 to 16777215);
port(
clk_i : in std_logic;
reset_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_AS1_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_LWORD_n_i : in std_logic;
VME_ADDR_123_i : in std_logic_vector(2 downto 0);
INT_Level_i : in std_logic_vector(7 downto 0);
INT_Vector_i : in std_logic_vector(7 downto 0);
VME_DS_n_i : in std_logic_vector (1 downto 0);
VME_ADDR_123_i : in std_logic_vector (2 downto 0);
INT_Level_i : in std_logic_vector (7 downto 0);
INT_Vector_i : in std_logic_vector (7 downto 0);
INT_Req_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic
);
end component VME_IRQ_Controller;
VME_DATA_o : out std_logic_vector (31 downto 0);
VME_DATA_DIR_o : out std_logic);
end component;
component VME_CRAM is
generic (dl : integer := 8;
......
hdl/syn/svec/svec-tdc-fmc.gise
View file @ c098769a
......@@ -103,7 +103,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1385128254" xil_pn:in_ck="5268971704634117961" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7543648610729664005" xil_pn:start_ts="1385128088">
<transform xil_pn:end_ts="1385649337" xil_pn:in_ck="5268971704634117961" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7543648610729664005" xil_pn:start_ts="1385649161">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -125,7 +125,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1385128269" xil_pn:in_ck="-3760130385703199631" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8504525175841796663" xil_pn:start_ts="1385128254">
<transform xil_pn:end_ts="1385649353" xil_pn:in_ck="-3760130385703199631" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8504525175841796663" xil_pn:start_ts="1385649337">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -135,7 +135,7 @@
<outfile xil_pn:name="top_tdc.ngd"/>
<outfile xil_pn:name="top_tdc_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1385128482" xil_pn:in_ck="-7440346353620165565" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7568465460566446564" xil_pn:start_ts="1385128269">
<transform xil_pn:end_ts="1385649562" xil_pn:in_ck="-7440346353620165565" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7568465460566446564" xil_pn:start_ts="1385649353">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -148,7 +148,7 @@
<outfile xil_pn:name="top_tdc_summary.xml"/>
<outfile xil_pn:name="top_tdc_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1385128706" xil_pn:in_ck="4998236143670007004" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-7978487711023391987" xil_pn:start_ts="1385128482">
<transform xil_pn:end_ts="1385649703" xil_pn:in_ck="4998236143670007004" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-7978487711023391987" xil_pn:start_ts="1385649562">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -163,7 +163,7 @@
<outfile xil_pn:name="top_tdc_pad.txt"/>
<outfile xil_pn:name="top_tdc_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1385128766" xil_pn:in_ck="182976557419624816" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5293564962942599218" xil_pn:start_ts="1385128706">
<transform xil_pn:end_ts="1385649768" xil_pn:in_ck="182976557419624816" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5293564962942599218" xil_pn:start_ts="1385649703">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -175,7 +175,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1385128706" xil_pn:in_ck="-7440346353620165697" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1385128683">
<transform xil_pn:end_ts="1385649703" xil_pn:in_ck="-7440346353620165697" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1385649681">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/syn/svec/top_tdc.bin
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hdl/syn/svec/top_tdc.twr
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hdl/syn/svec/top_tdc_summary.html
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