Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC TDC 1ns 5cha - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
1
Issues
1
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC TDC 1ns 5cha - Gateware
Commits
c2a10e64
Commit
c2a10e64
authored
Apr 29, 2015
by
Tomasz Wlostowski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
hdl: independent FIFO buffers per channel - top level verified on the SVEC
parent
8b800231
Show whitespace changes
Inline
Side-by-side
Showing
13 changed files
with
1904 additions
and
1904 deletions
+1904
-1904
data_formatting.vhd
hdl/rtl/data_formatting.vhd
+11
-4
fmc_tdc_core.vhd
hdl/rtl/fmc_tdc_core.vhd
+1
-1
fmc_tdc_mezzanine.vhd
hdl/rtl/fmc_tdc_mezzanine.vhd
+17
-18
tdc_core_pkg.vhd
hdl/rtl/tdc_core_pkg.vhd
+19
-18
tdc_eic.vhd
hdl/rtl/tdc_eic.vhd
+321
-321
timestamp_fifo.vhd
hdl/rtl/timestamp_fifo.vhd
+42
-13
timestamp_fifo_wb.vhd
hdl/rtl/timestamp_fifo_wb.vhd
+92
-217
timestamp_fifo_wbgen2_pkg.vhd
hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
+24
-13
tdc_eic.wb
hdl/rtl/wbgen/tdc_eic.wb
+28
-12
timestamp_fifo_wb.wb
hdl/rtl/wbgen/timestamp_fifo_wb.wb
+40
-7
wr_svec_tdc.xise
hdl/syn/svec/wr_svec_tdc.xise
+1151
-1140
main.sv
hdl/testbench/svec/main.sv
+21
-6
wave.do
hdl/testbench/svec/wave.do
+137
-134
No files found.
hdl/rtl/data_formatting.vhd
View file @
c2a10e64
...
...
@@ -137,7 +137,7 @@ architecture rtl of data_formatting is
signal
un_current_retrig_from_roll_over
:
unsigned
(
31
downto
0
);
signal
un_acam_fine_time
:
unsigned
(
31
downto
0
);
signal
previous_utc
:
std_logic_vector
(
31
downto
0
);
signal
timestamp_valid_int
:
std_logic
;
--=================================================================================================
-- architecture begin
...
...
@@ -149,9 +149,9 @@ begin
begin
if
rising_edge
(
clk_i
)
then
if
rst_i
=
'1'
then
timestamp_valid_
o
<=
'0'
;
timestamp_valid_
int
<=
'0'
;
else
timestamp_valid_
o
<=
acam_tstamp1_ok_p_i
or
acam_tstamp2_ok_p_i
;
timestamp_valid_
int
<=
acam_tstamp1_ok_p_i
or
acam_tstamp2_ok_p_i
;
end
if
;
end
if
;
end
process
;
...
...
@@ -333,9 +333,16 @@ begin
full_timestamp
(
63
downto
32
)
<=
coarse_time
;
full_timestamp
(
95
downto
64
)
<=
utc
;
full_timestamp
(
127
downto
96
)
<=
metadata
;
timestamp_o
<=
full_timestamp
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
timestamp_o
<=
full_timestamp
;
timestamp_valid_o
<=
timestamp_valid_int
;
end
if
;
end
process
;
end
rtl
;
----------------------------------------------------------------------------------------------------
-- architecture ends
...
...
hdl/rtl/fmc_tdc_core.vhd
View file @
c2a10e64
...
...
@@ -549,7 +549,7 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
---------------------------------------------------------------------------------------------------
start_dis_o
<=
'0'
;
channel_enable_o
<=
acam_inputs_en
(
4
downto
0
);
channel_enable_o
<=
acam_inputs_en
(
20
downto
16
);
end
rtl
;
----------------------------------------------------------------------------------------------------
...
...
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @
c2a10e64
...
...
@@ -416,9 +416,6 @@ begin
end
generate
gen_fifos
;
irq_tstamp
<=
'1'
when
unsigned
(
irq_channel
)
/=
0
else
'0'
;
p_gen_1ms_tick
:
process
(
clk_tdc_i
)
begin
if
rising_edge
(
clk_tdc_i
)
then
...
...
@@ -527,9 +524,11 @@ begin
wb_ack_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
ack
,
wb_stall_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
stall
,
wb_int_o
=>
wb_irq_o
,
irq_tdc_tstamps_i
=>
irq_tstamp
,
irq_tdc_time_i
=>
'0'
,
irq_tdc_acam_err_i
=>
'0'
);
irq_tdc_fifo1_i
=>
irq_channel
(
0
),
irq_tdc_fifo2_i
=>
irq_channel
(
1
),
irq_tdc_fifo3_i
=>
irq_channel
(
2
),
irq_tdc_fifo4_i
=>
irq_channel
(
3
),
irq_tdc_fifo5_i
=>
irq_channel
(
4
));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
...
...
hdl/rtl/tdc_core_pkg.vhd
View file @
c2a10e64
...
...
@@ -726,10 +726,9 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
component
tdc_eic
port
(
rst_n_i
:
in
std_logic
;
component
tdc_eic
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
...
...
@@ -741,9 +740,11 @@ package tdc_core_pkg is
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
irq_tdc_tstamps_i
:
in
std_logic
;
irq_tdc_time_i
:
in
std_logic
;
irq_tdc_acam_err_i
:
in
std_logic
);
irq_tdc_fifo1_i
:
in
std_logic
;
irq_tdc_fifo2_i
:
in
std_logic
;
irq_tdc_fifo3_i
:
in
std_logic
;
irq_tdc_fifo4_i
:
in
std_logic
;
irq_tdc_fifo5_i
:
in
std_logic
);
end
component
tdc_eic
;
...
...
hdl/rtl/tdc_eic.vhd
View file @
c2a10e64
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC EIC
---------------------------------------------------------------------------------------
-- File :
output.vhd
-- Author : auto-generated by wbgen2 from
tdc_eic.wb
-- Created :
01/21/14 15:13:26
-- File :
tdc_eic.vhd
-- Author : auto-generated by wbgen2 from
wbgen/tdc_eic.wb
-- Created :
Mon Apr 20 17:34:12 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE
tdc_eic.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE
wbgen/tdc_eic.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
...
...
@@ -29,24 +29,26 @@ entity tdc_eic is
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
irq_tdc_tstamps_i
:
in
std_logic
;
irq_tdc_time_i
:
in
std_logic
;
irq_tdc_acam_err_i
:
in
std_logic
irq_tdc_fifo1_i
:
in
std_logic
;
irq_tdc_fifo2_i
:
in
std_logic
;
irq_tdc_fifo3_i
:
in
std_logic
;
irq_tdc_fifo4_i
:
in
std_logic
;
irq_tdc_fifo5_i
:
in
std_logic
);
end
tdc_eic
;
architecture
syn
of
tdc_eic
is
signal
eic_idr_int
:
std_logic_vector
(
2
downto
0
);
signal
eic_idr_int
:
std_logic_vector
(
4
downto
0
);
signal
eic_idr_write_int
:
std_logic
;
signal
eic_ier_int
:
std_logic_vector
(
2
downto
0
);
signal
eic_ier_int
:
std_logic_vector
(
4
downto
0
);
signal
eic_ier_write_int
:
std_logic
;
signal
eic_imr_int
:
std_logic_vector
(
2
downto
0
);
signal
eic_isr_clear_int
:
std_logic_vector
(
2
downto
0
);
signal
eic_isr_status_int
:
std_logic_vector
(
2
downto
0
);
signal
eic_irq_ack_int
:
std_logic_vector
(
2
downto
0
);
signal
eic_imr_int
:
std_logic_vector
(
4
downto
0
);
signal
eic_isr_clear_int
:
std_logic_vector
(
4
downto
0
);
signal
eic_isr_status_int
:
std_logic_vector
(
4
downto
0
);
signal
eic_irq_ack_int
:
std_logic_vector
(
4
downto
0
);
signal
eic_isr_write_int
:
std_logic
;
signal
irq_inputs_vector_int
:
std_logic_vector
(
2
downto
0
);
signal
irq_inputs_vector_int
:
std_logic_vector
(
4
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -171,9 +173,7 @@ begin
when
"10"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
2
downto
0
)
<=
eic_imr_int
(
2
downto
0
);
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
4
downto
0
)
<=
eic_imr_int
(
4
downto
0
);
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
...
...
@@ -207,9 +207,7 @@ begin
if
(
wb_we_i
=
'1'
)
then
eic_isr_write_int
<=
'1'
;
end
if
;
rddata_reg
(
2
downto
0
)
<=
eic_isr_status_int
(
2
downto
0
);
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
4
downto
0
)
<=
eic_isr_status_int
(
4
downto
0
);
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
...
...
@@ -253,20 +251,20 @@ begin
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int
(
2
downto
0
)
<=
wrdata_reg
(
2
downto
0
);
eic_idr_int
(
4
downto
0
)
<=
wrdata_reg
(
4
downto
0
);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int
(
2
downto
0
)
<=
wrdata_reg
(
2
downto
0
);
eic_ier_int
(
4
downto
0
)
<=
wrdata_reg
(
4
downto
0
);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int
(
2
downto
0
)
<=
wrdata_reg
(
2
downto
0
);
eic_isr_clear_int
(
4
downto
0
)
<=
wrdata_reg
(
4
downto
0
);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst
:
wbgen2_eic
generic
map
(
g_num_interrupts
=>
3
,
g_irq00_mode
=>
0
,
g_irq01_mode
=>
0
,
g_irq02_mode
=>
0
,
g_irq03_mode
=>
0
,
g_irq04_mode
=>
0
,
g_num_interrupts
=>
5
,
g_irq00_mode
=>
3
,
g_irq01_mode
=>
3
,
g_irq02_mode
=>
3
,
g_irq03_mode
=>
3
,
g_irq04_mode
=>
3
,
g_irq05_mode
=>
0
,
g_irq06_mode
=>
0
,
g_irq07_mode
=>
0
,
...
...
@@ -311,9 +309,11 @@ begin
wb_irq_o
=>
wb_int_o
);
irq_inputs_vector_int
(
0
)
<=
irq_tdc_tstamps_i
;
irq_inputs_vector_int
(
1
)
<=
irq_tdc_time_i
;
irq_inputs_vector_int
(
2
)
<=
irq_tdc_acam_err_i
;
irq_inputs_vector_int
(
0
)
<=
irq_tdc_fifo1_i
;
irq_inputs_vector_int
(
1
)
<=
irq_tdc_fifo2_i
;
irq_inputs_vector_int
(
2
)
<=
irq_tdc_fifo3_i
;
irq_inputs_vector_int
(
3
)
<=
irq_tdc_fifo4_i
;
irq_inputs_vector_int
(
4
)
<=
irq_tdc_fifo5_i
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
...
...
hdl/rtl/timestamp_fifo.vhd
View file @
c2a10e64
...
...
@@ -85,8 +85,17 @@ architecture rtl of timestamp_fifo is
signal
channel_id
:
std_logic_vector
(
2
downto
0
);
signal
ts_match
:
std_logic
;
signal
seq_counter
:
unsigned
(
31
downto
0
);
signal
timestamp_with_seq
:
std_logic_vector
(
127
downto
0
);
begin
timestamp_with_seq
(
95
downto
0
)
<=
timestamp_i
(
95
downto
0
);
-- TS
timestamp_with_seq
(
98
downto
96
)
<=
timestamp_i
(
98
downto
96
);
-- channel
timestamp_with_seq
(
100
)
<=
timestamp_i
(
100
);
-- slope
timestamp_with_seq
(
127
downto
101
)
<=
std_logic_vector
(
seq_counter
(
26
downto
0
));
U_WB_Slave
:
timestamp_fifo_wb
port
map
(
rst_n_i
=>
rst_n_sys_i
,
...
...
@@ -114,6 +123,7 @@ begin
if
rst_tdc_i
=
'1'
then
regs_in
.
fifo_wr_req_i
<=
'0'
;
else
if
(
enable_i
=
'1'
and
regs_out
.
fifo_wr_full_o
=
'0'
and
ts_match
=
'1'
)
then
regs_in
.
fifo_wr_req_i
<=
'1'
;
else
...
...
@@ -123,24 +133,43 @@ begin
end
if
;
end
process
;
regs_in
.
fifo_ts0_i
<=
timestamp_with_seq
(
31
downto
0
);
regs_in
.
fifo_ts1_i
<=
timestamp_with_seq
(
63
downto
32
);
regs_in
.
fifo_ts2_i
<=
timestamp_with_seq
(
95
downto
64
);
regs_in
.
fifo_ts3_i
<=
timestamp_with_seq
(
127
downto
96
);
p_seq_counter
:
process
(
clk_tdc_i
)
begin
if
rising_edge
(
clk_tdc_i
)
then
if
rst_tdc_i
=
'1'
or
regs_out
.
csr_rst_seq_o
=
'1'
then
seq_counter
<=
(
others
=>
'0'
);
else
if
(
enable_i
=
'1'
and
ts_match
=
'1'
)
then
seq_counter
<=
seq_counter
+
1
;
end
if
;
end
if
;
end
if
;
end
process
;
p_latch_last_timestamp
:
process
(
clk_tdc_i
)
begin
if
rising_edge
(
clk_tdc_i
)
then
if
rst_tdc_i
=
'1'
then
regs_in
.
ltsctl
_valid_i
<=
'0'
;
regs_in
.
csr_last
_valid_i
<=
'0'
;
else
if
(
enable_i
=
'1'
and
ts_match
=
'1'
)
then
regs_in
.
ltsctl_valid_i
<=
'1'
;
last_ts
<=
timestamp_i
;
elsif
(
regs_out
.
ltsctl_valid_o
=
'0'
and
regs_out
.
ltsctl_valid_load_o
=
'1'
)
then
regs_in
.
ltsctl_valid_i
<=
'0'
;
-- latch only the last rising edge TS
if
(
enable_i
=
'1'
and
ts_match
=
'1'
and
timestamp_with_seq
(
100
)
=
'1'
)
then
regs_in
.
csr_last_valid_i
<=
'1'
;
last_ts
<=
timestamp_with_seq
;
elsif
(
regs_out
.
csr_last_valid_o
=
'0'
and
regs_out
.
csr_last_valid_load_o
=
'1'
)
then
regs_in
.
csr_last_valid_i
<=
'0'
;
end
if
;
if
(
regs_out
.
ltsctl_valid_o
=
'0'
and
regs_out
.
ltsctl
_valid_load_o
=
'1'
)
then
regs_in
.
lts0_i
<=
last_ts
(
127
downto
96
);
regs_in
.
lts1_i
<=
last_ts
(
95
downto
64
);
regs_in
.
lts2_i
<=
last_ts
(
63
downto
32
);
regs_in
.
lts3_i
<=
last_ts
(
31
downto
0
);
if
(
regs_out
.
csr_last_valid_o
=
'0'
and
regs_out
.
csr_last
_valid_load_o
=
'1'
)
then
regs_in
.
lts0_i
<=
last_ts
(
31
downto
0
);
regs_in
.
lts1_i
<=
last_ts
(
63
downto
32
);
regs_in
.
lts2_i
<=
last_ts
(
95
downto
64
);
regs_in
.
lts3_i
<=
last_ts
(
127
downto
96
);
end
if
;
end
if
;
end
if
;
...
...
@@ -152,7 +181,7 @@ begin
if
rst_tdc_i
=
'1'
or
enable_i
=
'0'
then
buf_irq_int
<=
'0'
;
else
if
(
buf_count
=
0
)
then
if
(
regs_out
.
fifo_wr_empty_o
=
'1'
)
then
buf_irq_int
<=
'0'
;
tmr_timeout
<=
(
others
=>
'0'
);
else
...
...
@@ -172,7 +201,7 @@ begin
-- Case 2: amount of data exceeded the threshold - assert the IRQ
-- line immediately.
if
(
buf_count
>
unsigned
(
irq_threshold_i
(
9
downto
0
)))
then
if
(
regs_out
.
fifo_wr_full_o
=
'1'
or
(
buf_count
>
unsigned
(
irq_threshold_i
(
9
downto
0
)
)))
then
buf_irq_int
<=
'1'
;
end
if
;
end
if
;
...
...
hdl/rtl/timestamp_fifo_wb.vhd
View file @
c2a10e64
...
...
@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for Timestamp FIFO
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wb.vhd
-- Author : auto-generated by wbgen2 from timestamp_fifo_wb.wb
-- Created :
Tue Apr 14 16:47:08
2015
-- Author : auto-generated by wbgen2 from
wbgen/
timestamp_fifo_wb.wb
-- Created :
Mon Apr 20 17:34:12
2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timestamp_fifo_wb.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE
wbgen/
timestamp_fifo_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
...
...
@@ -72,17 +72,23 @@ signal tsf_lts3_lwb_in_progress : std_logic ;
signal
tsf_lts3_lwb_s0
:
std_logic
;
signal
tsf_lts3_lwb_s1
:
std_logic
;
signal
tsf_lts3_lwb_s2
:
std_logic
;
signal
tsf_ltsctl_valid_int_read
:
std_logic
;
signal
tsf_ltsctl_valid_int_write
:
std_logic
;
signal
tsf_ltsctl_valid_lw
:
std_logic
;
signal
tsf_ltsctl_valid_lw_delay
:
std_logic
;
signal
tsf_ltsctl_valid_lw_read_in_progress
:
std_logic
;
signal
tsf_ltsctl_valid_lw_s0
:
std_logic
;
signal
tsf_ltsctl_valid_lw_s1
:
std_logic
;
signal
tsf_ltsctl_valid_lw_s2
:
std_logic
;
signal
tsf_ltsctl_valid_rwsel
:
std_logic
;
signal
tsf_csr_last_valid_int_read
:
std_logic
;
signal
tsf_csr_last_valid_int_write
:
std_logic
;
signal
tsf_csr_last_valid_lw
:
std_logic
;
signal
tsf_csr_last_valid_lw_delay
:
std_logic
;
signal
tsf_csr_last_valid_lw_read_in_progress
:
std_logic
;
signal
tsf_csr_last_valid_lw_s0
:
std_logic
;
signal
tsf_csr_last_valid_lw_s1
:
std_logic
;
signal
tsf_csr_last_valid_lw_s2
:
std_logic
;
signal
tsf_csr_last_valid_rwsel
:
std_logic
;
signal
tsf_csr_rst_seq_int
:
std_logic
;
signal
tsf_csr_rst_seq_int_delay
:
std_logic
;
signal
tsf_csr_rst_seq_sync0
:
std_logic
;
signal
tsf_csr_rst_seq_sync1
:
std_logic
;
signal
tsf_csr_rst_seq_sync2
:
std_logic
;
signal
tsf_fifo_full_int
:
std_logic
;
signal
tsf_fifo_empty_int
:
std_logic
;
signal
tsf_fifo_clear_bus_int
:
std_logic
;
signal
tsf_fifo_usedw_int
:
std_logic_vector
(
9
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -123,11 +129,14 @@ begin
tsf_lts3_lwb
<=
'0'
;
tsf_lts3_lwb_delay
<=
'0'
;
tsf_lts3_lwb_in_progress
<=
'0'
;
tsf_ltsctl_valid_lw
<=
'0'
;
tsf_ltsctl_valid_lw_delay
<=
'0'
;
tsf_ltsctl_valid_lw_read_in_progress
<=
'0'
;
tsf_ltsctl_valid_rwsel
<=
'0'
;
tsf_ltsctl_valid_int_write
<=
'0'
;
tsf_csr_last_valid_lw
<=
'0'
;
tsf_csr_last_valid_lw_delay
<=
'0'
;
tsf_csr_last_valid_lw_read_in_progress
<=
'0'
;
tsf_csr_last_valid_rwsel
<=
'0'
;
tsf_csr_last_valid_int_write
<=
'0'
;
tsf_csr_rst_seq_int
<=
'0'
;
tsf_csr_rst_seq_int_delay
<=
'0'
;
tsf_fifo_clear_bus_int
<=
'0'
;
tsf_fifo_rdreq_int
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
...
...
@@ -135,6 +144,7 @@ begin
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
tsf_fifo_clear_bus_int
<=
'0'
;
ack_in_progress
<=
'0'
;
else
tsf_lts0_lwb
<=
tsf_lts0_lwb_delay
;
...
...
@@ -161,12 +171,14 @@ begin
rddata_reg
(
31
downto
0
)
<=
tsf_lts3_int
;
tsf_lts3_lwb_in_progress
<=
'0'
;
end
if
;
tsf_
ltsctl_valid_lw
<=
tsf_ltsctl
_valid_lw_delay
;
tsf_
ltsctl
_valid_lw_delay
<=
'0'
;
if
((
ack_sreg
(
1
)
=
'1'
)
and
(
tsf_
ltsctl
_valid_lw_read_in_progress
=
'1'
))
then
rddata_reg
(
0
)
<=
tsf_
ltsctl
_valid_int_read
;
tsf_
ltsctl
_valid_lw_read_in_progress
<=
'0'
;
tsf_
csr_last_valid_lw
<=
tsf_csr_last
_valid_lw_delay
;
tsf_
csr_last
_valid_lw_delay
<=
'0'
;
if
((
ack_sreg
(
1
)
=
'1'
)
and
(
tsf_
csr_last
_valid_lw_read_in_progress
=
'1'
))
then
rddata_reg
(
0
)
<=
tsf_
csr_last
_valid_int_read
;
tsf_
csr_last
_valid_lw_read_in_progress
<=
'0'
;
end
if
;
tsf_csr_rst_seq_int
<=
tsf_csr_rst_seq_int_delay
;
tsf_csr_rst_seq_int_delay
<=
'0'
;
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
...
...
@@ -213,20 +225,22 @@ begin
ack_in_progress
<=
'1'
;
when
"0100"
=>
if
(
wb_we_i
=
'1'
)
then
tsf_ltsctl_valid_int_write
<=
wrdata_reg
(
0
);
tsf_ltsctl_valid_lw
<=
'1'
;
tsf_ltsctl_valid_lw_delay
<=
'1'
;
tsf_ltsctl_valid_lw_read_in_progress
<=
'0'
;
tsf_ltsctl_valid_rwsel
<=
'1'
;
tsf_csr_last_valid_int_write
<=
wrdata_reg
(
0
);
tsf_csr_last_valid_lw
<=
'1'
;
tsf_csr_last_valid_lw_delay
<=
'1'
;
tsf_csr_last_valid_lw_read_in_progress
<=
'0'
;
tsf_csr_last_valid_rwsel
<=
'1'
;
tsf_csr_rst_seq_int
<=
wrdata_reg
(
1
);
tsf_csr_rst_seq_int_delay
<=
wrdata_reg
(
1
);
end
if
;
if
(
wb_we_i
=
'0'
)
then
rddata_reg
(
0
)
<=
'X'
;
tsf_
ltsctl
_valid_lw
<=
'1'
;
tsf_
ltsctl
_valid_lw_delay
<=
'1'
;
tsf_
ltsctl
_valid_lw_read_in_progress
<=
'1'
;
tsf_
ltsctl
_valid_rwsel
<=
'0'
;
tsf_
csr_last
_valid_lw
<=
'1'
;
tsf_
csr_last
_valid_lw_delay
<=
'1'
;
tsf_
csr_last
_valid_lw_read_in_progress
<=
'1'
;
tsf_
csr_last
_valid_rwsel
<=
'0'
;
end
if
;
rddata_reg
(
1
)
<=
'
X
'
;
rddata_reg
(
1
)
<=
'
0
'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
...
...
@@ -265,194 +279,37 @@ begin
if
(
tsf_fifo_rdreq_int_d0
=
'0'
)
then
tsf_fifo_rdreq_int
<=
not
tsf_fifo_rdreq_int
;
else
rddata_reg
(
31
downto
0
)
<=
tsf_fifo_out_int
(
31
downto
0
);
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
when
"0110"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
31
downto
0
)
<=
tsf_fifo_out_int
(
63
downto
32
);
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0111"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
31
downto
0
)
<=
tsf_fifo_out_int
(
95
downto
64
);
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1000"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
31
downto
0
)
<=
tsf_fifo_out_int
(
127
downto
96
);
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1001"
=>
if
(
wb_we_i
=
'1'
)
then
if
(
wrdata_reg
(
18
)
=
'1'
)
then
tsf_fifo_clear_bus_int
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1010"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
16
)
<=
tsf_fifo_full_int
;
rddata_reg
(
17
)
<=
tsf_fifo_empty_int
;
rddata_reg
(
18
)
<=
'0'
;
rddata_reg
(
9
downto
0
)
<=
tsf_fifo_usedw_int
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
...
...
@@ -460,7 +317,6 @@ begin
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
...
...
@@ -490,8 +346,11 @@ begin
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
-- extra code for reg/fifo/mem: Timestamp FIFO
tsf_fifo_in_int
(
127
downto
0
)
<=
regs_i
.
fifo_value_i
;
tsf_fifo_rst_n
<=
rst_n_i
;
tsf_fifo_in_int
(
31
downto
0
)
<=
regs_i
.
fifo_ts0_i
;
tsf_fifo_in_int
(
63
downto
32
)
<=
regs_i
.
fifo_ts1_i
;
tsf_fifo_in_int
(
95
downto
64
)
<=
regs_i
.
fifo_ts2_i
;
tsf_fifo_in_int
(
127
downto
96
)
<=
regs_i
.
fifo_ts3_i
;
tsf_fifo_rst_n
<=
rst_n_i
and
(
not
tsf_fifo_clear_bus_int
);
tsf_fifo_INST
:
wbgen2_fifo_async
generic
map
(
g_size
=>
1024
,
...
...
@@ -599,27 +458,44 @@ begin
process
(
clk_tdc_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
tsf_
ltsctl
_valid_lw_s0
<=
'0'
;
tsf_
ltsctl
_valid_lw_s1
<=
'0'
;
tsf_
ltsctl
_valid_lw_s2
<=
'0'
;
tsf_
ltsctl
_valid_int_read
<=
'0'
;
regs_o
.
ltsctl
_valid_load_o
<=
'0'
;
regs_o
.
ltsctl
_valid_o
<=
'0'
;
tsf_
csr_last
_valid_lw_s0
<=
'0'
;
tsf_
csr_last
_valid_lw_s1
<=
'0'
;
tsf_
csr_last
_valid_lw_s2
<=
'0'
;
tsf_
csr_last
_valid_int_read
<=
'0'
;
regs_o
.
csr_last
_valid_load_o
<=
'0'
;
regs_o
.
csr_last
_valid_o
<=
'0'
;
elsif
rising_edge
(
clk_tdc_i
)
then
tsf_
ltsctl_valid_lw_s0
<=
tsf_ltsctl
_valid_lw
;
tsf_
ltsctl_valid_lw_s1
<=
tsf_ltsctl
_valid_lw_s0
;
tsf_
ltsctl_valid_lw_s2
<=
tsf_ltsctl
_valid_lw_s1
;
if
((
tsf_
ltsctl_valid_lw_s2
=
'0'
)
and
(
tsf_ltsctl
_valid_lw_s1
=
'1'
))
then
if
(
tsf_
ltsctl
_valid_rwsel
=
'1'
)
then
regs_o
.
ltsctl_valid_o
<=
tsf_ltsctl
_valid_int_write
;
regs_o
.
ltsctl
_valid_load_o
<=
'1'
;
tsf_
csr_last_valid_lw_s0
<=
tsf_csr_last
_valid_lw
;
tsf_
csr_last_valid_lw_s1
<=
tsf_csr_last
_valid_lw_s0
;
tsf_
csr_last_valid_lw_s2
<=
tsf_csr_last
_valid_lw_s1
;
if
((
tsf_
csr_last_valid_lw_s2
=
'0'
)
and
(
tsf_csr_last
_valid_lw_s1
=
'1'
))
then
if
(
tsf_
csr_last
_valid_rwsel
=
'1'
)
then
regs_o
.
csr_last_valid_o
<=
tsf_csr_last
_valid_int_write
;
regs_o
.
csr_last
_valid_load_o
<=
'1'
;
else
regs_o
.
ltsctl
_valid_load_o
<=
'0'
;
tsf_
ltsctl_valid_int_read
<=
regs_i
.
ltsctl
_valid_i
;
regs_o
.
csr_last
_valid_load_o
<=
'0'
;
tsf_
csr_last_valid_int_read
<=
regs_i
.
csr_last
_valid_i
;
end
if
;
else
regs_o
.
ltsctl_valid_load_o
<=
'0'
;
regs_o
.
csr_last_valid_load_o
<=
'0'
;
end
if
;
end
if
;
end
process
;
-- Reset Sequence Counter
process
(
clk_tdc_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
regs_o
.
csr_rst_seq_o
<=
'0'
;
tsf_csr_rst_seq_sync0
<=
'0'
;
tsf_csr_rst_seq_sync1
<=
'0'
;
tsf_csr_rst_seq_sync2
<=
'0'
;
elsif
rising_edge
(
clk_tdc_i
)
then
tsf_csr_rst_seq_sync0
<=
tsf_csr_rst_seq_int
;
tsf_csr_rst_seq_sync1
<=
tsf_csr_rst_seq_sync0
;
tsf_csr_rst_seq_sync2
<=
tsf_csr_rst_seq_sync1
;
regs_o
.
csr_rst_seq_o
<=
tsf_csr_rst_seq_sync2
and
(
not
tsf_csr_rst_seq_sync1
);
end
if
;
end
process
;
...
...
@@ -638,7 +514,6 @@ begin
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 3
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 4
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
...
...
hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
View file @
c2a10e64
...
...
@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for Timestamp FIFO
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from timestamp_fifo_wb.wb
-- Created :
Tue Apr 14 16:47:08
2015
-- Author : auto-generated by wbgen2 from
wbgen/
timestamp_fifo_wb.wb
-- Created :
Mon Apr 20 17:34:12
2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timestamp_fifo_wb.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE
wbgen/
timestamp_fifo_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
...
...
@@ -22,22 +22,28 @@ package tsf_wbgen2_pkg is
type
t_tsf_in_registers
is
record
fifo_wr_req_i
:
std_logic
;
fifo_value_i
:
std_logic_vector
(
127
downto
0
);
fifo_ts0_i
:
std_logic_vector
(
31
downto
0
);
fifo_ts1_i
:
std_logic_vector
(
31
downto
0
);
fifo_ts2_i
:
std_logic_vector
(
31
downto
0
);
fifo_ts3_i
:
std_logic_vector
(
31
downto
0
);
lts0_i
:
std_logic_vector
(
31
downto
0
);
lts1_i
:
std_logic_vector
(
31
downto
0
);
lts2_i
:
std_logic_vector
(
31
downto
0
);
lts3_i
:
std_logic_vector
(
31
downto
0
);
ltsctl_valid_i
:
std_logic
;
csr_last_valid_i
:
std_logic
;
end
record
;
constant
c_tsf_in_registers_init_value
:
t_tsf_in_registers
:
=
(
fifo_wr_req_i
=>
'0'
,
fifo_value_i
=>
(
others
=>
'0'
),
fifo_ts0_i
=>
(
others
=>
'0'
),
fifo_ts1_i
=>
(
others
=>
'0'
),
fifo_ts2_i
=>
(
others
=>
'0'
),
fifo_ts3_i
=>
(
others
=>
'0'
),
lts0_i
=>
(
others
=>
'0'
),
lts1_i
=>
(
others
=>
'0'
),
lts2_i
=>
(
others
=>
'0'
),
lts3_i
=>
(
others
=>
'0'
),
ltsctl
_valid_i
=>
'0'
csr_last
_valid_i
=>
'0'
);
-- Output registers (WB slave -> user design)
...
...
@@ -46,16 +52,18 @@ package tsf_wbgen2_pkg is
fifo_wr_full_o
:
std_logic
;
fifo_wr_empty_o
:
std_logic
;
fifo_wr_usedw_o
:
std_logic_vector
(
9
downto
0
);
ltsctl_valid_o
:
std_logic
;
ltsctl_valid_load_o
:
std_logic
;
csr_last_valid_o
:
std_logic
;
csr_last_valid_load_o
:
std_logic
;
csr_rst_seq_o
:
std_logic
;
end
record
;
constant
c_tsf_out_registers_init_value
:
t_tsf_out_registers
:
=
(
fifo_wr_full_o
=>
'0'
,
fifo_wr_empty_o
=>
'0'
,
fifo_wr_usedw_o
=>
(
others
=>
'0'
),
ltsctl_valid_o
=>
'0'
,
ltsctl_valid_load_o
=>
'0'
csr_last_valid_o
=>
'0'
,
csr_last_valid_load_o
=>
'0'
,
csr_rst_seq_o
=>
'0'
);
function
"or"
(
left
,
right
:
t_tsf_in_registers
)
return
t_tsf_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
...
...
@@ -87,12 +95,15 @@ function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers is
variable
tmp
:
t_tsf_in_registers
;
begin
tmp
.
fifo_wr_req_i
:
=
f_x_to_zero
(
left
.
fifo_wr_req_i
)
or
f_x_to_zero
(
right
.
fifo_wr_req_i
);
tmp
.
fifo_value_i
:
=
f_x_to_zero
(
left
.
fifo_value_i
)
or
f_x_to_zero
(
right
.
fifo_value_i
);
tmp
.
fifo_ts0_i
:
=
f_x_to_zero
(
left
.
fifo_ts0_i
)
or
f_x_to_zero
(
right
.
fifo_ts0_i
);
tmp
.
fifo_ts1_i
:
=
f_x_to_zero
(
left
.
fifo_ts1_i
)
or
f_x_to_zero
(
right
.
fifo_ts1_i
);
tmp
.
fifo_ts2_i
:
=
f_x_to_zero
(
left
.
fifo_ts2_i
)
or
f_x_to_zero
(
right
.
fifo_ts2_i
);
tmp
.
fifo_ts3_i
:
=
f_x_to_zero
(
left
.
fifo_ts3_i
)
or
f_x_to_zero
(
right
.
fifo_ts3_i
);
tmp
.
lts0_i
:
=
f_x_to_zero
(
left
.
lts0_i
)
or
f_x_to_zero
(
right
.
lts0_i
);
tmp
.
lts1_i
:
=
f_x_to_zero
(
left
.
lts1_i
)
or
f_x_to_zero
(
right
.
lts1_i
);
tmp
.
lts2_i
:
=
f_x_to_zero
(
left
.
lts2_i
)
or
f_x_to_zero
(
right
.
lts2_i
);
tmp
.
lts3_i
:
=
f_x_to_zero
(
left
.
lts3_i
)
or
f_x_to_zero
(
right
.
lts3_i
);
tmp
.
ltsctl_valid_i
:
=
f_x_to_zero
(
left
.
ltsctl_valid_i
)
or
f_x_to_zero
(
right
.
ltsctl
_valid_i
);
tmp
.
csr_last_valid_i
:
=
f_x_to_zero
(
left
.
csr_last_valid_i
)
or
f_x_to_zero
(
right
.
csr_last
_valid_i
);
return
tmp
;
end
function
;
end
package
body
;
hdl/rtl/wbgen/tdc_eic.wb
View file @
c2a10e64
...
...
@@ -6,24 +6,40 @@ peripheral {
irq {
name = "FMC TDC timestamps interrupt
";
description = "FMC TDC
timestamp interrupt (rising edge sensitive)
.";
prefix = "tdc_
tstamps
";
trigger =
EDGE_RISING
;
name = "FMC TDC timestamps interrupt (FIFO1)
";
description = "FMC TDC
FIFO1 not empty
.";
prefix = "tdc_
fifo1
";
trigger =
LEVEL_1
;
};
irq {
name = "FMC TDC time
interrupt
";
description = "FMC TDC
time interrupt (rising edge sensitive)
.";
prefix = "tdc_
time
";
trigger =
EDGE_RISING
;
name = "FMC TDC time
stamps interrupt (FIFO2)
";
description = "FMC TDC
FIFO1 not empty
.";
prefix = "tdc_
fifo2
";
trigger =
LEVEL_1
;
};
irq {
name = "FMC TDC
acam error interrupt
";
description = "FMC
slot 1 acam error interrupt (rising edge sensitive)
.";
prefix = "tdc_
acam_err
";
trigger =
EDGE_RISING
;
name = "FMC TDC
timestamps interrupt (FIFO3)
";
description = "FMC
TDC FIFO3 not empty
.";
prefix = "tdc_
fifo3
";
trigger =
LEVEL_1
;
};
irq {
name = "FMC TDC timestamps interrupt (FIFO4)";
description = "FMC TDC FIFO4 not empty.";
prefix = "tdc_fifo4";
trigger = LEVEL_1;
};
irq {
name = "FMC TDC timestamps interrupt (FIFO5)";
description = "FMC TDC FIFO5 not empty.";
prefix = "tdc_fifo5";
trigger = LEVEL_1;
};
};
hdl/rtl/timestamp_fifo_wb.wb
→
hdl/rtl/
wbgen/
timestamp_fifo_wb.wb
View file @
c2a10e64
...
...
@@ -15,14 +15,35 @@ peripheral {
name = "Timestamp FIFO";
clock = "clk_tdc_i";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT
, FIFO_CLEAR
};
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
field {
name = "The timestamp";
prefix = "
value
";
name = "The timestamp
(word 0)
";
prefix = "
ts0
";
type = SLV;
size = 128;
size = 32;
};
field {
name = "The timestamp (word 1)";
prefix = "ts1";
type = SLV;
size = 32;
};
field {
name = "The timestamp (word 2)";
prefix = "ts2";
type = SLV;
size = 32;
};
field {
name = "The timestamp (word 4)";
prefix = "ts3";
type = SLV;
size = 32;
};
};
...
...
@@ -84,19 +105,31 @@ peripheral {
};
};
reg {
name = "
Last Timestamp
Control/Status";
prefix = "
LTSCTL
";
name = "Control/Status";
prefix = "
CSR
";
field {
name = "Last Timestamp Valid";
clock = "clk_tdc_i";
prefix = "VALID";
prefix = "
LAST_
VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Reset Sequence Counter";
clock = "clk_tdc_i";
prefix = "RST_SEQ";
type = MONOSTABLE;
};
};
};
hdl/syn/svec/wr_svec_tdc.xise
View file @
c2a10e64
<?xml version="1.0" ?>
<?xml version="1.0"
encoding="UTF-8" standalone="no"
?>
<project
xmlns=
"http://www.xilinx.com/XMLSchema"
xmlns:xil_pn=
"http://www.xilinx.com/XMLSchema"
>
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
...
...
@@ -9,7 +10,8 @@
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
...
...
@@ -20,7 +22,8 @@
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v"
xil_pn:type=
"FILE_VERILOG"
/>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v"
xil_pn:type=
"FILE_VERILOG"
/>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v"
xil_pn:type=
"FILE_VERILOG"
/>
</autoManagedFiles>
</autoManagedFiles>
<properties>
<property
xil_pn:name=
"AES Initial Vector spartan6"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"AES Key (Hex String) spartan6"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
...
...
@@ -40,7 +43,7 @@
<property
xil_pn:name=
"BRAM Utilization Ratio"
xil_pn:value=
"100"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Bring Out Global Set/Reset Net as a Port"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Bring Out Global Tristate Net as a Port"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Bus Delimiter"
xil_pn:value=
"<>
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Bus Delimiter"
xil_pn:value=
"<>
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Case"
xil_pn:value=
"Maintain"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Case Implementation Style"
xil_pn:value=
"None"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Change Device Speed To"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
...
...
@@ -328,6 +331,9 @@
<property
xil_pn:name=
"Watchdog Timer Value spartan6"
xil_pn:value=
"0xFFFF"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Working Directory"
xil_pn:value=
"."
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Write Timing Constraints"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property
xil_pn:name=
"PROP_BehavioralSimTop"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_DesignName"
xil_pn:value=
"spec_top_fmc_tdc"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_DevFamilyPMName"
xil_pn:value=
"spartan6"
xil_pn:valueState=
"default"
/>
...
...
@@ -341,802 +347,807 @@
<property
xil_pn:name=
"PROP_intWbtProjectID"
xil_pn:value=
"7FBE502A282B40C7A2410990D68F770C"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intWorkingDirLocWRTProjDir"
xil_pn:value=
"Same"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intWorkingDirUsed"
xil_pn:value=
"No"
xil_pn:valueState=
"non-default"
/>
</properties>
</properties>
<libraries/>
<files>
<file
xil_pn:name=
"../../top/svec/wr_svec_tdc.ucf"
xil_pn:type=
"FILE_UCF"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"19
"
/>
</file>
<file
xil_pn:name=
"../../rtl/tdc_core_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
5"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
5"
/>
</file>
<file
xil_pn:name=
"../../rtl/acam_databus_interface.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
6"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
6"
/>
</file>
<file
xil_pn:name=
"../../rtl/carrier_info.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"159
"
/>
</file>
<file
xil_pn:name=
"../../rtl/clks_rsts_manager.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"149
"
/>
</file>
<file
xil_pn:name=
"../../rtl/data_engine.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"104
"
/>
</file>
<file
xil_pn:name=
"../../rtl/data_formatting.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"103
"
/>
</file>
<file
xil_pn:name=
"../../rtl/decr_counter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"68
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"12
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"164
"
/>
</file>
<file
xil_pn:name=
"../../rtl/fmc_tdc_mezzanine.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"13
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"147
"
/>
</file>
<file
xil_pn:name=
"../../rtl/free_counter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"14
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"67
"
/>
</file>
<file
xil_pn:name=
"../../rtl/incr_counter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"15
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"66
"
/>
</file>
<file
xil_pn:name=
"../../rtl/leds_manager.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"16
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"101
"
/>
</file>
<file
xil_pn:name=
"../../rtl/local_pps_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"17
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"100
"
/>
</file>
<file
xil_pn:name=
"../../rtl/reg_ctrl.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"18
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"99
"
/>
</file>
<file
xil_pn:name=
"../../rtl/start_retrig_ctrl.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"19
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"98
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"20
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
"
/>
</file>
<file
xil_pn:name=
"../../rtl/wrabbit_sync.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"21
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"127
"
/>
</file>
<file
xil_pn:name=
"../../rtl/fmc_tdc_direct_readout_slave_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
2"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
2"
/>
</file>
<file
xil_pn:name=
"../../rtl/fmc_tdc_direct_readout_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"23
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"130
"
/>
</file>
<file
xil_pn:name=
"../../rtl/fmc_tdc_direct_readout.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"24
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"148
"
/>
</file>
<file
xil_pn:name=
"../../rtl/fmc_tdc_wrapper.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"25
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"158
"
/>
</file>
<file
xil_pn:name=
"../../rtl/timestamp_fifo_wbgen2_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"26
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"64
"
/>
</file>
<file
xil_pn:name=
"../../rtl/timestamp_fifo_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
7"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
7"
/>
</file>
<file
xil_pn:name=
"../../rtl/timestamp_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
28"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
28"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
9"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
9"
/>
</file>
<file
xil_pn:name=
"../../top/svec/synthesis_descriptor.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"30
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"157
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"31
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"118
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"32
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"165
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"33
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"120
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
4"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
4"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"35
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"140
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"36
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"117
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"37
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"155
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"38
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"139
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
9"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
9"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"40
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"83
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"41
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"116
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"42
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"138
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"43
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"115
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
4"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
4"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"45
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"113
"
/>
</file>
<file
xil_pn:name=
"../../rtl/acam_timecontrol_interface.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"46
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"105
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
7"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
7"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_moving_average.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"48
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"49
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"26
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
0"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"51
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_reset.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"52
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"53
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"54
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"55
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"56
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"25
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"57
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"58
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"59
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
0"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_word_packer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"61
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"62
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"63
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"64
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_big_adder.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"65
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"66
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
67"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
67"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_sync_register.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"68
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"69
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"70
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"71
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"63
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"72
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"13
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"73
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"14
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"74
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"71
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"75
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"76
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"77
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"78
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"62
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"79
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"80
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"22
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"81
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"24
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"82
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"23
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"83
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"84
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"85"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"86"
/>
</file>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"122"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"87
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"55
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"88
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"21
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"89
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"58
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"90
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"94
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"91
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"124
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"92
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"144
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"93
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"94
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"145
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram_mixed.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"95
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"96
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"97
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"98
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"99
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"100
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"52
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
1"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"102
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"50
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"103
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"20
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"104
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"53
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
5"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
5"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"106
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"121
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"107
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"142
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"108
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"141
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"109
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"156
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"110
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"166
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"111
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"112
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"113
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"114
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"115
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
6"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"12
6"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"117
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"125
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"118
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"146
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"119
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"12
0"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"121
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"122
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"123
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"124
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"125
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"126
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"143
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"127
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"123
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"128
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"129
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"92
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"130
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"91
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"131
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"56
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"132
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"90
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"133
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"89
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"134
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"88
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"135
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"87
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"136
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"93
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"13
7"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
7"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"138
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"54
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"139
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"95
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"14
0"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"141
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"142
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"143
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"144
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"145
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"146
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"147
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"148
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"149
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"61
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"15
0"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"151
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"96
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"152
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"59
"
/>
</file>
<file
xil_pn:name=
"../../rtl/tdc_eic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"153
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"129
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"154
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"155
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"156
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"157
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"158
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"159
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"16
0"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"161
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"162
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"47
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"163
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"164
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"165
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"137
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"166
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"167
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"168
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"169
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"153
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"170
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"82
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"171
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"48
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"172
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"173
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"174
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"175
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"176
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"177
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"29
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"178
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"73
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"17
9"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
9"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"180
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"134
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"181
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"182
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"70
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"183
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"28
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"184
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"80
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"185
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"132
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"186
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"107
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"187
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"69
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"188
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"189
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"12
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"19
0"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"19
1"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"192
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"37
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"193
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"46
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"194
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"43
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"195
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"79
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"196
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"18
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"19
7"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
7"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"198
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"77
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"199
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"33
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"200
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"38
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"201
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"39
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"202
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"45
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_framer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"203
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"75
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"20
4"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
4"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"205
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"34
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"206
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"32
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"207
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"35
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"208
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"76
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"209
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"78
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"210
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"42
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"21
1"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"212
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"16
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"213
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"15
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"21
4"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
4"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"215
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"36
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"216
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"40
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"217
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"112
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"218
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"110
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"219
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"135
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"220
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"72
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"221
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"108
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"222
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"133
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"223
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"224
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"162
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"225
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"226
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"227
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"228
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"229
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"23
0"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"231
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca_gpio_channel.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"232
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"233
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"234
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"235
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"236
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca_flags.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"237
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca_queue_channel.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"238
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"239
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca_wb_channel.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"24
0"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"241
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"242
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"243
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"244
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"245
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"246
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"247
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"160
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"248
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"154
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"249
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../rtl/fmc_tdc_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"250
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"131
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"251
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"136
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"252
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"253
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"81
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"254
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"163
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"255
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"111
"
/>
</file>
<file
xil_pn:name=
"../../top/svec/wr_svec_tdc.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"256
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"168
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"257
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"152
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"258
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"151
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"259
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"26
0"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"261
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"262
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"150
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"263
"
/>
</file>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"161
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"264"
/>
</file>
</files>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
</files>
<bindings/>
<version
xil_pn:ise_version=
"14.7"
xil_pn:schema_version=
"2"
/>
</project>
hdl/testbench/svec/main.sv
View file @
c2a10e64
...
...
@@ -51,12 +51,12 @@ module fake_acam(
if
(
addr
==
8
)
begin
acam_fifo_entry
ent
;
ent
=
fifo1
.
pop_front
()
;
data
<=
ent
.
ts
|
(
ent
.
channel
<<
26
)
;
data
<=
ent
.
ts
|
(
ent
.
channel
<<
26
)
|
(
1
<<
17
)
;
end
else
if
(
addr
==
9
)
begin
acam_fifo_entry
ent
;
ent
=
fifo2
.
pop_front
()
;
data
<=
ent
.
ts
|
(
ent
.
channel
<<
26
)
;
data
<=
ent
.
ts
|
(
ent
.
channel
<<
26
)
|
(
1
<<
17
)
;
end
else
data
<=
28'bz
;
...
...
@@ -218,7 +218,7 @@ module main;
acc
.
write
(
'hc13004
,
'hf
)
;
// enable EIC irq
acc
.
write
(
'hc12084
,
'h1f
)
;
// enable all ACAM inputs
acc
.
write
(
'hc12084
,
'h1f
0000
)
;
// enable all ACAM inputs
acc
.
write
(
'hc120fc
,
(
1
<<
0
))
;
// start acquisition
acc
.
write
(
'hc120fc
,
(
1
<<
0
))
;
// start acquisition
...
...
@@ -230,11 +230,11 @@ module main;
#
300u
s
;
fork
forever
begin
acc
.
read
(
'hc15000
+
`ADDR_TSF_
LTSCTL
,
d
)
;
acc
.
read
(
'hc15000
+
`ADDR_TSF_
CSR
,
d
)
;
if
(
d
&
1
)
begin
uint64_t
t0
,
t1
,
t2
,
t3
;
acc
.
write
(
'hc15000
+
`ADDR_TSF_
LTSCTL
,
0
)
;
acc
.
write
(
'hc15000
+
`ADDR_TSF_
CSR
,
0
)
;
acc
.
read
(
'hc15000
+
`ADDR_TSF_LTS0
,
t0
)
;
acc
.
read
(
'hc15000
+
`ADDR_TSF_LTS1
,
t1
)
;
acc
.
read
(
'hc15000
+
`ADDR_TSF_LTS2
,
t2
)
;
...
...
@@ -245,6 +245,21 @@ module main;
end
acc
.
read
(
'hc15000
+
`ADDR_TSF_FIFO_CSR
,
d
)
;
// $display("FIFO CSR %x", d);
/* -----\/----- EXCLUDED -----\/-----
if(!(d&`TSF_FIFO_CSR_EMPTY)) begin
uint64_t t0,t1,t2,t3;
acc.read('hc15000 + `ADDR_TSF_FIFO_R0, t0);
acc.read('hc15000 + `ADDR_TSF_FIFO_R1, t1);
acc.read('hc15000 + `ADDR_TSF_FIFO_R2, t2);
acc.read('hc15000 + `ADDR_TSF_FIFO_R3, t3);
$display("Fifo: %08x %08x %08x %08x",t0,t1,t2,t3);
end
-----/\----- EXCLUDED -----/\----- */
end
...
...
hdl/testbench/svec/wave.do
View file @
c2a10e64
...
...
@@ -103,140 +103,143 @@ add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/i
add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/irq_timeout
add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tick_1ms
add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/counter_1ms
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_sys_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_tdc_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_n_sys_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_tdc_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_o
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_o
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/enable_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tick_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_threshold_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_timeout_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_valid_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tmr_timeout
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_irq_int
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_count
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/last_ts
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_in
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_out
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/channel_id
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_sys_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_n_sys_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_tdc_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_tdc_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_refclk_r_edge_p_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/send_dac_word_p_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/dac_word_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/err_flag_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/int_flag_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_dis_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/stop_dis_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_bus_io
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/address_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cs_n_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/oe_n_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rd_n_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wr_n_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef1_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef2_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/enable_inputs_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_1_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_2_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_3_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_4_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_5_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_status_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig1_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig2_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig3_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig4_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig5_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_status_reg_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_synched_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_p_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_stb_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/channel_enable_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_threshold_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_timeout_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_adr
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_cyc
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_stb
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_we
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_ack
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_r
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_w
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1_meta
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2_meta
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_f_edge_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_r_edge_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_intflag_f_edge_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1_ok_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2_ok_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/activate_acq_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_acq_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_acam_config
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_config
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_status
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo1
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo2
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_start01
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reset_acam
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_utc
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_incr_recent
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_chan
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/pulse_delay
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/window_delay
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_period
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/starting_utc
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_inputs_en
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo1
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo2
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_start01
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_tstamp_threshold
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_time_threshold
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config_rdbk
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/state_active_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_i_cycles_offset
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_nb
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/retrig_nb_offset
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/current_retrig_nb
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_channel
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp_channel
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_sys
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_valid
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_sys_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_n_sys_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_tdc_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_tdc_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_refclk_r_edge_p_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/send_dac_word_p_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/dac_word_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/err_flag_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/int_flag_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_dis_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/stop_dis_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_bus_io
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/address_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cs_n_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/oe_n_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rd_n_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wr_n_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef1_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef2_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/enable_inputs_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_1_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_2_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_3_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_4_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_5_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_status_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig1_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig2_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig3_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig4_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig5_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_status_reg_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_synched_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_p_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_stb_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/channel_enable_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_threshold_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_timeout_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_adr
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_cyc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_stb
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_we
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_ack
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_r
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_w
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1_meta
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2_meta
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_f_edge_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_r_edge_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_intflag_f_edge_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1_ok_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2_ok_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/activate_acq_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_acq_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_acam_config
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_config
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_status
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_start01
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reset_acam
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_incr_recent
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_chan
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/pulse_delay
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/window_delay
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_period
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/starting_utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_inputs_en
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_start01
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_tstamp_threshold
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_time_threshold
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config_rdbk
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/state_active_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_i_cycles_offset
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_nb
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/retrig_nb_offset
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/current_retrig_nb
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_channel
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp_channel
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_sys
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_valid
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_sys_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_tdc_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_n_sys_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_tdc_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_o
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_o
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/enable_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tick_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_threshold_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_timeout_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_valid_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tmr_timeout
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_irq_int
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_count
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/last_ts
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_in
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_out
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/channel_id
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/ts_match
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/seq_counter
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_with_seq
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {9
36185162
ps} 0}
WaveRestoreCursors {{Cursor 1} {9
71916383
ps} 0}
configure wave -namecolwidth 177
configure wave -valuecolwidth 100
configure wave -justifyvalue left
...
...
@@ -251,4 +254,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {
890208852 ps} {1005778482
ps}
WaveRestoreZoom {
969414062 ps} {973025614
ps}
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment