Skip to content

F
FMC TDC 1ns 5cha - Gateware
Commit d463d198 authored by egousiou's avatar egousiou
Browse files
Options

spec no dma (still needs some cleaning) 

git-svn-id: http://svn.ohwr.org/fmc-tdc@148 85dfdc96-de2c-444c-878d-45b388be74a9
parent 745fe32b
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 552 additions and 250 deletions
hdl/rtl/acam_databus_interface.vhd
View file @ d463d198
This diff is collapsed.
hdl/rtl/acam_timecontrol_interface.vhd
View file @ d463d198
......@@ -73,7 +73,7 @@ entity acam_timecontrol_interface is
int_flag_i : in std_logic; -- ACAM interrupt flag, active HIGH; through ACAM config
-- reg 12 it is set to the MSB of Start#
-- Signals from the reg_ctrl unit
activate_acq_p_i : in std_logic; -- signal from PCIe/VME to start following the ACAM chip
activate_acq_p_i : in std_logic; -- signal from GN4124/VME to start following the ACAM chip
-- for tstamps aquisition
window_delay_i : in std_logic_vector(31 downto 0); -- eva: not needed
......@@ -142,7 +142,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Input Synchronizers --
-- start_from_fpga_o generation --
---------------------------------------------------------------------------------------------------
-- Generation of the start pulse and the enable window:
-- the start pulse originates from an internal signal at the same time, the StartDis is de-asserted.
......@@ -232,7 +232,7 @@ begin
end process;
inputs_synchronizer: process (clk_i)
start_trig_pulse: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i ='1' then
......
hdl/rtl/carrier_info.vhd 0 → 100644
View file @ d463d198
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Misc Info about Carrier
---------------------------------------------------------------------------------------
-- File : carrier_info.vhd
-- Author : auto-generated by wbgen2 from carrier_info.wb
-- Created : 01/22/14 15:17:10
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_info.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity carrier_info is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
carrier_info_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
carrier_info_carrier_reserved_i : in std_logic_vector(11 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_info_carrier_type_i : in std_logic_vector(15 downto 0);
-- Port for BIT field: 'FMC presence' in reg: 'Status'
carrier_info_stat_fmc_pres_i : in std_logic;
-- Port for BIT field: 'GN4142 core P2L PLL status' in reg: 'Status'
carrier_info_stat_p2l_pll_lck_i : in std_logic;
-- Port for BIT field: 'System clock PLL status' in reg: 'Status'
carrier_info_stat_sys_pll_lck_i : in std_logic;
-- Port for BIT field: 'DDR3 calibration status' in reg: 'Status'
carrier_info_stat_ddr3_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status'
carrier_info_stat_reserved_i : in std_logic_vector(27 downto 0);
-- Port for BIT field: 'Green LED' in reg: 'Control'
carrier_info_ctrl_led_green_o : out std_logic;
-- Port for BIT field: 'Red LED' in reg: 'Control'
carrier_info_ctrl_led_red_o : out std_logic;
-- Port for BIT field: 'DAC clear' in reg: 'Control'
carrier_info_ctrl_dac_clr_n_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_info_ctrl_reserved_o : out std_logic_vector(28 downto 0);
-- Ports for BIT field: 'State of the reset line' in reg: 'Reset Register'
carrier_info_rst_fmc0_n_o : out std_logic;
carrier_info_rst_fmc0_n_i : in std_logic;
carrier_info_rst_fmc0_n_load_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register'
carrier_info_rst_reserved_o : out std_logic_vector(30 downto 0)
);
end carrier_info;
architecture syn of carrier_info is
signal carrier_info_ctrl_led_green_int : std_logic ;
signal carrier_info_ctrl_led_red_int : std_logic ;
signal carrier_info_ctrl_dac_clr_n_int : std_logic ;
signal carrier_info_ctrl_reserved_int : std_logic_vector(28 downto 0);
signal carrier_info_rst_reserved_int : std_logic_vector(30 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_info_ctrl_led_green_int <= '0';
carrier_info_ctrl_led_red_int <= '0';
carrier_info_ctrl_dac_clr_n_int <= '0';
carrier_info_ctrl_reserved_int <= "00000000000000000000000000000";
carrier_info_rst_fmc0_n_load_o <= '0';
carrier_info_rst_reserved_int <= "0000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
carrier_info_rst_fmc0_n_load_o <= '0';
ack_in_progress <= '0';
else
carrier_info_rst_fmc0_n_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= carrier_info_carrier_pcb_rev_i;
rddata_reg(15 downto 4) <= carrier_info_carrier_reserved_i;
rddata_reg(31 downto 16) <= carrier_info_carrier_type_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= carrier_info_stat_fmc_pres_i;
rddata_reg(1) <= carrier_info_stat_p2l_pll_lck_i;
rddata_reg(2) <= carrier_info_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_info_stat_ddr3_cal_done_i;
rddata_reg(31 downto 4) <= carrier_info_stat_reserved_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
carrier_info_ctrl_led_green_int <= wrdata_reg(0);
carrier_info_ctrl_led_red_int <= wrdata_reg(1);
carrier_info_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_info_ctrl_reserved_int <= wrdata_reg(31 downto 3);
end if;
rddata_reg(0) <= carrier_info_ctrl_led_green_int;
rddata_reg(1) <= carrier_info_ctrl_led_red_int;
rddata_reg(2) <= carrier_info_ctrl_dac_clr_n_int;
rddata_reg(31 downto 3) <= carrier_info_ctrl_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_info_rst_fmc0_n_load_o <= '1';
carrier_info_rst_reserved_int <= wrdata_reg(31 downto 1);
end if;
rddata_reg(0) <= carrier_info_rst_fmc0_n_i;
rddata_reg(31 downto 1) <= carrier_info_rst_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- PCB revision
-- Reserved register
-- Carrier type
-- FMC presence
-- GN4142 core P2L PLL status
-- System clock PLL status
-- DDR3 calibration status
-- Reserved
-- Green LED
carrier_info_ctrl_led_green_o <= carrier_info_ctrl_led_green_int;
-- Red LED
carrier_info_ctrl_led_red_o <= carrier_info_ctrl_led_red_int;
-- DAC clear
carrier_info_ctrl_dac_clr_n_o <= carrier_info_ctrl_dac_clr_n_int;
-- Reserved
carrier_info_ctrl_reserved_o <= carrier_info_ctrl_reserved_int;
-- State of the reset line
carrier_info_rst_fmc0_n_o <= wrdata_reg(0);
-- Reserved
carrier_info_rst_reserved_o <= carrier_info_rst_reserved_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/rtl/circular_buffer.vhd
View file @ d463d198
......@@ -17,17 +17,17 @@
-- o The data_formatting unit is writing 128-bit long timestamps, using a WISHBONE |
-- classic interface. The unit implements a WISHBONE classic slave. |
-- As figure 1 indicates, from this side the memory is of size: 255 * 128. |
-- o The GNUM/VME core is reading 32-bit words. Readings take place using pipelined |
-- WISHBONE interface. For the PCi-e interface, Direct Memory Access can take |
-- place on this side. The unit implements the WISHBONE pipelined slave. |
-- o The GN4124/VME core is reading 32-bit words. Readings take place using |
-- pipelined WISHBONE interface. For the PCi-e interface, Direct Memory Access can|
-- take place on this side. The unit implements the WISHBONE pipelined slave. |
-- As figure 1 indicates, from this side the memory is of size: 1024 * 32. |
-- |
-- Note also that in principle the data_formatting unit is only writing in the RAM |
-- and the GNUM core is only reading from it. |
-- and the GN4124/VME core is only reading from it. |
-- |
-- |
-- RAM as seen from the RAM as seen from the |
-- data_formatting unit GNUM/VME core |
-- data_formatting unit GN4124/VME core |
-- ____________________________________________________________ _______________ |
-- 0 | 128 bits | 0 | 32 bits | |
-- |____________________________________________________________| |_______________| |
......@@ -115,7 +115,7 @@ entity circular_buffer is
tstamp_wr_adr_i : in std_logic_vector(7 downto 0); -- adr 8 bits long 2^8 = 255
tstamp_wr_dat_i : in std_logic_vector(127 downto 0); -- timestamp 128 bits long
-- Signals from the GNUM/VME core unit (WISHBONE pipelined): timestamps reading
-- Signals from the GN4124/VME core unit (WISHBONE pipelined): timestamps reading
tdc_mem_wb_rst_i : in std_logic; -- timestamp reading WISHBONE reset
tdc_mem_wb_stb_i : in std_logic; -- timestamp reading WISHBONE strobe
tdc_mem_wb_cyc_i : in std_logic; -- timestamp reading WISHBONE cycle
......@@ -128,7 +128,7 @@ entity circular_buffer is
tstamp_wr_ack_p_o : out std_logic; -- timestamp writing WISHBONE classic acknowledge
tstamp_wr_dat_o : out std_logic_vector(127 downto 0); -- not used
-- Signals to the GNUM/VME core unit (WISHBONE pipelined): timestamps reading
-- Signals to the GN4124/VME core unit (WISHBONE pipelined): timestamps reading
tdc_mem_wb_ack_o : out std_logic; -- timestamp reading WISHBONE pepelined acknowledge
tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0); -- 32 bit words
tdc_mem_wb_stall_o : out std_logic); -- timestamp reading WISHBONE pipelined stall
......@@ -282,7 +282,7 @@ begin
wea => tstamp_wr_we,
douta => tstamp_wr_dat_o, -- not used
-- Port B: attached to the GNUM/VME_core unit
-- Port B: attached to the GN4124/VME_core unit
clkb => clk_i,
addrb => tdc_mem_wb_adr_i(9 downto 0),-- 2^10 = 1024 addresses
dinb => tdc_mem_wb_dat_i, -- not used
......
hdl/rtl/clks_rsts_manager.vhd
View file @ d463d198
......@@ -12,9 +12,18 @@
---------------------------------------------------------------------------------------------------
-- File clks_rsts_manager.vhd |
-- |
-- Description Independent block that uses the clk_20m_vcxo_i to parameterize the TDC mezzanine |
-- PLL and DAC that will be used by all the other blocks. |
-- Includes input clk buffers for Xilinx Spartan6. |
-- Description Independent block that uses the clk_20m_vcxo_i to parameterize the PLL and DAC on |
-- TDC mezzanine. |
-- The PLL is programmed to generate a 125 MHz clock that arrives to to the FPGA and |
-- is used by all the other units of the core. |
-- It is also programmed to generates a 31.25 MHz clock which is the reference clock |
-- for the ACAM chip. |
-- The registers for programming the PLL are hard-coded in this unit. |
-- |
-- The unit is also responsible for the generation of a global internal reset signal |
-- for all the rest of the core. This internal reset is triggered by a GN4124/VME |
-- interface reset or by a Power On Reset at startup. The idea is to keep this reset |
-- asserted until the 125 MHz clock signal received from the PLL is stable (PLL lock)|
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
......@@ -84,8 +93,8 @@ entity clks_rsts_manager is
pll_status_i : in std_logic; -- PLL lock detect
pll_sdo_i : in std_logic; -- not used
-- Reset signal from the PCIe/VME interface
rst_n_i : in std_logic; -- GNUM/VME interface reset
-- Reset signal from the GN4124/VME interface
rst_n_i : in std_logic; -- GN4124/VME interface reset
-- Signals from the reg_ctrl unit for the reconfiguration of the DAC
send_dac_word_p_i : in std_logic; -- pulse upon VME request for a DAC reconfiguration
......@@ -268,13 +277,13 @@ begin
-- Global Internal Reset --
---------------------------------------------------------------------------------------------------
-- The following processes generate a global internal reset signal for all the rest of the core.
-- This internal reset is triggered by a GNUM/VME interface reset or by a Power On Reset at startup.
-- This internal reset is triggered by a GN4124/VME interface reset or by a Power On Reset at startup.
-- The idea is to keep this reset asserted until the 125 MHz clock signal received from the TDC
-- mezzanine PLL is stable.
---------------------------------------------------------------------------------------------------
-- Synchronous process rst_n_i_synchronizer: Synchronization of the input reset signal rst_n_i,
-- coming from the GNUM/VME interface or a PoR, to the clk_20m_vcxo_i, using a set of 2 registers.
-- coming from the GN4124/VME interface or a PoR, to the clk_20m_vcxo_i, using a set of 2 registers.
-- Note that the removal of the reset signal is synchronised.
PoR_synchronizer: process (clk_20m_vcxo_i, rst_n_i)
begin
......@@ -305,8 +314,8 @@ begin
-- Synchronous process Global_rst_generation: Generation of a reset signal for as long as the PLL
-- on the TDC board is not locked. As soon as the pll_status is received this global internal reset
-- is released. Note that the level of the pll_status signal rather than its rising edge is used,
-- as in the case of a PCIe/VME reset during operation the PLL will remain locked, therefore no
-- as in the case of a GN4124/VME reset during operation the PLL will remain locked, therefore no
-- rising edge would be detected.
Global_rst_generation: process (clk_20m_vcxo_i)
begin
if rising_edge (clk_20m_vcxo_i) then
......@@ -410,8 +419,8 @@ begin
-- FSM for configuration of the DAC and PLL --
---------------------------------------------------------------------------------------------------
-- Configuration of the PLL on the TDC mezzanine board:
-- after the powering-up of the board or after a GN4124/VME reset (rst_n_i), or
-- after a GN4124/VME command for the reconfiguration of the DAC (send_dac_word_p_i)
---------------------------------------------------------------------------------------------------
pll_dac_initialization_seq: process (clk_20m_vcxo_i)
begin
......
hdl/rtl/data_engine.vhd
View file @ d463d198
......@@ -85,7 +85,7 @@ entity data_engine is
(clk_i : in std_logic; -- 125 MHz
rst_i : in std_logic; -- global reset
-- Signals from the reg_ctrl unit: communication with PCIe/VME for registers configuration
-- Signals from the reg_ctrl unit: communication with GN4124/VME for registers configuration
activate_acq_p_i : in std_logic; -- activates tstamps aquisition
deactivate_acq_p_i : in std_logic; -- activates configuration readings/ writings
acam_wr_config_p_i : in std_logic; -- enables writing acam_config_i values to ACAM regs 0-7, 11, 12, 14
......@@ -97,7 +97,7 @@ entity data_engine is
acam_rdbk_start01_p_i: in std_logic; -- enables reading of ACAM reg 10
acam_config_i : in config_vector; -- array keeping values for ACAM regs 0-7, 11, 12, 14
-- as received from the PCIe/VME interface
-- as received from the GN4124/VME interface
-- Signals from the acam_databus_interface unit: empty FIFO flags
acam_ef1_i : in std_logic; -- empty fifo 1 (fully synched signal; ef1 after 2 DFFs)
......@@ -119,9 +119,8 @@ entity data_engine is
acam_dat_o : out std_logic_vector(31 downto 0);-- values to write to ACAM regs
acam_we_o : out std_logic; -- WISHBONE write (enabled only for reg writings)
-- Signals to the reg_ctrl unit: communication with PCIe/VME for registers configuration
-- Signals to the reg_ctrl unit: communication with GN4124/VME for registers configuration
acam_config_rdbk_o : out config_vector; -- array keeping values read from ACAM regs 0-7, 11, 12, 14
acam_status_o : out std_logic_vector(31 downto 0);-- keeps value read from ACAM reg 12
acam_ififo1_o : out std_logic_vector(31 downto 0);-- keeps value read from ACAM reg 8
acam_ififo2_o : out std_logic_vector(31 downto 0);-- keeps value read from ACAM reg 9
acam_start01_o : out std_logic_vector(31 downto 0);-- keeps value read from ACAM reg 10
......@@ -194,7 +193,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- from the INACTIVE state modifications/readings of the ACAM configuration can be initiated;
-- all interactions here refer to transfers between the ACAM and locally this core.
-- All the interactions between the PCIe/VME interface and this core take place at the
-- All the interactions between the GN4124/VME interface and this core take place at the
-- the reg_ctrl unit.
when INACTIVE =>
-----------------------------------------------
......@@ -552,7 +551,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- data_config_decoder: according to the acam_adr this process generates the acam_dat_o output
-- with the new value to be loaded to the corresponding ACAM reg. The values come from the
-- acam_config_i vector that keeps what has been loaded from the GN4124 interface.
data_config_decoder: process(acam_adr, engine_st, acam_config_i, reset_word)
begin
......@@ -610,7 +609,6 @@ begin
-- config regs&FIFOs, but this option is not used
---------------------------------------------------------------------------------------------------
-- Aquisition of ACAM Timestamps or Reedback Registers --
---------------------------------------------------------------------------------------------------
......@@ -708,7 +706,6 @@ begin
acam_tstamp2_ok_p_o <= '1' when (acam_ack_i ='1' and engine_st = GET_STAMP2) else '0';
acam_config_rdbk_o <= acam_config_rdbk;
acam_status_o <= acam_config_rdbk(9);
end architecture rtl;
......
hdl/rtl/data_formatting.vhd
View file @ d463d198
......@@ -89,7 +89,7 @@ entity data_formatting is
-- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO2
-- Signals from the reg_ctrl unit
dacapo_c_rst_p_i : in std_logic; -- instruction from PCIe/VME to clear dacapo flag
dacapo_c_rst_p_i : in std_logic; -- instruction from GN4124/VME to clear dacapo flag
-- Signals from the one_hz_gen unit
local_utc_i : in std_logic_vector(31 downto 0); -- local UTC time
......@@ -118,7 +118,7 @@ entity data_formatting is
-- Signal to the reg_ctrl unit
wr_index_o : out std_logic_vector(31 downto 0)); -- index of last byte written
-- note that the index is provided
-- #bytes, as the PCIe/VME expects
-- #bytes, as the GN4124/VME expects
-- (not in #128-bits-words)
end data_formatting;
......@@ -136,7 +136,7 @@ architecture rtl of data_formatting is
signal acam_start_nb : std_logic_vector(7 downto 0);
-- timestamp manipulations
signal un_acam_start_nb, un_clk_i_cycles_offset : unsigned(31 downto 0);
signal un_nb_of_retrig, un_retrig_nb_offset : unsigned(31 downto 0);
signal un_roll_over, un_nb_of_retrig, un_retrig_nb_offset : unsigned(31 downto 0);
signal un_nb_of_cycles, un_retrig_from_roll_over : unsigned(31 downto 0);
signal acam_start_nb_32 : std_logic_vector(31 downto 0);
-- final timestamp fields
......@@ -148,6 +148,8 @@ architecture rtl of data_formatting is
signal dacapo_counter : unsigned(19 downto 0);
signal wr_index : unsigned(7 downto 0);
-- coarse time calculations
signal tstamp_on_first_retrig_case1 : std_logic;
signal tstamp_on_first_retrig_case2 : std_logic;
signal un_previous_clk_i_cycles_offset : unsigned(31 downto 0);
signal un_previous_retrig_nb_offset : unsigned(31 downto 0);
signal un_previous_roll_over_nb : unsigned(31 downto 0);
......@@ -205,7 +207,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- tstamp_wr_wb_adr: the process keeps track of the place in the memory the next timestamp is to be
-- written; wr_index indicates which one is the next address to write to.
-- The index is also used by the PCIe host to configure the DMA coherently (DMALENR register)
-- The index is also used by the GN4124 host to configure the DMA coherently (DMALENR register)
tstamp_wr_wb_adr: process (clk_i)
begin
if rising_edge (clk_i) then
......@@ -235,7 +237,7 @@ begin
-- Da Capo flag --
---------------------------------------------------------------------------------------------------
-- dacapo_counter_update: the Da Capo counter indicates the number of times the circular buffer
-- has been written completely; it can be cleared by the PCIe/VME host.
-- has been written completely; it can be cleared by the GN4124/VME host.
dacapo_counter_update: process (clk_i)
begin
if rising_edge (clk_i) then
......@@ -355,12 +357,12 @@ begin
-- The following process makes essential calculations for the definition of the coarse time.
-- Regarding the signals: un_clk_i_cycles_offset, un_retrig_nb_offset, local_utc it has to be difined
-- if the values that characterize the current second or the one previous to it should be used.
-- In the case where: a timestamp came on the same retrigger after a new second
-- In the case where: a timestamp came on the same retgigger after a new second
-- (un_current_retrig_from_roll_over is 0 and un_acam_start_nb = un_current_retrig_nb_offset)
-- the values of the previous second should be used.
-- Also, according to the ACAM documentation there is an indeterminacy to whether the fine time refers
-- to the previous retrigger or the current one. The equation described on line 392 describes
-- the case where: a timestamp came on the same retrigger after a new second but the ACAM assigned
-- to the previous retrigger or the current one. The equation described on line 386 describes
-- the case where: a timestamp came on the same retgigger after a new second but the ACAM assigned
-- it to the previous retrigger (the "un_current_retrig_from_roll_over = 0" describes that a new second
-- has arrived; the "un_acam_fine_time > 6318" desribes a fine time that is referred to the previous retrigger;
-- 6318 * 81ps = 512ns which is a complete ACAM retrigger).
......
hdl/rtl/fmc_tdc_core.vhd
View file @ d463d198
This diff is collapsed.
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ d463d198
This diff is collapsed.
hdl/rtl/irq_generator.vhd
View file @ d463d198
......@@ -14,14 +14,15 @@
-- |
-- Description Interrupts generator: the unit generates three interrups: |
-- |
-- o irq_tstamp_p_o is a 1-clk_i-long pulse generated when the amount of timestamps|
-- written in the circular_buffer, since the last interrupt or since the startup |
-- of the aquisition,exceeds the PCIe/VME settable threshold irq_tstamp_threshold|
-- o irq_tstamp_p_o is a 1-clk_i-long pulse generated when the amount of |
-- timestamps written in the circular_buffer, since the last interrupt or since |
-- the startup of the aquisition, exceeds the GN4124/VME settable threshold |
-- irq_tstamp_threshold. |
-- |
-- o irq_time_p_o is a 1-clk_i-long pulse generated when some timestamps have been |
-- written in the circular_buffer (>=1 timestamp) and the amount of time passed |
-- since the last interrupt or since the aquisition startup, exceeds the PCIe/VME|
-- settable threshold irq_time_threshold |
-- since the last interrupt or since the aquisition startup, exceeds the |
-- GN4124/VME settable threshold irq_time_threshold. The threshold is in ms. |
-- |
-- o irq_acam_err_p_o is a 1-clk_i-long pulse generated when the ACAM Hit FIFOS are|
-- full (according to ACAM configuration register 11) |
......@@ -80,10 +81,10 @@ entity irq_generator is
-- INPUTS
-- Signal from the clks_rsts_manager
(clk_i : in std_logic; -- 125 MHz clk
rst_i : in std_logic; -- global reset, synched to clk_i
rst_i : in std_logic; -- global reset
irq_tstamp_threshold_i : in std_logic_vector(g_width-1 downto 0); -- PCIe/VME settable threshold
irq_time_threshold_i : in std_logic_vector(g_width-1 downto 0); -- PCIe/VME settable threshold
irq_tstamp_threshold_i : in std_logic_vector(g_width-1 downto 0); -- GN4124/VME settable threshold
irq_time_threshold_i : in std_logic_vector(g_width-1 downto 0); -- GN4124/VME settable threshold
-- Signal from the acam_timecontrol_interface
acam_errflag_r_edge_p_i : in std_logic; -- ACAM ErrFlag rising edge; through the ACAM config reg 11
......@@ -96,9 +97,6 @@ entity irq_generator is
-- Signals from the data_formatting unit
tstamp_wr_p_i : in std_logic; -- pulse upon storage of a new timestamp
-- Signal from the one_hz_gen unit (currently not used)
one_hz_p_i : in std_logic; -- pulse upon new second arrival
-- OUTPUTS
-- Signals to the wb_irq_controller
......
hdl/rtl/leds_manager.vhd
View file @ d463d198
......@@ -63,6 +63,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific libraries
library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.gencores_pkg.all;
......@@ -108,8 +109,10 @@ end leds_manager;
--=================================================================================================
architecture rtl of leds_manager is
signal tdc_led_blink_done : std_logic;
signal visible_blink_length : std_logic_vector(g_width-1 downto 0);
signal tdc_led_blink_done : std_logic;
signal visible_blink_length : std_logic_vector(g_width-1 downto 0);
-- signal rst_n, blink_led1, blink_led2 : std_logic;
-- signal blink_led3, blink_led4, blink_led5 : std_logic;
begin
......@@ -148,14 +151,62 @@ begin
-- TDC FRONT PANEL LEDs 2-6 --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
lad_1to5_outputs: process (clk_i)
-- rst_n <= not(rst_i);
-- cmp_extend_ch1_pulse: gc_extend_pulse
-- generic map
-- (g_width => 5000000)
-- port map
-- (clk_i => clk_i,
-- rst_n_i => rst_n,
-- pulse_i => fordebug_i(0),
-- extended_o => blink_led1);
-- -- -- -- -- --
-- cmp_extend_ch2_pulse: gc_extend_pulse
-- generic map
-- (g_width => 5000000)
-- port map
-- (clk_i => clk_i,
-- rst_n_i => rst_n,
-- pulse_i => fordebug_i(1),
-- extended_o => blink_led2);
-- -- -- -- -- --
-- cmp_extend_ch3_pulse: gc_extend_pulse
-- generic map
-- (g_width => 5000000)
-- port map
-- (clk_i => clk_i,
-- rst_n_i => rst_n,
-- pulse_i => fordebug_i(2),
-- extended_o => blink_led3);
-- -- -- -- -- --
-- cmp_extend_ch4_pulse: gc_extend_pulse
-- generic map
-- (g_width => 5000000)
-- port map
-- (clk_i => clk_i,
-- rst_n_i => rst_n,
-- pulse_i => fordebug_i(3),
-- extended_o => blink_led4);
-- -- -- -- -- --
-- cmp_extend_ch5_pulse: gc_extend_pulse
-- generic map
-- (g_width => 5000000)
-- port map
-- (clk_i => clk_i,
-- rst_n_i => rst_n,
-- pulse_i => fordebug_i(4),
-- extended_o => blink_led5);
-- -- -- -- -- --
led_1to5_outputs: process (clk_i)
begin
if rising_edge (clk_i) then
tdc_led_trig5_o <= acam_inputs_en_i(4) and acam_inputs_en_i(7);
tdc_led_trig4_o <= acam_inputs_en_i(3) and acam_inputs_en_i(7);
tdc_led_trig3_o <= acam_inputs_en_i(2) and acam_inputs_en_i(7);
tdc_led_trig2_o <= acam_inputs_en_i(1) and acam_inputs_en_i(7);
tdc_led_trig1_o <= acam_inputs_en_i(0) and acam_inputs_en_i(7);
tdc_led_trig1_o <= acam_inputs_en_i(0) and acam_inputs_en_i(7);-- and blink_led1;
tdc_led_trig2_o <= acam_inputs_en_i(1) and acam_inputs_en_i(7);-- and blink_led2;
tdc_led_trig3_o <= acam_inputs_en_i(2) and acam_inputs_en_i(7);-- and blink_led3;
tdc_led_trig4_o <= acam_inputs_en_i(3) and acam_inputs_en_i(7);-- and blink_led4;
tdc_led_trig5_o <= acam_inputs_en_i(4) and acam_inputs_en_i(7);-- and blink_led5;
end if;
end process;
......@@ -164,4 +215,4 @@ begin
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
\ No newline at end of file
hdl/rtl/one_hz_gen.vhd
View file @ d463d198
......@@ -74,7 +74,7 @@ entity one_hz_gen is
-- Signals from the reg_ctrl unit
load_utc_p_i : in std_logic; -- enables loading of the local UTC time with starting_utc_i value
starting_utc_i : in std_logic_vector(g_width-1 downto 0); -- value coming from the PCIe/VME
starting_utc_i : in std_logic_vector(g_width-1 downto 0); -- value coming from the GN4124/VME
pulse_delay_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods phase delay
-- with respect to reference clock
......
hdl/rtl/reg_ctrl.vhd
View file @ d463d198
......@@ -12,9 +12,9 @@
---------------------------------------------------------------------------------------------------
-- File reg_ctrl.vhd |
-- |
-- Description Interfaces with the PCIe/VME core for the configuration of the ACAM chip and of |
-- the TDC core. Data transfers take place between the PCIe/VME interface and locally|
-- the TDC core. The unit implements a WISHBONE slave. |
-- Description Interfaces with the GN4124/VME core for the configuration of the ACAM chip and of |
-- the TDC core. Data transfers take place between the GN4124/VME interface and |
-- locally the TDC core. The unit implements a WISHBONE slave. |
-- |
-- Through WISHBONE writes, the unit receives: |
-- o the ACAM configuration registers which are then made available to the |
......@@ -88,16 +88,15 @@ entity reg_ctrl is
(clk_i : in std_logic; -- 125 MHz
rst_i : in std_logic; -- global reset, synched to clk_i
-- Signals from the GNUM/VME_core unit: WISHBONE for regs transfer
-- Signals from the GN4124/VME_core unit: WISHBONE for regs transfer
tdc_config_wb_adr_i : in std_logic_vector(g_span-1 downto 0); -- WISHBONE address
tdc_config_wb_cyc_i : in std_logic; -- WISHBONE cycle
tdc_config_wb_dat_i : in std_logic_vector(g_width-1 downto 0); -- WISHBONE data in
tdc_config_wb_stb_i : in std_logic; -- WISHBONE strobe
tdc_config_wb_we_i : in std_logic; -- WISHBONE write enable
-- Signals from the data_engine unit: config regs readback from the ACAM
-- Signals from the data_engine unit: configuration regs read back from the ACAM
acam_config_rdbk_i : in config_vector; -- array keeping values read back from ACAM regs 0-7, 11, 12, 14
acam_status_i : in std_logic_vector(g_width-1 downto 0); -- keeps value read back from ACAM reg 12
acam_ififo1_i : in std_logic_vector(g_width-1 downto 0); -- keeps value read back from ACAM reg 8; for debug reasons only
acam_ififo2_i : in std_logic_vector(g_width-1 downto 0); -- keeps value read back from ACAM reg 9; for debug reasons only
acam_start01_i : in std_logic_vector(g_width-1 downto 0); -- keeps value read back from ACAM reg 10; for debug reasons only
......@@ -114,7 +113,7 @@ entity reg_ctrl is
-- OUTPUTS
-- Signals to the GNUM/VME_core unit: WISHBONE for regs transfer
-- Signals to the GN4124/VME_core unit: WISHBONE for regs transfer
tdc_config_wb_ack_o : out std_logic; -- WISHBONE acknowledge
tdc_config_wb_dat_o : out std_logic_vector(g_width-1 downto 0); -- WISHBONE data out
......@@ -169,7 +168,7 @@ architecture rtl of reg_ctrl is
signal dac_word : std_logic_vector(23 downto 0);
signal pulse_extender_en : std_logic;
signal pulse_extender_c : std_logic_vector(2 downto 0);
signal dat_out, dat_out_pipe0 : std_logic_vector(g_span-1 downto 0);
signal dat_out : std_logic_vector(g_span-1 downto 0);
signal tdc_config_wb_ack_o_pipe0 : std_logic;
......@@ -181,11 +180,11 @@ begin
reg_adr <= tdc_config_wb_adr_i(7 downto 0); -- we are interested in addresses 0:5000 to 0:50FC
---------------------------------------------------------------------------------------------------
-- WISHBONE ACK to GNUM/VME_core --
-- WISHBONE ACK to GN4124/VME_core --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- TDCconfig_ack_generator: generation of the WISHBONE acknowledge signal for the
-- interactions with the PCIe/VME_core.
-- interactions with the GN4124/VME_core.
TDCconfig_ack_generator: process (clk_i)
begin
......@@ -208,7 +207,7 @@ begin
-- Reception of ACAM Configuration Registers --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- ACAM_config_reg_reception: reception from the PCIe/VME interface of the configuration registers
-- ACAM_config_reg_reception: reception from the GN4124/VME interface of the configuration registers
-- to be loaded to the ACAM chip. The received data is stored in the acam_config vector which is
-- input to the data_engine and the acam_databus_interface units for the further transfer to the
-- ACAM chip.
......@@ -285,12 +284,12 @@ begin
-- Reception of TDC core Configuration Registers --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- TDCcore_config_reg_reception: reception from the PCIe/VME interface of the configuration
-- TDCcore_config_reg_reception: reception from the GN4124/VME interface of the configuration
-- registers to be loaded locally.
-- The following information is received:
-- o acam_inputs_en : for the activation of the TDC input channels
-- o irq_tstamp_threshold : for the activation of PCIe/VME interrupts based on the number of timestamps
-- o irq_time_threshold : for the activation of PCIe/VME interrupts based on the time elapsed
-- o irq_tstamp_threshold : for the activation of GN4124/VME interrupts based on the number of timestamps
-- o irq_time_threshold : for the activation of GN4124/VME interrupts based on the time elapsed
-- o starting_utc : definition of the current UTC time
-- o starting_utc : definition of the current UTC time
-- o one_hz_phase : eva: think it s not used
......@@ -356,7 +355,7 @@ begin
-- Reception of TDC core Control Register --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- TDCcore_ctrl_reg_reception: reception from the PCIe/VME interface of the control register that
-- TDCcore_ctrl_reg_reception: reception from the GN4124/VME interface of the control register that
-- defines the action to be taken by the TDC core.
-- Note that only one bit of the register should be written at a time. The process receives
-- the register, defines the action to be taken and after 1 clk cycle clears the register.
......@@ -418,8 +417,9 @@ begin
---------------------------------------------------------------------------------------------------
-- Delivery of ACAM and TDC core Readback Registers --
---------------------------------------------------------------------------------------------------
-- TDCcore_ctrl_reg_reception: Delivery to the PCIe interface of all the readable registers,
-- TDCcore_ctrl_reg_reception: Delivery to the GN4124/VME interface of all the readable registers,
-- including those of the ACAM and the TDC core.
-- Note: pipelining of the address for timing/slack reasons
WISHBONEreads: process (clk_i)
begin
......@@ -434,7 +434,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
with reg_adr_pipe0 select dat_out <=
-- regs written by the PCIe/VME interface
-- regs written by the GN4124/VME interface
acam_config(0) when c_ACAM_REG0_ADR,
acam_config(1) when c_ACAM_REG1_ADR,
acam_config(2) when c_ACAM_REG2_ADR,
......@@ -461,7 +461,7 @@ begin
acam_config_rdbk_i(8) when c_ACAM_REG11_RDBK_ADR,
acam_config_rdbk_i(9) when c_ACAM_REG12_RDBK_ADR,
acam_config_rdbk_i(10) when c_ACAM_REG14_RDBK_ADR,
-- regs written by the PCIe/VME interface
-- regs written by the GN4124/VME interface
starting_utc when c_STARTING_UTC_ADR,
acam_inputs_en when c_ACAM_INPUTS_EN_ADR,
start_phase when c_START_PHASE_ADR,
......@@ -484,4 +484,4 @@ end architecture rtl;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
\ No newline at end of file
hdl/rtl/tdc_eic.vhd
View file @ d463d198
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC EIC
---------------------------------------------------------------------------------------
-- File : tdc_eic.vhd
-- File : output.vhd
-- Author : auto-generated by wbgen2 from tdc_eic.wb
-- Created : 01/14/14 16:24:20
-- Created : 01/21/14 15:13:26
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc_eic.wb
......
hdl/rtl/wbgen/tdc_eic.wb 0 → 100644
View file @ d463d198
peripheral {
name = "TDC EIC";
description = "FMC TDC embedded interrrupt controller.";
hdl_entity = "tdc_eic";
prefix = "tdc_eic";
irq {
name = "FMC TDC timestamps interrupt";
description = "FMC TDC timestamp interrupt (rising edge sensitive).";
prefix = "tdc_tstamps";
trigger = EDGE_RISING;
};
irq {
name = "FMC TDC time interrupt";
description = "FMC TDC time interrupt (rising edge sensitive).";
prefix = "tdc_time";
trigger = EDGE_RISING;
};
irq {
name = "FMC TDC acam error interrupt";
description = "FMC slot 1 acam error interrupt (rising edge sensitive).";
prefix = "tdc_acam_err";
trigger = EDGE_RISING;
};
};
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment