Skip to content

F
FMC TDC 1ns 5cha - Gateware
Commit dce05010 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

fmc_tdc_direct_readout: drive the FIFO write flag correctly...

parent e964d950
Hide whitespace changes
Inline Side-by-side
Showing with 17 additions and 6 deletions
hdl/wr_spec_tdc/hdl/top/spec/fmc_tdc_direct_readout.vhd
View file @ dce05010
...@@ -67,9 +67,12 @@ architecture rtl of fmc_tdc_direct_readout is ...@@ -67,9 +67,12 @@ architecture rtl of fmc_tdc_direct_readout is
signal ts_bins : std_logic_vector(17 downto 0); signal ts_bins : std_logic_vector(17 downto 0);
signal ts_edge : std_logic; signal ts_edge : std_logic;
signal ts_channel : std_logic_vector(2 downto 0); signal ts_channel : std_logic_vector(2 downto 0);
signal direct_slave_out: t_wishbone_slave_out;
begin begin
ts_channel <= direct_timestamp_i(98 downto 96); ts_channel <= direct_timestamp_i(98 downto 96);
ts_edge <= direct_timestamp_i(100); ts_edge <= direct_timestamp_i(100);
ts_seconds <= direct_timestamp_i(95 downto 64); ts_seconds <= direct_timestamp_i(95 downto 64);
...@@ -82,19 +85,21 @@ begin ...@@ -82,19 +85,21 @@ begin
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
wb_adr_i => direct_slave_i.adr(4 downto 2), wb_adr_i => direct_slave_i.adr(4 downto 2),
wb_dat_i => direct_slave_i.dat, wb_dat_i => direct_slave_i.dat,
wb_dat_o => direct_slave_o.dat, wb_dat_o => direct_slave_out.dat,
wb_cyc_i => direct_slave_i.cyc, wb_cyc_i => direct_slave_i.cyc,
wb_sel_i => direct_slave_i.sel, wb_sel_i => direct_slave_i.sel,
wb_stb_i => direct_slave_i.stb, wb_stb_i => direct_slave_i.stb,
wb_we_i => direct_slave_i.we, wb_we_i => direct_slave_i.we,
wb_ack_o => direct_slave_o.ack, wb_ack_o => direct_slave_out.ack,
wb_stall_o => direct_slave_o.stall, wb_stall_o => direct_slave_out.stall,
clk_tdc_i => clk_tdc_i, clk_tdc_i => clk_tdc_i,
regs_i => regs_in, regs_i => regs_in,
regs_o => regs_out); regs_o => regs_out);
direct_slave_o.err <= '0'; direct_slave_out.err <= '0';
direct_slave_o.rty <= '0'; direct_slave_out.rty <= '0';
direct_slave_o <= direct_slave_out;
regs_in.fifo_cycles_i <= ts_cycles; regs_in.fifo_cycles_i <= ts_cycles;
regs_in.fifo_edge_i <= '1'; regs_in.fifo_edge_i <= '1';
...@@ -102,6 +107,7 @@ begin ...@@ -102,6 +107,7 @@ begin
regs_in.fifo_channel_i <= '0'&ts_channel; regs_in.fifo_channel_i <= '0'&ts_channel;
regs_in.fifo_bins_i <= ts_bins; regs_in.fifo_bins_i <= ts_bins;
gen_channels : for i in 0 to c_num_channels-1 generate gen_channels : for i in 0 to c_num_channels-1 generate
p_dead_time : process (clk_tdc_i) p_dead_time : process (clk_tdc_i)
...@@ -139,8 +145,12 @@ begin ...@@ -139,8 +145,12 @@ begin
if rst_tdc_n_i = '0' then if rst_tdc_n_i = '0' then
regs_in.fifo_wr_req_i <= '0'; regs_in.fifo_wr_req_i <= '0';
else else
regs_in.fifo_wr_req_i <= '0';
for i in 0 to c_num_channels-1 loop for i in 0 to c_num_channels-1 loop
regs_in.fifo_wr_req_i <= c(i).fifo_wr and not regs_out.fifo_wr_full_o; if(c(i).fifo_wr = '1' and regs_out.fifo_wr_full_o = '0') then
regs_in.fifo_wr_req_i <= '1';
end if;
end loop; end loop;
end if; end if;
end if; end if;
...@@ -148,3 +158,4 @@ begin ...@@ -148,3 +158,4 @@ begin
end rtl; end rtl;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment