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FMC TDC 1ns 5cha - Gateware
Commit fdef93de authored by Evangelia Gousiou's avatar Evangelia Gousiou
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deleted scripts for ucf generation; now all the spec generic pinout comes with… 

deleted scripts for ucf generation; now all the spec generic pinout comes with the spec submodule and are applied in the syn Manifest
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hdl/scripts/fmc-tdc-v3.pins deleted 100644 → 0
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#
# Mezzanine top level pin assignment file:
# syntax: pin FMC_pin_name Core_Pin_name IO_Standard
# % is replaced with FMC number if the carrier supports more than 1 mezzanine
#
mezzanine fmc-tdc-v3
pin clk0m2c_p ft%_acam_refclk_p_i lvds_25
pin clk0m2c_n ft%_acam_refclk_n_i lvds_25
pin clk1m2c_p ft%_tdc_125m_clk_p_i lvds_25
pin clk1m2c_n ft%_tdc_125m_clk_n_i lvds_25
pin la_n30 ft%_tdc_led_trig1_o lvcmos25
pin la_p32 ft%_tdc_led_trig2_o lvcmos25
pin la_n32 ft%_tdc_led_trig3_o lvcmos25
pin la_p0 ft%_term_en_1_o lvcmos25
pin la_n0 ft%_term_en_2_o lvcmos25
pin la_p16 ft%_ef1_i lvcmos25
pin la_n16 ft%_ef2_i lvcmos25
pin la_p20 ft%_term_en_3_o lvcmos25
pin la_n20 ft%_term_en_4_o lvcmos25
pin la_p22 ft%_term_en_5_o lvcmos25
pin la_n22 ft%_tdc_led_status_o lvcmos25
pin la_p31 ft%_tdc_led_trig4_o lvcmos25
pin la_n31 ft%_tdc_led_trig5_o lvcmos25
pin la_p23 ft%_pll_sclk_o lvcmos25
pin la_n23 ft%_pll_dac_sync_n_o lvcmos25
pin la_p26 ft%_pll_cs_n_o lvcmos25
pin la_n26 ft%_cs_n_o lvcmos25
pin la_p15 ft%_err_flag_i lvcmos25
pin la_n15 ft%_int_flag_i lvcmos25
pin la_p25 ft%_start_dis_o lvcmos25
pin la_n25 ft%_stop_dis_o lvcmos25
pin la_n27 ft%_pll_sdo_i lvcmos25
pin la_n29 ft%_pll_status_i lvcmos25
pin la_p27 ft%_pll_sdi_o lvcmos25
pin la_p29 ft%_start_from_fpga_o lvcmos25
pin la_n14 ft%_data_bus_io[27] lvcmos25
pin la_p14 ft%_data_bus_io[26] lvcmos25
pin la_n13 ft%_data_bus_io[25] lvcmos25
pin la_p13 ft%_data_bus_io[24] lvcmos25
pin la_n11 ft%_data_bus_io[23] lvcmos25
pin la_p11 ft%_data_bus_io[22] lvcmos25
pin la_n12 ft%_data_bus_io[21] lvcmos25
pin la_p12 ft%_data_bus_io[20] lvcmos25
pin la_n10 ft%_data_bus_io[19] lvcmos25
pin la_p10 ft%_data_bus_io[18] lvcmos25
pin la_n9 ft%_data_bus_io[17] lvcmos25
pin la_p9 ft%_data_bus_io[16] lvcmos25
pin la_n7 ft%_data_bus_io[15] lvcmos25
pin la_p7 ft%_data_bus_io[14] lvcmos25
pin la_n5 ft%_data_bus_io[13] lvcmos25
pin la_p5 ft%_data_bus_io[12] lvcmos25
pin la_n8 ft%_data_bus_io[11] lvcmos25
pin la_p8 ft%_data_bus_io[10] lvcmos25
pin la_n6 ft%_data_bus_io[9] lvcmos25
pin la_p6 ft%_data_bus_io[8] lvcmos25
pin la_n1 ft%_data_bus_io[7] lvcmos25
pin la_n4 ft%_data_bus_io[6] lvcmos25
pin la_p1 ft%_data_bus_io[5] lvcmos25
pin la_p4 ft%_data_bus_io[4] lvcmos25
pin la_n3 ft%_data_bus_io[3] lvcmos25
pin la_p3 ft%_data_bus_io[2] lvcmos25
pin la_n2 ft%_data_bus_io[1] lvcmos25
pin la_p2 ft%_data_bus_io[0] lvcmos25
pin la_n19 ft%_address_o[3] lvcmos25
pin la_p19 ft%_address_o[2] lvcmos25
pin la_n18 ft%_address_o[1] lvcmos25
pin la_p18 ft%_address_o[0] lvcmos25
pin la_p21 ft%_oe_n_o lvcmos25
pin la_n17 ft%_rd_n_o lvcmos25
pin la_p17 ft%_wr_n_o lvcmos25
pin la_p33 ft%_enable_inputs_o lvcmos25
pin la_n33 ft%_mezz_one_wire_b lvcmos25
#eof
hdl/scripts/spec.pins deleted 100644 → 0
View file @ 1251d7a5
#
# Carrier FMC pins description file
#
# Syntax:
# carrier carrier_name numeber_of_fmc_slots
# pin FMC_Slot signal_name FPGA_pin
carrier spec 1
pin 0 clk1m2c_p L20 #
pin 0 clk1m2c_n L22 #
pin 0 clk0m2c_p E16 #
pin 0 clk0m2c_n F16 #
pin 0 la_p33 C19
pin 0 la_p32 B20
pin 0 la_p31 D17
pin 0 la_p30 V17
pin 0 la_p29 W17
pin 0 la_p28 Y16
pin 0 la_p27 AA18
pin 0 la_p26 Y17
pin 0 la_p25 T15
pin 0 la_p24 W14
pin 0 la_p23 AA16
pin 0 la_p22 R13
pin 0 la_p21 V13
pin 0 la_p20 R11
pin 0 la_p19 Y15
pin 0 la_p18 T12
pin 0 la_p17 Y13
pin 0 la_p16 W12
pin 0 la_p15 V11
pin 0 la_p14 AA4
pin 0 la_p13 Y9
pin 0 la_p12 T10
pin 0 la_p11 W10
pin 0 la_p10 AA8
pin 0 la_p9 Y7
pin 0 la_p8 R9
pin 0 la_p7 U9
pin 0 la_p6 Y5
pin 0 la_p5 AA6
pin 0 la_p4 T8
pin 0 la_p3 V7
pin 0 la_p2 W6
pin 0 la_p1 AA12
pin 0 la_p0 Y11
pin 0 la_n33 A19
pin 0 la_n32 A20
pin 0 la_n31 C18
pin 0 la_n30 W18
pin 0 la_n29 Y18
pin 0 la_n28 W15
pin 0 la_n27 AB18
pin 0 la_n26 AB17
pin 0 la_n25 U15
pin 0 la_n24 Y14
pin 0 la_n23 AB16
pin 0 la_n22 T14
pin 0 la_n21 W13
pin 0 la_n20 T11
pin 0 la_n19 AB15
pin 0 la_n18 U12
pin 0 la_n17 AB13
pin 0 la_n16 Y12
pin 0 la_n15 W11
pin 0 la_n14 AB4 #
pin 0 la_n13 AB9
pin 0 la_n12 U10
pin 0 la_n11 Y10
pin 0 la_n10 AB8
pin 0 la_n9 AB7
pin 0 la_n8 R8
pin 0 la_n7 V9
pin 0 la_n6 AB5 #
pin 0 la_n5 AB6 #
pin 0 la_n4 U8 #
pin 0 la_n3 W8 #
pin 0 la_n2 Y6 #
pin 0 la_n1 AB12 #
pin 0 la_n0 AB11 #
#eof
hdl/scripts/svec.pins deleted 100644 → 0
View file @ 1251d7a5
#
# Carrier FMC pins description file
#
# Syntax:
# carrier carrier_name numeber_of_fmc_slots
# pin FMC_Slot signal_name FPGA_pin
carrier svec-v0 2
pin 0 clk1m2c_p E16
pin 0 clk1m2c_n D16
pin 0 clk0m2c_p H15
pin 0 clk0m2c_n G15
pin 0 la_p33 J12
pin 0 la_p32 H11
pin 0 la_p31 L11
pin 0 la_p30 J13
pin 0 la_p29 F9
pin 0 la_p28 L12
pin 0 la_p27 M13
pin 0 la_p26 L14
pin 0 la_p25 F11
pin 0 la_p24 G10
pin 0 la_p23 M15
pin 0 la_p22 F13
pin 0 la_p21 G12
pin 0 la_p20 F15
pin 0 la_p19 G14
pin 0 la_p18 J14
pin 0 la_p17 B15
pin 0 la_p16 F19
pin 0 la_p15 H16
pin 0 la_p14 F17
pin 0 la_p13 G18
pin 0 la_p12 F21
pin 0 la_p11 G20
pin 0 la_p10 L21
pin 0 la_p9 M20
pin 0 la_p8 F23
pin 0 la_p7 G22
pin 0 la_p6 B25
pin 0 la_p5 M19
pin 0 la_p4 D24
pin 0 la_p3 E25
pin 0 la_p2 J22
pin 0 la_p1 H21
pin 0 la_p0 C16
pin 0 la_n33 H12
pin 0 la_n32 G11
pin 0 la_n31 K11
pin 0 la_n30 H13
pin 0 la_n29 E9
pin 0 la_n28 K12
pin 0 la_n27 L13
pin 0 la_n26 K14
pin 0 la_n25 E11
pin 0 la_n24 F10
pin 0 la_n23 K15
pin 0 la_n22 E13
pin 0 la_n21 F12
pin 0 la_n20 E15
pin 0 la_n19 F14
pin 0 la_n18 H14
pin 0 la_n17 A15
pin 0 la_n16 E19
pin 0 la_n15 G16
pin 0 la_n14 E17
pin 0 la_n13 F18
pin 0 la_n12 E21
pin 0 la_n11 F20
pin 0 la_n10 K21
pin 0 la_n9 L20
pin 0 la_n8 E23
pin 0 la_n7 F22
pin 0 la_n6 A25
pin 0 la_n5 L19
pin 0 la_n4 C24
pin 0 la_n3 D25
pin 0 la_n2 H22
pin 0 la_n1 G21
pin 0 la_n0 A16
pin 1 clk1m2c_p AH16
pin 1 clk1m2c_n AK16
pin 1 clk0m2c_p AF16
pin 1 clk0m2c_n AG16
pin 1 la_p33 AA19
pin 1 la_p32 W19
pin 1 la_p31 Y21
pin 1 la_p30 W20
pin 1 la_p29 AC24
pin 1 la_p28 AA22
pin 1 la_p27 AB20
pin 1 la_p26 AC19
pin 1 la_p25 AB17
pin 1 la_p24 AB21
pin 1 la_p23 AF25
pin 1 la_p22 AE24
pin 1 la_p21 AD22
pin 1 la_p20 AE19
pin 1 la_p19 AE23
pin 1 la_p18 AE21
pin 1 la_p17 AC16
pin 1 la_p16 AB14
pin 1 la_p15 Y17
pin 1 la_p14 Y15
pin 1 la_p13 AC15
pin 1 la_p12 AE15
pin 1 la_p11 Y16
pin 1 la_p10 Y14
pin 1 la_p9 W14
pin 1 la_p8 AB12
pin 1 la_p7 AD12
pin 1 la_p6 AD10
pin 1 la_p5 AE11
pin 1 la_p4 AJ15
pin 1 la_p3 AE13
pin 1 la_p2 AC11
pin 1 la_p1 AG8
pin 1 la_p0 AJ17
pin 1 la_n33 AB19
pin 1 la_n32 Y19
pin 1 la_n31 AA21
pin 1 la_n30 Y20
pin 1 la_n29 AD24
pin 1 la_n28 AC22
pin 1 la_n27 AC20
pin 1 la_n26 AD19
pin 1 la_n25 AD17
pin 1 la_n24 AC21
pin 1 la_n23 AG25
pin 1 la_n22 AF24
pin 1 la_n21 AE22
pin 1 la_n20 AF19
pin 1 la_n19 AF23
pin 1 la_n18 AF21
pin 1 la_n17 AD16
pin 1 la_n16 AC14
pin 1 la_n15 AA17
pin 1 la_n14 AA15
pin 1 la_n13 AD15
pin 1 la_n12 AF15
pin 1 la_n11 AB16
pin 1 la_n10 AA14
pin 1 la_n9 Y13
pin 1 la_n8 AC12
pin 1 la_n7 AE12
pin 1 la_n6 AE10
pin 1 la_n5 AF11
pin 1 la_n4 AK15
pin 1 la_n3 AF13
pin 1 la_n2 AD11
pin 1 la_n1 AH8
pin 1 la_n0 AK17
#eof
hdl/scripts/ucfgen.py deleted 100644 → 0
View file @ 1251d7a5
#!/usr/bin/python
import re, os
def find_first(cond, l):
x = filter(cond, l)
if len(x):
return x[0]
else:
return None
class MezzaninePin:
def __init__(self, fmc_line=None, port_name=None, io_standard=None):
self.fmc_line = fmc_line
self.port_name = port_name
self.io_standard = io_standard
def parse(self, s):
self.fmc_line = s[1]
self.port_name = s[2]
self.io_standard= s[3]
def __str__(self):
return "FMC Pin: name %s port %s io %s" % ( self.fmc_line, self.port_name, self.io_standard)
class CarrierPin:
def __init__(self, fmc_line=None, fmc_slot=None, fpga_pin=None):
self.fmc_slot = fmc_slot
self.fmc_line = fmc_line
self.fpga_pin = fpga_pin
def parse(self, s):
self.fmc_slot = int(s[1], 10)
self.fmc_line = s[2]
self.fpga_pin = s[3]
def __str__(self):
return "Carrier Pin: name %s slot %d pin %s" % ( self.fmc_line, self.fmc_slot, self.fpga_pin)
class Carrier:
def __init__(self, name, num_slots):
self.name = name
self.num_slots = num_slots
self.pins = []
def add_pin(self, pin):
self.pins.append(pin)
class Mezzanine:
def __init__(self, name):
self.name = name
self.pins = []
def add_pin(self, pin):
self.pins.append(pin)
class UCFGen:
desc_files_path = ["./", "./pin_defs"];
def __init__(self):
self.carriers = []
self.mezzanines = []
pass
def load_desc_file(self, name):
lines=open(name,"r").read().splitlines()
print(name)
import re
m_ncomments = re.compile("^\s*([^#]+)\s*#?.*$")
car = mez = None
for l in lines:
m=re.match(m_ncomments, l)
if not m:
continue
print(m.group(1))
tokens = m.group(1).split()
command = tokens[0]
if(command == "carrier"):
car = Carrier(tokens[1], int(tokens[2], 10))
elif(command == "mezzanine"):
mez = Mezzanine(tokens[1])
elif(command == "pin"):
if(car):
p=CarrierPin()
p.parse(tokens)
car.add_pin(p)
elif(mez):
p=MezzaninePin()
p.parse(tokens)
mez.add_pin(p)
else:
raise Exception("%s: define a carrier/mezzanine before defining pins." % name)
else:
raise Exception("%s: Unrecognized command '%s'." % (name, command))
if(car):
self.carriers.append(car)
elif(mez):
self.mezzanines.append(mez)
def load_descs(self):
for d in self.desc_files_path:
if not os.path.isdir(d):
continue
for f in os.listdir(d):
fname=d+"/"+f
if(os.path.isfile(fname) and fname.endswith(".pins")):
self.load_desc_file(fname)
# print("Loaded %d carrier and %d mezzanine pin descriptions." % ( len(self.carriers), len(self.mezzanines)))
def dump_descs(self):
print("Supported carriers:")
for c in self.carriers:
print("* %s" % c.name)
print("Supported mezzanines:")
for m in self.mezzanines:
print("* %s" % m.name)
def generate_ucf(self, ucf_filename, carrier_name, slot_mappings):
f = None
try:
f = open(ucf_filename,"r")
except:
pass
ucf_user=[]
if f:
ucf_lines=f.read().splitlines()
usermode = True
for l in ucf_lines:
if(l == "# <ucfgen_start>"):
usermode = False
if(usermode):
ucf_user.append(l)
if (l == "# <ucfgen_end>"):
usermode = True
f.close()
car = find_first(lambda car: car.name == carrier_name, self.carriers)
if not car:
raise Exception("Unsupported carrier: %s" % carrier_name)
ucf_ours=[]
ucf_ours.append("")
ucf_ours.append("# <ucfgen_start>")
ucf_ours.append("")
ucf_ours.append("# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.")
slot = 0
for mapping in slot_mappings:
if not mapping:
continue
mez = find_first(lambda mez: mez.name == mapping, self.mezzanines)
if not mez:
raise Exception("Unsupported mezzanine: %s " % mapping)
print("Found mezzanine %s for slot %d." % (mez.name, slot))
if(car.num_slots > 1):
slot_str = str(slot)
else:
slot_str=""
ucf_ours.append("# ucfgen pin assignments for mezzanine %s slot %d" % (mapping, slot))
for p in mez.pins:
p_carrier = find_first(lambda f : f.fmc_line == p.fmc_line and f.fmc_slot == slot, car.pins)
if (not p_carrier):
raise Exception("Mezzanine FMC line %s not defined in the carrier description" % p.fmc_line)
print(p.port_name.replace("%", slot_str))
ucf_ours.append("NET \"%s\" LOC = \"%s\";" % ( p.port_name.replace("%", slot_str), p_carrier.fpga_pin))
ucf_ours.append("NET \"%s\" IOSTANDARD = \"%s\";" % ( p.port_name.replace("%", slot_str), p.io_standard.upper()))
slot=slot+1
ucf_ours.append("# <ucfgen_end>")
f_out = open(ucf_filename, "w")
for l in ucf_user:
f_out.write(l+"\n")
for l in ucf_ours:
f_out.write(l+"\n")
f_out.close()
print("Successfully updated UCF file %s" % ucf_filename)
def usage():
import getopt, sys
print("Ucfgen, a trivial script for automatizing Xilinx UCF FMC Mezzanine-Carrier pin assignments.\n")
print("usage: %s [options] ucf_file" % sys.argv[0])
print("Options:")
print(" -h, --help: print this message");
print(" -c, --carrier <type>: select carrier type");
print(" -m, --mezzanine <slot:type>: select <type> of mezzanine inserted into carrier slot <slot>");
print(" -l, --list: list supported carriers and mezzanines");
def main():
import getopt, sys, os
if len(sys.argv) == 1:
print("Missing command line option. Type %s --help for spiritual guidance." % sys.argv[0])
sys.exit(0)
try:
opts, args = getopt.getopt(sys.argv[1:], "hlo:m:c:", ["help", "list", "output=", "mezzanine=slot:type", "carrier="])
except getopt.GetoptError, err:
print str(err)
usage()
sys.exit(1)
output = None
carrier = None
u = UCFGen()
u.desc_files_path.append(os.path.dirname(os.path.realpath(sys.argv[0])))
u.load_descs()
mezzanines=[]
for i in range(0,128):
mezzanines.append(None)
for o, a in opts:
if o in [ "-h", "--help" ]:
usage()
sys.exit()
elif o in ("-l", "--list"):
u.dump_descs()
sys.exit()
elif o in ("-c", "--carrier"):
carrier = a
elif o in ("-m", "--mezzanine"):
t=a.split(":")
mezzanines[int(t[0])] = t[1]
else:
assert False, "unhandled option"
ucf_name = sys.argv[len(sys.argv)-1]
u.generate_ucf(ucf_name, carrier, mezzanines)
main()
#u.generate_ucf("svec_top.ucf", "svec-v0", [ "fmc-delay-v4", "fmc-delay-v4" ])
\ No newline at end of file
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