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FMC TDC 1ns 5cha - Software
Commit 05f9063b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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kernel: fixed VIC support, removed DMA buffer in the SPEC and lots of carrier-specific functions

parent c756a9bd
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Showing with 1 addition and 16 deletions
kernel/ft-core.c
View file @ 05f9063b
...@@ -246,10 +246,6 @@ int ft_probe(struct fmc_device *fmc) ...@@ -246,10 +246,6 @@ int ft_probe(struct fmc_device *fmc)
dev_info(dev, "Gateware successfully loaded \n"); dev_info(dev, "Gateware successfully loaded \n");
ret = ft->carrier_specific->init(ft);
if (ret < 0)
return ret;
ret = ft->carrier_specific->reset_core(ft); ret = ft->carrier_specific->reset_core(ft);
if (ret < 0) if (ret < 0)
return ret; return ret;
...@@ -349,9 +345,6 @@ int ft_remove(struct fmc_device *fmc) ...@@ -349,9 +345,6 @@ int ft_remove(struct fmc_device *fmc)
if (m->exit) if (m->exit)
m->exit(ft); m->exit(ft);
} }
ft->carrier_specific->exit(ft);
return 0; return 0;
} }
......
kernel/ft-irq.c
View file @ 05f9063b
...@@ -318,7 +318,7 @@ int ft_irq_init(struct fmctdc_dev *ft) ...@@ -318,7 +318,7 @@ int ft_irq_init(struct fmctdc_dev *ft)
/* pass the core's base addr as the VIC IRQ vector. */ /* pass the core's base addr as the VIC IRQ vector. */
/* fixme: vector table points to the bridge instead of the core's base address */ /* fixme: vector table points to the bridge instead of the core's base address */
ft->fmc->irq = ft->ft_core_base - 0x10000; ft->fmc->irq = ft->ft_irq_base;
ret = ft->fmc->op->irq_request(ft->fmc, ft_irq_handler, "fmc-tdc", 0); ret = ft->fmc->op->irq_request(ft->fmc, ft_irq_handler, "fmc-tdc", 0);
if (ret < 0) { if (ret < 0) {
......
kernel/ft-spec.c
View file @ 05f9063b
...@@ -28,14 +28,6 @@ static int ft_spec_reset(struct fmctdc_dev *ft) ...@@ -28,14 +28,6 @@ static int ft_spec_reset(struct fmctdc_dev *ft)
/* set local bus clock to 160 MHz. The FPGA can't handle more. */ /* set local bus clock to 160 MHz. The FPGA can't handle more. */
gennum_writel(spec, 0xE001F04C, 0x808); gennum_writel(spec, 0xE001F04C, 0x808);
/* fixme: there is no possibility of doing a software reset of the TDC core on the SPEC
other than through a Gennum config register. This begs for a fix in the
gateware! */
gennum_writel(spec, 0x00021040, GNPCI_SYS_CFG_SYSTEM);
mdelay(10);
gennum_writel(spec, 0x00025000, GNPCI_SYS_CFG_SYSTEM);
msleep(3000); /* it takes a while for the PLL to bootstrap.... or not! msleep(3000); /* it takes a while for the PLL to bootstrap.... or not!
We have no possibility to check, as the PLL status register is driven We have no possibility to check, as the PLL status register is driven
by the clock from this PLL :( */ by the clock from this PLL :( */
......
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