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FMC TDC 1ns 5cha - Software
Commit 471540f1 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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kernel: added FIFO register header

parent 9660ad52
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kernel/hw/timestamp_fifo_regs.h 0 → 100644
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/*
Register definitions for slave core: Timestamp FIFO
* File : timestamp_fifo_regs.h
* Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
* Created : Thu Aug 30 21:26:01 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_TIMESTAMP_FIFO_WB_WB
#define __WBGEN2_REGDEFS_TIMESTAMP_FIFO_WB_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Delta Timestamp Word 1 */
/* definitions for register: Delta Timestamp Word 2 */
/* definitions for register: Delta Timestamp Word 3 */
/* definitions for register: Channel Offset Word 1 */
/* definitions for register: Channel Offset Word 2 */
/* definitions for register: Channel Offset Word 3 */
/* definitions for register: Control/Status */
/* definitions for field: Delta Timestamp Ready in reg: Control/Status */
#define TSF_CSR_DELTA_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Read Delta Timestamp in reg: Control/Status */
#define TSF_CSR_DELTA_READ WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reset Sequence Counter in reg: Control/Status */
#define TSF_CSR_RST_SEQ WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Delta Timestamp Reference Channel in reg: Control/Status */
#define TSF_CSR_DELTA_REF_MASK WBGEN2_GEN_MASK(3, 3)
#define TSF_CSR_DELTA_REF_SHIFT 3
#define TSF_CSR_DELTA_REF_W(value) WBGEN2_GEN_WRITE(value, 3, 3)
#define TSF_CSR_DELTA_REF_R(reg) WBGEN2_GEN_READ(reg, 3, 3)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 0 */
/* definitions for field: The timestamp (word 0) in reg: FIFO 'Timestamp FIFO' data output register 0 */
#define TSF_FIFO_R0_TS0_MASK WBGEN2_GEN_MASK(0, 32)
#define TSF_FIFO_R0_TS0_SHIFT 0
#define TSF_FIFO_R0_TS0_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define TSF_FIFO_R0_TS0_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 1 */
/* definitions for field: The timestamp (word 1) in reg: FIFO 'Timestamp FIFO' data output register 1 */
#define TSF_FIFO_R1_TS1_MASK WBGEN2_GEN_MASK(0, 32)
#define TSF_FIFO_R1_TS1_SHIFT 0
#define TSF_FIFO_R1_TS1_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define TSF_FIFO_R1_TS1_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 2 */
/* definitions for field: The timestamp (word 2) in reg: FIFO 'Timestamp FIFO' data output register 2 */
#define TSF_FIFO_R2_TS2_MASK WBGEN2_GEN_MASK(0, 32)
#define TSF_FIFO_R2_TS2_SHIFT 0
#define TSF_FIFO_R2_TS2_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define TSF_FIFO_R2_TS2_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 3 */
/* definitions for field: The timestamp (word 3) in reg: FIFO 'Timestamp FIFO' data output register 3 */
#define TSF_FIFO_R3_TS3_MASK WBGEN2_GEN_MASK(0, 32)
#define TSF_FIFO_R3_TS3_SHIFT 0
#define TSF_FIFO_R3_TS3_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define TSF_FIFO_R3_TS3_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Timestamp FIFO' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Timestamp FIFO' control/status register */
#define TSF_FIFO_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Timestamp FIFO' control/status register */
#define TSF_FIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO clear in reg: FIFO 'Timestamp FIFO' control/status register */
#define TSF_FIFO_CSR_CLEAR_BUS WBGEN2_GEN_MASK(18, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Timestamp FIFO' control/status register */
#define TSF_FIFO_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 6)
#define TSF_FIFO_CSR_USEDW_SHIFT 0
#define TSF_FIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define TSF_FIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* [0x0]: REG Delta Timestamp Word 1 */
#define TSF_REG_DELTA1 0x00000000
/* [0x4]: REG Delta Timestamp Word 2 */
#define TSF_REG_DELTA2 0x00000004
/* [0x8]: REG Delta Timestamp Word 3 */
#define TSF_REG_DELTA3 0x00000008
/* [0xc]: REG Channel Offset Word 1 */
#define TSF_REG_OFFSET1 0x0000000c
/* [0x10]: REG Channel Offset Word 2 */
#define TSF_REG_OFFSET2 0x00000010
/* [0x14]: REG Channel Offset Word 3 */
#define TSF_REG_OFFSET3 0x00000014
/* [0x18]: REG Control/Status */
#define TSF_REG_CSR 0x00000018
/* [0x1c]: REG FIFO 'Timestamp FIFO' data output register 0 */
#define TSF_REG_FIFO_R0 0x0000001c
/* [0x20]: REG FIFO 'Timestamp FIFO' data output register 1 */
#define TSF_REG_FIFO_R1 0x00000020
/* [0x24]: REG FIFO 'Timestamp FIFO' data output register 2 */
#define TSF_REG_FIFO_R2 0x00000024
/* [0x28]: REG FIFO 'Timestamp FIFO' data output register 3 */
#define TSF_REG_FIFO_R3 0x00000028
/* [0x2c]: REG FIFO 'Timestamp FIFO' control/status register */
#define TSF_REG_FIFO_CSR 0x0000002c
#endif
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