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FMC TDC 1ns 5cha - Software
Commit d25a1ff9 authored by Federico Vaga's avatar Federico Vaga
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kernel: use the new FPGA TS fifo 

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent 020ec649
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Showing with 170 additions and 159 deletions
kernel/fmc-tdc.h
View file @ d25a1ff9
......@@ -117,8 +117,9 @@ struct ft_wr_timestamp {
uint32_t coarse;
uint32_t frac;
uint32_t channel;
uint32_t seq_id;
uint64_t gseq_id;
uint32_t hseq_id; /* hardware channel sequence id */
uint32_t dseq_id; /* channel sequence id */
uint64_t gseq_id; /* global sequence id */
};
struct ft_channel_state {
......@@ -154,7 +155,6 @@ struct fmctdc_dev {
void *carrier_data;
/* current calibration block */
struct ft_calibration calib;
struct tasklet_struct readout_tasklet;
int initialized;
/* DS18S20 temperature sensor 1-wire ID */
uint8_t ds18_id[8];
......@@ -167,8 +167,6 @@ struct fmctdc_dev {
int verbose;
struct ft_channel_state channels[FT_NUM_CHANNELS];
int wr_mode;
/* hardware buffer pointers / dacapo regs */
uint32_t cur_wr_ptr, prev_wr_ptr;
uint64_t sequence; /**< Board time-stamp sequence number */
};
......
kernel/ft-irq.c
View file @ d25a1ff9
This diff is collapsed.
kernel/ft-zio.c
View file @ d25a1ff9
......@@ -297,8 +297,6 @@ static void ft_change_flags(struct zio_obj_head *head, unsigned long mask)
ft = chan->cset->zdev->priv_d;
st = &ft->channels[chan->cset->index];
dev_dbg(&chan->head.dev, "change status flag to %d\n",
!!(chan->flags & ZIO_STATUS));
ien = ft_readl(ft, TDC_REG_INPUT_ENABLE);
if (chan->flags & ZIO_STATUS) {
/* DISABLED */
......@@ -324,8 +322,6 @@ static void ft_change_flags(struct zio_obj_head *head, unsigned long mask)
* abort() ZIO takes the cset flag. So this will not fail, but bear in
* mind that if you do this when it is assigned to a cset it wont work
*/
dev_dbg(&chan->head.dev, "trigger status 0x%lx\n",
chan->cset->ti->flags);
}
static struct zio_channel ft_chan_tmpl = {
......
kernel/hw/tdc_regs.h
View file @ d25a1ff9
......@@ -51,12 +51,22 @@
/* TDC_REG_INPUT_ENABLE bits */
#define TDC_INPUT_ENABLE_FLAG BIT(7)
#define TDC_INPUT_ENABLE_CH1 BIT(16)
#define TDC_INPUT_ENABLE_CH2 BIT(17)
#define TDC_INPUT_ENABLE_CH3 BIT(18)
#define TDC_INPUT_ENABLE_CH4 BIT(19)
#define TDC_INPUT_ENABLE_CH5 BIT(20)
#define TDC_INPUT_ENABLE_CH_ALL (TDC_INPUT_ENABLE_CH1 | \
TDC_INPUT_ENABLE_CH2 | \
TDC_INPUT_ENABLE_CH3 | \
TDC_INPUT_ENABLE_CH4 | \
TDC_INPUT_ENABLE_CH5)
/* IRQ controler registers */
#define TDC_REG_EIC_IDR 0x20
#define TDC_REG_EIC_IER 0x24
#define TDC_REG_EIC_IMR 0x28
#define TDC_REG_EIC_ISR 0x2c
#define TDC_REG_EIC_IDR 0x0
#define TDC_REG_EIC_IER 0x4
#define TDC_REG_EIC_IMR 0x8
#define TDC_REG_EIC_ISR 0xc
/* IRQ status/enable bits */
#define TDC_IRQ_TDC_TSTAMP BIT(0)
......@@ -69,6 +79,20 @@
#define TDC_EVENT_FIFO_EF_MASK 0xF000
#define TDC_EVENT_DACAPO_FLAG BIT(0)
/* FIFO registers */
#define TDC_FIFO_OFFSET 0x100
#define TDC_FIFO_LAST 0x0
#define TDC_FIFO_LAST_N 4
#define TDC_FIFO_LAST_CSR 0x10
#define TDC_FIFO_LAST_CSR_VALID BIT(0)
#define TDC_FIFO_LAST_CSR_RST_SEQ BIT(1)
#define TDC_FIFO_OUT 0x14
#define TDC_FIFO_OUT_N 4
#define TDC_FIFO_CSR 0x24
#define TDC_FIFO_CSR_EMPTY BIT(17)
#define TDC_FIFO_CSR_FULL BIT(16)
#define TDC_FIFO_CSR_USEDW
/* Carrier CSRs */
#define TDC_REG_CARRIER_CTL0 0x0 /* a.k.a. Carrier revision/PCB id reg */
#define TDC_REG_CARRIER_STATUS 0x4
......@@ -101,9 +125,9 @@
/* TDC core submodule offsets (wrs to the TDC control registers block) */
#define TDC_MEZZ_I2C_OFFSET (0x2000)
#define TDC_MEZZ_ONEWIRE_OFFSET (-0x1000)
#define TDC_MEZZ_EIC_OFFSET (0x1000)
#define TDC_MEZZ_I2C_OFFSET (0x2000)
#define TDC_MEZZ_MEM_OFFSET (0x3000)
......
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